From 05a92663bdcfadc92e47c24706be62414e19f5b1 Mon Sep 17 00:00:00 2001
From: BOTTIN Elodie <elodie.bottin@imt-atlantique.net>
Date: Wed, 26 Mar 2025 10:43:32 +0000
Subject: [PATCH] Replace operativUnit.vhd
---
.../sources_1/new/operativUnit.vhd | 278 +++++++++---------
1 file changed, 144 insertions(+), 134 deletions(-)
diff --git a/project_ecg/project_ecg.srcs/sources_1/new/operativUnit.vhd b/project_ecg/project_ecg.srcs/sources_1/new/operativUnit.vhd
index d718fda..03f6cad 100644
--- a/project_ecg/project_ecg.srcs/sources_1/new/operativUnit.vhd
+++ b/project_ecg/project_ecg.srcs/sources_1/new/operativUnit.vhd
@@ -54,27 +54,28 @@ entity operativeUnit is
end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
- type registerFileFIR1 is array(0 to 88) of signed(7 downto 0);
- type registerFileFIR2 is array(0 to 11) of signed(7 downto 0);
- type registerFileIIR1 is array(0 to 2) of signed(7 downto 0);
- type registerFileIIR2 is array(0 to 2) of signed(7 downto 0);
+ --à modifier
+ type registerFileFIR1 is array(0 to 88) of signed(9 downto 0);
+ type registerFileFIR2 is array(0 to 11) of signed(9 downto 0);
+ type registerFileIIR1 is array(0 to 2) of signed(9 downto 0);
+ type registerFileIIR2 is array(0 to 2) of signed(9 downto 0);
signal SR_coefFIR1 : registerFileFIR1;
signal SR_coefFIR2 : registerFileFIR2;
signal SR_coefIIR1 : registerFileIIR1;
signal SR_coefIIR2 : registerFileIIR2;
-
- signal SR_shiftX : __BLANK__;
- signal SR_shiftY : __BLANK__;
- signal SR_shiftZ : __BLANK__;
- signal SC_multOperand1 : signed(7 downto 0);
- signal SC_multOperand2 : signed(7 downto 0);
- signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi
- signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition
- signal SR_sum : signed(19 downto 0); -- Accumulation register
- signal SR_Y : signed(7 downto 0); -- filtered sample storage register
- signal SR_readAddress : integer range 0 to 15; -- register files read address
+ type shiftDynamic is array(natural range <>) of signed(10 downto 0);
+ signal SR_shiftX : shiftDynamic(0 to 108);
+ signal SR_shiftY : shiftDynamic(0 to 2);
+ signal SR_shiftZ : shiftDynamic(0 to 11);
+ signal SC_multOperand1 : signed(10 downto 0);
+ signal SC_multOperand2 : signed(9 downto 0);
+ signal SC_MultResult : signed(19 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(22 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(22 downto 0); -- Accumulation register
+ signal SR_Y : signed(10 downto 0); -- filtered sample storage register
+ signal SR_readAddress : integer range 0 to 88; -- register files read address
@@ -82,117 +83,117 @@ begin
-- Low-pass filter provided with octave (or Matlab ;)) command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
- SR_coefFIR1 <= (to_signed(-1, 8), -- ROM register used file to store FIR coefficients
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-3, 8),
- to_signed(-3, 8),
- to_signed(-3, 8),
- to_signed(-3, 8),
- to_signed(-4, 8),
- to_signed(-4, 8),
- to_signed(-4, 8),
- to_signed(-5, 8),
- to_signed(-5, 8),
- to_signed(-5, 8),
- to_signed(-5, 8),
- to_signed(-6, 8),
- to_signed(-6, 8),
- to_signed(-6, 8),
- to_signed(-7, 8),
- to_signed(-7, 8),
- to_signed(-7, 8),
- to_signed(-7, 8),
- to_signed(-8, 8),
- to_signed(-8, 8),
- to_signed(-8, 8),
- to_signed(-8, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-10, 8),
- to_signed(-10, 8),
- to_signed(-10, 8),
- to_signed(-10, 8),
- to_signed(502, 8),
- to_signed(-10, 8),
- to_signed(-10, 8),
- to_signed(-10, 8),
- to_signed(-10, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-9, 8),
- to_signed(-8, 8),
- to_signed(-8, 8),
- to_signed(-8, 8),
- to_signed(-8, 8),
- to_signed(-7, 8),
- to_signed(-7, 8),
- to_signed(-7, 8),
- to_signed(-7, 8),
- to_signed(-6, 8),
- to_signed(-6, 8),
- to_signed(-6, 8),
- to_signed(-5, 8),
- to_signed(-5, 8),
- to_signed(-5, 8),
- to_signed(-5, 8),
- to_signed(-4, 8),
- to_signed(-4, 8),
- to_signed(-4, 8),
- to_signed(-3, 8),
- to_signed(-3, 8),
- to_signed(-3, 8),
- to_signed(-3, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8)
+ SR_coefFIR1 <= (to_signed(-1, 10), -- ROM register used file to store FIR coefficients
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-3, 10),
+ to_signed(-3, 10),
+ to_signed(-3, 10),
+ to_signed(-3, 10),
+ to_signed(-4, 10),
+ to_signed(-4, 10),
+ to_signed(-4, 10),
+ to_signed(-5, 10),
+ to_signed(-5, 10),
+ to_signed(-5, 10),
+ to_signed(-5, 10),
+ to_signed(-6, 10),
+ to_signed(-6, 10),
+ to_signed(-6, 10),
+ to_signed(-7, 10),
+ to_signed(-7, 10),
+ to_signed(-7, 10),
+ to_signed(-7, 10),
+ to_signed(-8, 10),
+ to_signed(-8, 10),
+ to_signed(-8, 10),
+ to_signed(-8, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-10, 10),
+ to_signed(-10, 10),
+ to_signed(-10, 10),
+ to_signed(-10, 10),
+ to_signed(502, 10),
+ to_signed(-10, 10),
+ to_signed(-10, 10),
+ to_signed(-10, 10),
+ to_signed(-10, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-9, 10),
+ to_signed(-8, 10),
+ to_signed(-8, 10),
+ to_signed(-8, 10),
+ to_signed(-8, 10),
+ to_signed(-7, 10),
+ to_signed(-7, 10),
+ to_signed(-7, 10),
+ to_signed(-7, 10),
+ to_signed(-6, 10),
+ to_signed(-6, 10),
+ to_signed(-6, 10),
+ to_signed(-5, 10),
+ to_signed(-5, 10),
+ to_signed(-5, 10),
+ to_signed(-5, 10),
+ to_signed(-4, 10),
+ to_signed(-4, 10),
+ to_signed(-4, 10),
+ to_signed(-3, 10),
+ to_signed(-3, 10),
+ to_signed(-3, 10),
+ to_signed(-3, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-2, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10),
+ to_signed(-1, 10)
);
- SR_coefFIR2 <= (to_signed(-59, 8),
- to_signed(61, 8),
- to_signed(74, 8),
- to_signed(96, 8),
- to_signed(113, 8),
- to_signed(120, 8),
- to_signed(113, 8),
- to_signed(96, 8),
- to_signed(74, 8),
- to_signed(61, 8),
- to_signed(-59, 8));
+ SR_coefFIR2 <= (to_signed(-59, 10),
+ to_signed(61, 10),
+ to_signed(74, 10),
+ to_signed(96, 10),
+ to_signed(113, 10),
+ to_signed(120, 10),
+ to_signed(113, 10),
+ to_signed(96, 10),
+ to_signed(74, 10),
+ to_signed(61, 10),
+ to_signed(-59, 10));
- SR_coefIIR1 <= (to_signed(480, 8),
- to_signed(-777, 8),
- to_signed(480, 8));
+ SR_coefIIR1 <= (to_signed(480, 10),
+ to_signed(-777, 10),
+ to_signed(480, 10));
--à vérifier
- SR_coefIIR2 <= (to_signed(512, 8),
- to_signed(-777, 8),
- to_signed(449, 8));
+ SR_coefIIR2 <= (to_signed(512, 10),
+ to_signed(-777, 10),
+ to_signed(449, 10));
shift : process (I_reset, I_clock) is
begin -- process shift samples
@@ -202,14 +203,14 @@ begin
SR_shiftZ <= (others => (others => '0'));
elsif rising_edge(I_clock) then
if I_loadShiftX = '1' then
- SR_shiftX(1 to 15) <= SR_shiftX(0 to 14);
+ SR_shiftX(1 to 108) <= SR_shiftX(0 to 107);
SR_shiftX(0) <= signed(I_inputSample);
elsif I_loadShiftY = '1' then
- SR_shiftY(1 to 15) <= SR_shiftY(0 to 14);
- SR_shiftY(0) <= signed(SC_addResult);
+ SR_shiftY(1 to 2) <= SR_shiftY(0 to 1);
+ SR_shiftY(0) <= SC_addResult(19 downto 9);
elsif I_loadShiftZ = '1' then
- SR_shiftZ(1 to 15) <= SR_shiftZ(0 to 14);
- SR_shiftZ(0) <= signed(SC_addResult);
+ SR_shiftZ(1 to 11) <= SR_shiftZ(0 to 10);
+ SR_shiftZ(0) <= SC_addResult(19 downto 9);
end if;
end if;
@@ -222,17 +223,26 @@ begin
elsif rising_edge(I_clock) then
if I_initAddress = '1' then
SR_readAddress <= 0;
- elsif (I_incrAddress = '1' and SR_readAddress <= 14) then
+ elsif (I_incrAddress = '1' and SR_readAddress <= 88) then
SR_readAddress <= SR_readAddress + 1;
end if;
-
end if;
end process incr_address;
- O_processingDone <= '1' when SR_readAddress >= 14 else '0' ;
+ O_processingDoneFIR1 <= '1' when ((SR_readAddress >= 88) and (I_coeff = "00")) else '0' ;
+ O_processingDoneFIR2 <= '1' when (SR_readAddress >= 12 and I_coeff = "11") else '0' ;
+ O_processingDoneIIR1 <= '1' when (SR_readAddress >= 3 and I_coeff = "01") else '0' ;
+ O_processingDoneIIR2 <= '1' when (SR_readAddress >= 3 and I_coeff = "10") else '0' ;
+
+ SC_multOperand1 <= SR_shiftX(SR_readAddress+20) when I_Samples = "00" else --11 bits
+ SR_shiftY(SR_readAddress) when I_Samples = "01" else
+ SR_shiftZ(SR_readAddress);
+
+ SC_multOperand2 <= SR_coefFIR1(SR_readAddress) when I_Coeff ="00" else -- 10 bits
+ SR_coefIIR1(SR_readAddress) when I_Coeff ="01" else
+ SR_coefIIR2(SR_readAddress) when I_Coeff = "10" else
+ SR_coefFIR2(SR_readAddress);
- SC_multOperand1 <= SR_shiftFIR1(SR_readAddress); -- 8 bits
- SC_multOperand2 <= SR_coefFIR1(SR_readAddress); -- 8 bits
SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 16 bits
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
@@ -255,10 +265,10 @@ begin
SR_Y <= (others => '0');
elsif rising_edge(I_clock) then
if I_loadY = '1' then
- if SC_addResult(6) = '1' then
- SR_Y <= SC_addResult(14 downto 7)+1;
+ if SC_addResult(8) = '1' then
+ SR_Y <= SC_addResult(19 downto 9)+1;
else
- SR_Y <= SC_addResult(14 downto 7);
+ SR_Y <= SC_addResult(19 downto 9);
end if;
end if;
end if;
--
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