diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index bcc655d66913928d7dcdede3d6b09390249d6a4f..1eeb2af442c478cf3d275e4dbc3147fe321eff5b 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -3,39 +3,40 @@
Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
-
+I_sel, I_0, I_1, I_2, I_3, I_4, I_5, : the multiplexer control signal and the inputs so that the output is updated.
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
-
+It creates a latch, which we do not want in this circuit.
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
-
+The simulation is valid, the multiplexer works as expected
## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
-
+I_clk, I_rst : the clock to be synchronous and the reset.
## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
-
+It creates a latch, which we do not want in this circuit.
## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
-
+The counter works as expected, we can validate the module.
## Question Loto 7 : Combien de processus avez-vous décris ?
-
+We have described 1 process.
## Question Loto 8 : De quel(s) type(s) sont-ils
-
+A synchronous one to both update the current state and to define the next state.
## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
-
+We could have used 2 processes : 1 synchronous to update the current state and another asynchronous one to define the next state.
## Question Loto 10 : Ce test est-il concluant ? Justifiez.
-
+The test is conclusive, we get the behaviour described by the Finite State Machine diagram.
## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
-
+Yes, the circuite is conform.
## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
-
+73 LUT and 89 Flip-Flop. We don't have any latch.
## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
+Because of the 100 MHz clock, the draw is random for a human. For a computer it is just a cycle.
diff --git a/src/automate.vhd b/src/automate.vhd
index 1ccb931d7fe12fa743f62a8460c95a6d7fb05343..25f47fa4a6c46fb030406e7694dbd54490ec10aa 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,10 +36,14 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
- __BLANK_TO_FILL__
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ SR_STATE <= st_wait_success;
+
elsif rising_edge(I_clk)then
case SR_STATE is
- case SR_STATE is
when st_wait_success =>
O_l_green <= '1';
@@ -50,9 +54,66 @@ begin
SR_STATE <= st_counting;
end if;
- when __BLANK_TO_FILL__
+ when st_counting =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '1';
+ O_store <= '0';
+ if I_button = '0' then
+ SR_STATE <= st_compar;
+ end if;
- __BLANK_TO_FILL__
+ when st_compar =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_invalide = '0' then
+ SR_STATE <= st_store;
+ else
+ SR_STATE <= st_wait_failed;
+ end if;
+
+ when st_wait_failed =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_button = '1' then
+ SR_STATE <= st_counting;
+ end if;
+
+ when st_store =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '1';
+ if I_end = '0' then
+ SR_STATE <= st_wait_success;
+ else
+ SR_STATE <= st_end_red;
+ end if;
+
+ when st_end_red =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_clk_display = '1' then
+ SR_STATE <= st_end_green;
+ end if;
+
+ when st_end_green =>
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_clk_display = '0' then
+ SR_STATE <= st_end_red;
+ end if;
+
+ when others =>
+ SR_STATE <= st_wait_success;
end case;
end if;
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 7962a902901eb77362e130eb770ac5481684623d..47ddc73f40ce04f95083b3fa3ed344873f746fdf 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -20,15 +20,22 @@ architecture modulo6_a of compteur_modulo6 is
begin
- process (_BLANK_)
+ process (I_clk, I_rst)
begin
if I_rst = '1' then
- _BLANK_
+ SR_Counter <= "000";
elsif rising_edge(I_clk) then
- _BLANK_
+ if I_Block = '0' then
+ if SR_Counter = "101" then
+ SR_Counter <= "000";
+ else
+ SR_Counter <= SR_Counter + 1;
+ end if;
+ end if;
end if;
end process;
O_CounterMod6 <= std_logic_vector(SR_Counter);
+
end modulo6_a;
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
index a689bef6c26f4dd324c13f5d0653dfd294f6d097..b9c1afde5716cf86248e009dc8b6ccd318aab87b 100644
--- a/src/mux6_1.vhd
+++ b/src/mux6_1.vhd
@@ -20,7 +20,29 @@ end mux6_1;
architecture a_mux6_1 of mux6_1 is
begin
-__BLANK_TO_FILL__
+ process(I_sel, I_0, I_1, I_2, I_3, I_4, I_5)
+ begin
+
+ case I_sel is
+
+ when "000" =>
+ O_mux6 <= I_0;
+ when "001" =>
+ O_mux6 <= I_1;
+ when "010" =>
+ O_mux6 <= I_2;
+ when "011" =>
+ O_mux6 <= I_3;
+ when "100" =>
+ O_mux6 <= I_4;
+ when "101" =>
+ O_mux6 <= I_5;
+ when others =>
+ O_mux6 <= I_0;
+
+ end case;
+
+ end process;
diff --git a/src/transcodeur7s_u.vhd b/src/transcodeur7s_u.vhd
index ad82269687236fcaf902f4e52a56b3efbd629e97..93304fb3e12be0eb2eeaebbf249fcb38a3e57623 100644
--- a/src/transcodeur7s_u.vhd
+++ b/src/transcodeur7s_u.vhd
@@ -39,6 +39,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
entity transcodeur7s_u is
port (