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Commit 045e5b09 authored by KAMMOUN Yanis's avatar KAMMOUN Yanis
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-------------------------------------------------------------------------------
-- Title : firUnit
-- Project :
-------------------------------------------------------------------------------
-- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company :
-- Created : 2018-04-11
-- Last update: 2018-04-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 8 bit FIR
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-11 1.0 jnbazin Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity firUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic
);
end entity firUnit;
architecture archi_firUnit of firUnit is
component controlUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_GprocessingDone : in std_logic;
I_BprocessingDone : in std_logic;
I_AprocessingDone : in std_logic;
I_HprocessingDone : in std_logic;
O_loadShiftX : out std_logic; -- filtered sample
O_loadShiftY : out std_logic; -- filtered sample
O_loadShiftz : out std_logic; -- filtered sample
O_initAddress : out std_logic; -- Control signal to initialize register read address
O_incrAddress : out std_logic; -- Control signal to increment register read address
O_initSum : out std_logic; -- Control signal to initialize the MAC register
O_loadSum : out std_logic; -- Control signal to load the MAC register;
O_loadY : out std_logic; -- Control signal to load Y register
O_FilteredSampleValid : out std_logic; -- Data valid signal for filtered sample
O_samples : out std_logic_vector(1 to 0); -- Data signal to select samples
O_coeffs : out std_logic_vector(1 to 0)); -- Data signal to select coefficients
end component controlUnit;
component operativeUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
I_loadShiftX : in std_logic; -- filtered sample
I_loadShiftY : in std_logic; -- filtered sample
I_loadShiftz : in std_logic; -- filtered sample
I_initAddress : in std_logic; -- Control signal to initialize register read address
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register
I_samples : in std_logic_vector(1 to 0); -- Data signal to select X or Y samples (and B or A coefficients)
I_coeffs : in std_logic_vector(1 to 0); -- Data signal to select coefficients
O_GprocessingDone : out std_logic;
O_BprocessingDone : out std_logic;
O_AprocessingDone : out std_logic;
O_HprocessingDone : out std_logic;
O_Y : out std_logic_vector(10 downto 0) -- filtered sample
);
end component operativeUnit;
signal SC_GprocessingDone : std_logic;
signal SC_BprocessingDone : std_logic;
signal SC_AprocessingDone : std_logic;
signal SC_HprocessingDone : std_logic;
signal SC_loadShiftX : std_logic;
signal SC_loadShiftY : std_logic;
signal SC_loadShiftZ : std_logic;
signal SC_initAddress : std_logic;
signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic;
signal SC_loadSum : std_logic;
signal SC_loadY : std_logic;
signal SC_samples : std_logic_vector(1 to 0);
signal SC_coeffs : std_logic_vector(1 to 0);
begin
controlUnit_1 : entity work.controlUnit
port map (
I_clock => I_clock,
I_reset => I_reset,
I_inputSampleValid => I_inputSampleValid,
I_GprocessingDone => SC_GprocessingDone,
I_BprocessingDone => SC_BprocessingDone,
I_AprocessingDone => SC_AprocessingDone,
I_HprocessingDone => SC_HprocessingDone,
O_loadShiftX => SC_loadShiftX,
O_loadShiftY => SC_loadShiftY,
O_loadShiftZ => SC_loadShiftZ,
O_initAddress => SC_initAddress,
O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum,
O_loadSum => SC_loadSum,
O_loadY => SC_loadY,
O_samples => SC_samples,
O_coeffs => SC_coeffs,
O_FilteredSampleValid => O_FilteredSampleValid);
operativeUnit_1 : entity work.operativeUnit
port map (
I_clock => I_clock,
I_reset => I_reset,
I_inputSample => I_inputSample,
I_loadShiftX => SC_loadShiftX,
I_loadShiftY => SC_loadShiftY,
I_loadShiftZ => SC_loadShiftZ,
I_initAddress => SC_initAddress,
I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum,
I_loadSum => SC_loadSum,
I_loadY => SC_loadY,
I_samples => SC_samples,
I_coeffs => SC_coeffs,
O_GprocessingDone => SC_GprocessingDone,
O_BprocessingDone => SC_BprocessingDone,
O_AprocessingDone => SC_AprocessingDone,
O_HprocessingDone => SC_HprocessingDone,
O_Y => O_filteredSample);
end architecture archi_firUnit;
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