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VHDL/controlUnit.vhd

+-------------------------------------------------------------------------------
+-- Title      : controlUnit
+-- Project    :
+-------------------------------------------------------------------------------
+-- File       : operativeUnit.vhd
+-- Author     : Jean-Noel BAZIN  <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company    :
+-- Created    : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform   :
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Control unit of a sequential FIR filter.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2018-04-11  1.0      jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity controlUnit is
+
+  port (
+    I_clock               : in  std_logic;  -- global clock
+    I_reset               : in  std_logic;  -- asynchronous global reset
+    I_inputSampleValid    : in  std_logic;  -- Control signal to load the input sample in the sample shift register and shift the register
+    I_GprocessingDone     : in  std_logic;
+    I_BprocessingDone     : in  std_logic;
+    I_AprocessingDone     : in  std_logic;
+    I_HprocessingDone     : in  std_logic;
+    O_loadShiftX          : out std_logic;  -- filtered sample
+    O_loadShiftY          : out std_logic;  -- filtered sample
+    O_loadShiftz          : out std_logic;  -- filtered sample
+    O_initAddress         : out std_logic;  -- Control signal to initialize register read address
+    O_incrAddress         : out std_logic;  -- Control signal to increment register read address
+    O_initSum             : out std_logic;  -- Control signal to initialize the MAC register
+    O_loadSum             : out std_logic;  -- Control signal to load the MAC register;
+    O_loadY               : out std_logic;  -- Control signal to load Y register
+    O_FilteredSampleValid : out std_logic;  -- Data valid signal for filtered sample
+    O_samples             : out std_logic_vector(1 to 0);   -- Data signal to select samples 
+    O_coeffs              : out std_logic_vector(1 to 0) -- Data signal to select coefficients
+    );
+
+end entity controlUnit;
+architecture archi_operativeUnit of controlUnit is
+
+
+  type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP_1,END_LOOP_1, PROCESSING_LOOP_2, END_LOOP_2, PROCESSING_LOOP_3, END_LOOP_3, PROCESSING_LOOP_4, OUTPUT, WAIT_END_SAMPLE);  -- state list
+  signal SR_presentState : T_state;
+  signal SR_futurState   : T_state;
+
+begin
+
+
+  process (I_clock, I_reset) is
+    begin
+      if I_reset = '1' then               -- asynchronous reset (active high)
+        SR_presentState <= WAIT_SAMPLE;
+      elsif rising_edge(I_clock) then     -- rising clock edge
+        SR_presentState <= SR_futurState;
+      end if;
+    end process;
+  
+ 
+  -- Next state logic process
+  process (SR_presentState, I_inputSampleValid, I_GprocessingDone, I_BprocessingDone, I_AprocessingDone, I_HprocessingDone) is
+    begin
+      case SR_presentState is
+  
+        when WAIT_SAMPLE =>
+          if I_inputSampleValid = '1' then
+            SR_futurState <= STORE;
+          else
+            SR_futurState <= WAIT_SAMPLE;
+          end if;
+  
+        when STORE =>
+          O_samples <= "00";
+          O_coeffs  <= "00";
+          SR_futurState <= PROCESSING_LOOP_1;
+  
+        when PROCESSING_LOOP_1 =>
+          if I_GprocessingDone = '1' then
+            SR_futurState <= END_LOOP_1;
+          else
+            SR_futurState <= PROCESSING_LOOP_1;
+          end if;
+          
+        when END_LOOP_1 =>
+          O_samples <= "01";
+          O_coeffs  <= "01";
+          SR_futurState <= PROCESSING_LOOP_2;
+          
+        when PROCESSING_LOOP_2 =>
+          if I_BprocessingDone = '1' then
+            SR_futurState <= END_LOOP_2;
+          else
+            SR_futurState <= PROCESSING_LOOP_2;
+          end if;
+    
+        when END_LOOP_2 =>
+          O_samples <= "10";
+          O_coeffs  <= "10";
+          SR_futurState <= PROCESSING_LOOP_3;
+          
+        when PROCESSING_LOOP_3 =>
+          if I_AprocessingDone = '1' then
+            SR_futurState <= END_LOOP_3;
+          else
+            SR_futurState <= PROCESSING_LOOP_3;
+          end if;
+          
+        when END_LOOP_3 =>
+          O_samples <= "10";
+          O_coeffs  <= "11";
+          SR_futurState <= PROCESSING_LOOP_4;
+          
+        when PROCESSING_LOOP_4 =>
+          if I_AprocessingDone = '1' then
+            SR_futurState <= OUTPUT;
+          else
+            SR_futurState <= PROCESSING_LOOP_3;
+          end if;
+          
+        when OUTPUT =>
+          SR_futurState <= WAIT_END_SAMPLE;
+  
+        when WAIT_END_SAMPLE =>
+          if I_inputSampleValid = '0' then
+            SR_futurState <= WAIT_SAMPLE;
+          else
+            SR_futurState <= WAIT_END_SAMPLE;
+          end if;
+  
+        when others =>
+          SR_futurState <= WAIT_SAMPLE;
+      end case;
+    end process;
+  
+  -- Output logic
+  O_loadShiftX          <= '1' when SR_presentState = STORE else '0';
+  O_loadShiftY          <= '1' when SR_presentState = END_LOOP_1 else '0';
+  O_loadShiftZ          <= '1' when SR_presentState = END_LOOP_2 else '0';
+  O_initAddress         <= '1' when (SR_presentState = STORE OR SR_presentState = END_LOOP_1 OR SR_presentState = END_LOOP_2 OR SR_presentState = END_LOOP_3) else '0';
+  O_incrAddress         <= '1' when (SR_presentState = PROCESSING_LOOP_1 OR SR_presentState = PROCESSING_LOOP_2 OR SR_presentState = PROCESSING_LOOP_3 OR SR_presentState = PROCESSING_LOOP_4) else '0';
+  O_initSum             <= '1' when (SR_presentState = STORE OR SR_presentState = END_LOOP_1 OR SR_presentState = END_LOOP_3) else '0';
+  O_loadSum             <= '1' when (SR_presentState = PROCESSING_LOOP_1 OR SR_presentState = PROCESSING_LOOP_2 OR SR_presentState = PROCESSING_LOOP_3 OR SR_presentState = PROCESSING_LOOP_4) else '0';
+  O_loadY               <= '1' when SR_presentState = OUTPUT else '0';
+  
+  --O_FilteredSampleValid <= _BLANK_;
+
+
+
+
+end architecture archi_operativeUnit;