diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 705905d8efbad8482d22e650f8cce92ef78290f4..21da15f3e1bdfbfa00939c8508c01ee8a1caca2f 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -17,6 +17,8 @@
-- Revisions :
-- Date Version Author Description
-- 2018-04-11 1.0 jnbazin Created
+-- 2025-04-09 1.1 marzel Renamed some signals and port names to match
+-- the description of lab activity
-------------------------------------------------------------------------------
library ieee;
@@ -35,7 +37,7 @@ entity controlUnit is
O_incrAddress : out std_logic; -- Control signal to increment register read address
O_initSum : out std_logic; -- Control signal to initialize the MAC register
O_loadSum : out std_logic; -- Control signal to load the MAC register;
- O_loadY : out std_logic; -- Control signal to load Y register
+ O_loadOutput : out std_logic; -- Control signal to load Y register
O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
);
@@ -44,23 +46,28 @@ architecture archi_operativeUnit of controlUnit is
type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE); -- state list
- signal SR_presentState : T_state;
- signal SR_futurState : T_state;
+ signal SR_currentState : T_state;
+ signal SR_nextState : T_state;
begin
+ -- Process to describe the state register
+ -- Current state is provide at the output of the register
+ -- and is updated with the next state at each rising edge of clock
process (_BLANK_) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
- SR_presentState <= _BLANK_
+ SR_currentState <= _BLANK_
elsif rising_edge(I_clock) then -- rising clock edge
_BLANK_
end if;
end process;
+ -- Combinatorial process computing the next state which depends on
+ -- the current state and on the inputs
process (_BLANK_) is
begin
- case SR_presentState is
+ case SR_currentState is
when WAIT_SAMPLE =>
_BLANK_
@@ -69,13 +76,15 @@ begin
end case;
end process;
- O_loadShift <= '1' when _BLANK_ ;
- O_initAddress <= '1' when _BLANK_ ;
- O_incrAddress <= '1' when _BLANK_ ;
- O_initSum <= '1' when _BLANK_ ;
- O_loadSum <= '1' when _BLANK_ ;
- O_loadY <= '1' when _BLANK_ ;
- O_FilteredSampleValid <= '1' when _BLANK_ ;
+ -- Rules to compute the outputs depending on the current state
+ -- (and on the inputs, if you want a Mealy machine).
+ O_loadShift <= '1' when _BLANK_ else '0';
+ O_initAddress <= '1' when _BLANK_ else '0';
+ O_incrAddress <= '1' when _BLANK_ else '0';
+ O_initSum <= '1' when _BLANK_ else '0';
+ O_loadSum <= '1' when _BLANK_ else '0';
+ O_loadOutput <= '1' when _BLANK_ else '0';
+ O_FilteredSampleValid <= '1' when _BLANK_ else '0';
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 2c317f0ec840bcf248f38de4cb7f766b7afb95df..00c36d01de18b6a368d7e04c10895b0d5d6e471c 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -16,6 +16,9 @@
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
+-- 2025-04-09 1.1 marzel Renamed some signals and port names to match
+-- the description of lab activity
+-- Modified the sample width to 16 bits
-- 2018-04-11 1.0 jnbazin Created
-------------------------------------------------------------------------------
@@ -28,9 +31,9 @@ entity firUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(15 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
+ O_filteredSample : out std_logic_vector(15 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic
);
@@ -49,7 +52,7 @@ architecture archi_firUnit of firUnit is
O_incrAddress : out std_logic;
O_initSum : out std_logic;
O_loadSum : out std_logic;
- O_loadY : out std_logic;
+ O_loadOutput : out std_logic;
O_FilteredSampleValid : out std_logic);
end component controlUnit;
@@ -57,15 +60,15 @@ architecture archi_firUnit of firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSample : in std_logic_vector(15 downto 0);
I_loadShift : in std_logic;
I_initAddress : in std_logic;
I_incrAddress : in std_logic;
I_initSum : in std_logic;
I_loadSum : in std_logic;
- I_loadY : in std_logic;
+ I_loadOutput : in std_logic;
O_processingDone : out std_logic;
- O_Y : out std_logic_vector(7 downto 0));
+ O_filteredSample : out std_logic_vector(15 downto 0));
end component operativeUnit;
signal SC_processingDone : std_logic;
@@ -74,7 +77,7 @@ architecture archi_firUnit of firUnit is
signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic;
signal SC_loadSum : std_logic;
- signal SC_loadY : std_logic;
+ signal SC_loadOutput : std_logic;
begin
@@ -89,7 +92,7 @@ begin
O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum,
O_loadSum => SC_loadSum,
- O_loadY => SC_loadY,
+ O_loadOutput => SC_loadOutput,
O_FilteredSampleValid => O_FilteredSampleValid);
operativeUnit_1 : entity work.operativeUnit
@@ -102,8 +105,8 @@ begin
I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum,
I_loadSum => SC_loadSum,
- I_loadY => SC_loadY,
+ I_loadOutput => SC_loadOutput,
O_processingDone => SC_processingDone,
- O_Y => O_filteredSample);
+ O_filteredSample => O_filteredSample);
end architecture archi_firUnit;
diff --git a/src/hdl/operativeUnit.v b/src/hdl/operativeUnit.v
new file mode 100644
index 0000000000000000000000000000000000000000..167baf65b9d519f5dfc3b2a0e004bb70af020cc2
--- /dev/null
+++ b/src/hdl/operativeUnit.v
@@ -0,0 +1,4199 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date : Wed Apr 9 16:08:04 2025
+// Host : marzel-XPS-13-7390-2-in-1 running 64-bit Ubuntu 22.04.5 LTS
+// Command : write_verilog
+// /home/marzel/Documents/enseignements/IMTA_ELEC_A1S2_TAF/UE_EE/SAR_TA/Filtre_NexysVideo_PROF/proj/operativeUnit.v
+// Design : operativeUnit
+// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
+// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
+// design files.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* STRUCTURAL_NETLIST = "yes" *)
+module operativeUnit
+ (I_clock,
+ I_reset,
+ I_inputSample,
+ I_loadShift,
+ I_initAddress,
+ I_incrAddress,
+ I_initSum,
+ I_loadSum,
+ I_loadOutput,
+ O_processingDone,
+ O_filteredSample);
+ input I_clock;
+ input I_reset;
+ input [15:0]I_inputSample;
+ input I_loadShift;
+ input I_initAddress;
+ input I_incrAddress;
+ input I_initSum;
+ input I_loadSum;
+ input I_loadOutput;
+ output O_processingDone;
+ output [15:0]O_filteredSample;
+
+ wire \<const0> ;
+ wire \<const1> ;
+ wire GND_2;
+ wire I_clock;
+ wire I_clock_IBUF;
+ wire I_clock_IBUF_BUFG;
+ wire I_incrAddress;
+ wire I_incrAddress_IBUF;
+ wire I_initAddress;
+ wire I_initAddress_IBUF;
+ wire I_initSum;
+ wire I_initSum_IBUF;
+ wire [15:0]I_inputSample;
+ wire [15:0]I_inputSample_IBUF;
+ wire I_loadOutput;
+ wire I_loadOutput_IBUF;
+ wire I_loadShift;
+ wire I_loadShift_IBUF;
+ wire I_loadSum;
+ wire I_loadSum_IBUF;
+ wire I_reset;
+ wire I_reset_IBUF;
+ wire [30:15]L;
+ wire [15:0]O_filteredSample;
+ wire [15:0]O_filteredSample_OBUF;
+ wire O_processingDone;
+ wire O_processingDone_OBUF;
+ wire SC_addResult_i_100_n_0;
+ wire SC_addResult_i_101_n_0;
+ wire SC_addResult_i_102_n_0;
+ wire SC_addResult_i_103_n_0;
+ wire SC_addResult_i_104_n_0;
+ wire SC_addResult_i_105_n_0;
+ wire SC_addResult_i_106_n_0;
+ wire SC_addResult_i_107_n_0;
+ wire SC_addResult_i_108_n_0;
+ wire SC_addResult_i_109_n_0;
+ wire SC_addResult_i_110_n_0;
+ wire SC_addResult_i_111_n_0;
+ wire SC_addResult_i_112_n_0;
+ wire SC_addResult_i_113_n_0;
+ wire SC_addResult_i_114_n_0;
+ wire SC_addResult_i_115_n_0;
+ wire SC_addResult_i_116_n_0;
+ wire SC_addResult_i_117_n_0;
+ wire SC_addResult_i_118_n_0;
+ wire SC_addResult_i_119_n_0;
+ wire SC_addResult_i_120_n_0;
+ wire SC_addResult_i_121_n_0;
+ wire SC_addResult_i_122_n_0;
+ wire SC_addResult_i_123_n_0;
+ wire SC_addResult_i_124_n_0;
+ wire SC_addResult_i_29_n_0;
+ wire SC_addResult_i_30_n_0;
+ wire SC_addResult_i_31_n_0;
+ wire SC_addResult_i_32_n_0;
+ wire SC_addResult_i_33_n_0;
+ wire SC_addResult_i_34_n_0;
+ wire SC_addResult_i_35_n_0;
+ wire SC_addResult_i_36_n_0;
+ wire SC_addResult_i_37_n_0;
+ wire SC_addResult_i_38_n_0;
+ wire SC_addResult_i_39_n_0;
+ wire SC_addResult_i_40_n_0;
+ wire SC_addResult_i_41_n_0;
+ wire SC_addResult_i_42_n_0;
+ wire SC_addResult_i_43_n_0;
+ wire SC_addResult_i_44_n_0;
+ wire SC_addResult_i_45_n_0;
+ wire SC_addResult_i_46_n_0;
+ wire SC_addResult_i_47_n_0;
+ wire SC_addResult_i_48_n_0;
+ wire SC_addResult_i_49_n_0;
+ wire SC_addResult_i_50_n_0;
+ wire SC_addResult_i_51_n_0;
+ wire SC_addResult_i_52_n_0;
+ wire SC_addResult_i_53_n_0;
+ wire SC_addResult_i_54_n_0;
+ wire SC_addResult_i_55_n_0;
+ wire SC_addResult_i_56_n_0;
+ wire SC_addResult_i_57_n_0;
+ wire SC_addResult_i_58_n_0;
+ wire SC_addResult_i_59_n_0;
+ wire SC_addResult_i_60_n_0;
+ wire SC_addResult_i_61_n_0;
+ wire SC_addResult_i_62_n_0;
+ wire SC_addResult_i_63_n_0;
+ wire SC_addResult_i_64_n_0;
+ wire SC_addResult_i_65_n_0;
+ wire SC_addResult_i_66_n_0;
+ wire SC_addResult_i_67_n_0;
+ wire SC_addResult_i_68_n_0;
+ wire SC_addResult_i_69_n_0;
+ wire SC_addResult_i_70_n_0;
+ wire SC_addResult_i_71_n_0;
+ wire SC_addResult_i_72_n_0;
+ wire SC_addResult_i_73_n_0;
+ wire SC_addResult_i_74_n_0;
+ wire SC_addResult_i_75_n_0;
+ wire SC_addResult_i_76_n_0;
+ wire SC_addResult_i_77_n_0;
+ wire SC_addResult_i_78_n_0;
+ wire SC_addResult_i_79_n_0;
+ wire SC_addResult_i_80_n_0;
+ wire SC_addResult_i_81_n_0;
+ wire SC_addResult_i_82_n_0;
+ wire SC_addResult_i_83_n_0;
+ wire SC_addResult_i_84_n_0;
+ wire SC_addResult_i_85_n_0;
+ wire SC_addResult_i_86_n_0;
+ wire SC_addResult_i_87_n_0;
+ wire SC_addResult_i_88_n_0;
+ wire SC_addResult_i_89_n_0;
+ wire SC_addResult_i_90_n_0;
+ wire SC_addResult_i_91_n_0;
+ wire SC_addResult_i_92_n_0;
+ wire SC_addResult_i_93_n_0;
+ wire SC_addResult_i_94_n_0;
+ wire SC_addResult_i_95_n_0;
+ wire SC_addResult_i_96_n_0;
+ wire SC_addResult_i_97_n_0;
+ wire SC_addResult_i_98_n_0;
+ wire SC_addResult_i_99_n_0;
+ wire SC_addResult_n_100;
+ wire SC_addResult_n_101;
+ wire SC_addResult_n_102;
+ wire SC_addResult_n_103;
+ wire SC_addResult_n_104;
+ wire SC_addResult_n_105;
+ wire SC_addResult_n_70;
+ wire SC_addResult_n_71;
+ wire SC_addResult_n_72;
+ wire SC_addResult_n_73;
+ wire SC_addResult_n_74;
+ wire SC_addResult_n_91;
+ wire SC_addResult_n_92;
+ wire SC_addResult_n_93;
+ wire SC_addResult_n_94;
+ wire SC_addResult_n_95;
+ wire SC_addResult_n_96;
+ wire SC_addResult_n_97;
+ wire SC_addResult_n_98;
+ wire SC_addResult_n_99;
+ wire [11:0]SC_multOperand2;
+ wire \SR_filteredSample[3]_i_2_n_0 ;
+ wire \SR_filteredSample_reg[11]_i_1_n_0 ;
+ wire \SR_filteredSample_reg[11]_i_1_n_1 ;
+ wire \SR_filteredSample_reg[11]_i_1_n_2 ;
+ wire \SR_filteredSample_reg[11]_i_1_n_3 ;
+ wire \SR_filteredSample_reg[15]_i_1_n_1 ;
+ wire \SR_filteredSample_reg[15]_i_1_n_2 ;
+ wire \SR_filteredSample_reg[15]_i_1_n_3 ;
+ wire \SR_filteredSample_reg[3]_i_1_n_0 ;
+ wire \SR_filteredSample_reg[3]_i_1_n_1 ;
+ wire \SR_filteredSample_reg[3]_i_1_n_2 ;
+ wire \SR_filteredSample_reg[3]_i_1_n_3 ;
+ wire \SR_filteredSample_reg[7]_i_1_n_0 ;
+ wire \SR_filteredSample_reg[7]_i_1_n_1 ;
+ wire \SR_filteredSample_reg[7]_i_1_n_2 ;
+ wire \SR_filteredSample_reg[7]_i_1_n_3 ;
+ wire [3:0]SR_readAddress;
+ wire \SR_readAddress[0]_i_1_n_0 ;
+ wire \SR_readAddress[1]_i_1_n_0 ;
+ wire \SR_readAddress[2]_i_1_n_0 ;
+ wire \SR_readAddress[3]_i_1_n_0 ;
+ wire \SR_readAddress[3]_i_2_n_0 ;
+ wire [15:0]\SR_shiftRegister[0] ;
+ wire [15:0]\SR_shiftRegister_reg[0] ;
+ wire [15:0]\SR_shiftRegister_reg[10] ;
+ wire [15:0]\SR_shiftRegister_reg[11] ;
+ wire [15:0]\SR_shiftRegister_reg[12] ;
+ wire [15:0]\SR_shiftRegister_reg[13] ;
+ wire [15:0]\SR_shiftRegister_reg[14] ;
+ wire [15:0]\SR_shiftRegister_reg[15] ;
+ wire [15:0]\SR_shiftRegister_reg[1] ;
+ wire [15:0]\SR_shiftRegister_reg[2] ;
+ wire [15:0]\SR_shiftRegister_reg[3] ;
+ wire [15:0]\SR_shiftRegister_reg[4] ;
+ wire [15:0]\SR_shiftRegister_reg[5] ;
+ wire [15:0]\SR_shiftRegister_reg[6] ;
+ wire [15:0]\SR_shiftRegister_reg[7] ;
+ wire [15:0]\SR_shiftRegister_reg[8] ;
+ wire [15:0]\SR_shiftRegister_reg[9] ;
+ wire [35:0]SR_sum;
+ wire \SR_sum[35]_i_1_n_0 ;
+ wire [15:0]p_0_in;
+ wire [35:0]p_1_in;
+
+ GND GND
+ (.G(\<const0> ));
+ GND GND_1
+ (.G(GND_2));
+ BUFG I_clock_IBUF_BUFG_inst
+ (.I(I_clock_IBUF),
+ .O(I_clock_IBUF_BUFG));
+ IBUF I_clock_IBUF_inst
+ (.I(I_clock),
+ .O(I_clock_IBUF));
+ IBUF I_incrAddress_IBUF_inst
+ (.I(I_incrAddress),
+ .O(I_incrAddress_IBUF));
+ IBUF I_initAddress_IBUF_inst
+ (.I(I_initAddress),
+ .O(I_initAddress_IBUF));
+ IBUF I_initSum_IBUF_inst
+ (.I(I_initSum),
+ .O(I_initSum_IBUF));
+ IBUF \I_inputSample_IBUF[0]_inst
+ (.I(I_inputSample[0]),
+ .O(I_inputSample_IBUF[0]));
+ IBUF \I_inputSample_IBUF[10]_inst
+ (.I(I_inputSample[10]),
+ .O(I_inputSample_IBUF[10]));
+ IBUF \I_inputSample_IBUF[11]_inst
+ (.I(I_inputSample[11]),
+ .O(I_inputSample_IBUF[11]));
+ IBUF \I_inputSample_IBUF[12]_inst
+ (.I(I_inputSample[12]),
+ .O(I_inputSample_IBUF[12]));
+ IBUF \I_inputSample_IBUF[13]_inst
+ (.I(I_inputSample[13]),
+ .O(I_inputSample_IBUF[13]));
+ IBUF \I_inputSample_IBUF[14]_inst
+ (.I(I_inputSample[14]),
+ .O(I_inputSample_IBUF[14]));
+ IBUF \I_inputSample_IBUF[15]_inst
+ (.I(I_inputSample[15]),
+ .O(I_inputSample_IBUF[15]));
+ IBUF \I_inputSample_IBUF[1]_inst
+ (.I(I_inputSample[1]),
+ .O(I_inputSample_IBUF[1]));
+ IBUF \I_inputSample_IBUF[2]_inst
+ (.I(I_inputSample[2]),
+ .O(I_inputSample_IBUF[2]));
+ IBUF \I_inputSample_IBUF[3]_inst
+ (.I(I_inputSample[3]),
+ .O(I_inputSample_IBUF[3]));
+ IBUF \I_inputSample_IBUF[4]_inst
+ (.I(I_inputSample[4]),
+ .O(I_inputSample_IBUF[4]));
+ IBUF \I_inputSample_IBUF[5]_inst
+ (.I(I_inputSample[5]),
+ .O(I_inputSample_IBUF[5]));
+ IBUF \I_inputSample_IBUF[6]_inst
+ (.I(I_inputSample[6]),
+ .O(I_inputSample_IBUF[6]));
+ IBUF \I_inputSample_IBUF[7]_inst
+ (.I(I_inputSample[7]),
+ .O(I_inputSample_IBUF[7]));
+ IBUF \I_inputSample_IBUF[8]_inst
+ (.I(I_inputSample[8]),
+ .O(I_inputSample_IBUF[8]));
+ IBUF \I_inputSample_IBUF[9]_inst
+ (.I(I_inputSample[9]),
+ .O(I_inputSample_IBUF[9]));
+ IBUF I_loadOutput_IBUF_inst
+ (.I(I_loadOutput),
+ .O(I_loadOutput_IBUF));
+ IBUF I_loadShift_IBUF_inst
+ (.I(I_loadShift),
+ .O(I_loadShift_IBUF));
+ IBUF I_loadSum_IBUF_inst
+ (.I(I_loadSum),
+ .O(I_loadSum_IBUF));
+ IBUF I_reset_IBUF_inst
+ (.I(I_reset),
+ .O(I_reset_IBUF));
+ OBUF \O_filteredSample_OBUF[0]_inst
+ (.I(O_filteredSample_OBUF[0]),
+ .O(O_filteredSample[0]));
+ OBUF \O_filteredSample_OBUF[10]_inst
+ (.I(O_filteredSample_OBUF[10]),
+ .O(O_filteredSample[10]));
+ OBUF \O_filteredSample_OBUF[11]_inst
+ (.I(O_filteredSample_OBUF[11]),
+ .O(O_filteredSample[11]));
+ OBUF \O_filteredSample_OBUF[12]_inst
+ (.I(O_filteredSample_OBUF[12]),
+ .O(O_filteredSample[12]));
+ OBUF \O_filteredSample_OBUF[13]_inst
+ (.I(O_filteredSample_OBUF[13]),
+ .O(O_filteredSample[13]));
+ OBUF \O_filteredSample_OBUF[14]_inst
+ (.I(O_filteredSample_OBUF[14]),
+ .O(O_filteredSample[14]));
+ OBUF \O_filteredSample_OBUF[15]_inst
+ (.I(O_filteredSample_OBUF[15]),
+ .O(O_filteredSample[15]));
+ OBUF \O_filteredSample_OBUF[1]_inst
+ (.I(O_filteredSample_OBUF[1]),
+ .O(O_filteredSample[1]));
+ OBUF \O_filteredSample_OBUF[2]_inst
+ (.I(O_filteredSample_OBUF[2]),
+ .O(O_filteredSample[2]));
+ OBUF \O_filteredSample_OBUF[3]_inst
+ (.I(O_filteredSample_OBUF[3]),
+ .O(O_filteredSample[3]));
+ OBUF \O_filteredSample_OBUF[4]_inst
+ (.I(O_filteredSample_OBUF[4]),
+ .O(O_filteredSample[4]));
+ OBUF \O_filteredSample_OBUF[5]_inst
+ (.I(O_filteredSample_OBUF[5]),
+ .O(O_filteredSample[5]));
+ OBUF \O_filteredSample_OBUF[6]_inst
+ (.I(O_filteredSample_OBUF[6]),
+ .O(O_filteredSample[6]));
+ OBUF \O_filteredSample_OBUF[7]_inst
+ (.I(O_filteredSample_OBUF[7]),
+ .O(O_filteredSample[7]));
+ OBUF \O_filteredSample_OBUF[8]_inst
+ (.I(O_filteredSample_OBUF[8]),
+ .O(O_filteredSample[8]));
+ OBUF \O_filteredSample_OBUF[9]_inst
+ (.I(O_filteredSample_OBUF[9]),
+ .O(O_filteredSample[9]));
+ OBUF O_processingDone_OBUF_inst
+ (.I(O_processingDone_OBUF),
+ .O(O_processingDone));
+ LUT3 #(
+ .INIT(8'h80))
+ O_processingDone_OBUF_inst_i_1
+ (.I0(SR_readAddress[1]),
+ .I1(SR_readAddress[3]),
+ .I2(SR_readAddress[2]),
+ .O(O_processingDone_OBUF));
+ (* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
+ DSP48E1 #(
+ .ACASCREG(0),
+ .ADREG(1),
+ .ALUMODEREG(0),
+ .AREG(0),
+ .AUTORESET_PATDET("NO_RESET"),
+ .A_INPUT("DIRECT"),
+ .BCASCREG(0),
+ .BREG(0),
+ .B_INPUT("DIRECT"),
+ .CARRYINREG(0),
+ .CARRYINSELREG(0),
+ .CREG(0),
+ .DREG(1),
+ .INMODEREG(0),
+ .MASK(48'h3FFFFFFFFFFF),
+ .MREG(0),
+ .OPMODEREG(0),
+ .PATTERN(48'h000000000000),
+ .PREG(0),
+ .SEL_MASK("MASK"),
+ .SEL_PATTERN("PATTERN"),
+ .USE_DPORT("FALSE"),
+ .USE_MULT("MULTIPLY"),
+ .USE_PATTERN_DETECT("NO_PATDET"),
+ .USE_SIMD("ONE48"))
+ SC_addResult
+ (.A({\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] }),
+ .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,SC_multOperand2}),
+ .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .C({SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum}),
+ .CARRYCASCIN(\<const0> ),
+ .CARRYIN(\<const0> ),
+ .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
+ .CEA1(\<const0> ),
+ .CEA2(\<const0> ),
+ .CEAD(\<const0> ),
+ .CEALUMODE(\<const0> ),
+ .CEB1(\<const0> ),
+ .CEB2(\<const0> ),
+ .CEC(\<const0> ),
+ .CECARRYIN(\<const0> ),
+ .CECTRL(\<const0> ),
+ .CED(\<const0> ),
+ .CEINMODE(\<const0> ),
+ .CEM(\<const0> ),
+ .CEP(\<const0> ),
+ .CLK(\<const0> ),
+ .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
+ .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .MULTSIGNIN(\<const0> ),
+ .OPMODE({\<const0> ,\<const1> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
+ .P({SC_addResult_n_70,SC_addResult_n_71,SC_addResult_n_72,SC_addResult_n_73,SC_addResult_n_74,L,SC_addResult_n_91,SC_addResult_n_92,SC_addResult_n_93,SC_addResult_n_94,SC_addResult_n_95,SC_addResult_n_96,SC_addResult_n_97,SC_addResult_n_98,SC_addResult_n_99,SC_addResult_n_100,SC_addResult_n_101,SC_addResult_n_102,SC_addResult_n_103,SC_addResult_n_104,SC_addResult_n_105}),
+ .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .RSTA(\<const0> ),
+ .RSTALLCARRYIN(\<const0> ),
+ .RSTALUMODE(\<const0> ),
+ .RSTB(\<const0> ),
+ .RSTC(\<const0> ),
+ .RSTCTRL(\<const0> ),
+ .RSTD(\<const0> ),
+ .RSTINMODE(\<const0> ),
+ .RSTM(\<const0> ),
+ .RSTP(\<const0> ));
+ LUT2 #(
+ .INIT(4'h6))
+ SC_addResult_i_1
+ (.I0(SR_readAddress[2]),
+ .I1(SR_readAddress[3]),
+ .O(SC_multOperand2[11]));
+ LUT4 #(
+ .INIT(16'hBFFD))
+ SC_addResult_i_10
+ (.I0(SR_readAddress[2]),
+ .I1(SR_readAddress[3]),
+ .I2(SR_readAddress[1]),
+ .I3(SR_readAddress[0]),
+ .O(SC_multOperand2[2]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_100
+ (.I0(\SR_shiftRegister_reg[15] [6]),
+ .I1(\SR_shiftRegister_reg[14] [6]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [6]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [6]),
+ .O(SC_addResult_i_100_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_101
+ (.I0(\SR_shiftRegister_reg[3] [5]),
+ .I1(\SR_shiftRegister_reg[2] [5]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [5]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [5]),
+ .O(SC_addResult_i_101_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_102
+ (.I0(\SR_shiftRegister_reg[7] [5]),
+ .I1(\SR_shiftRegister_reg[6] [5]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [5]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [5]),
+ .O(SC_addResult_i_102_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_103
+ (.I0(\SR_shiftRegister_reg[11] [5]),
+ .I1(\SR_shiftRegister_reg[10] [5]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [5]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [5]),
+ .O(SC_addResult_i_103_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_104
+ (.I0(\SR_shiftRegister_reg[15] [5]),
+ .I1(\SR_shiftRegister_reg[14] [5]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [5]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [5]),
+ .O(SC_addResult_i_104_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_105
+ (.I0(\SR_shiftRegister_reg[3] [4]),
+ .I1(\SR_shiftRegister_reg[2] [4]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [4]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [4]),
+ .O(SC_addResult_i_105_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_106
+ (.I0(\SR_shiftRegister_reg[7] [4]),
+ .I1(\SR_shiftRegister_reg[6] [4]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [4]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [4]),
+ .O(SC_addResult_i_106_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_107
+ (.I0(\SR_shiftRegister_reg[11] [4]),
+ .I1(\SR_shiftRegister_reg[10] [4]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [4]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [4]),
+ .O(SC_addResult_i_107_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_108
+ (.I0(\SR_shiftRegister_reg[15] [4]),
+ .I1(\SR_shiftRegister_reg[14] [4]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [4]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [4]),
+ .O(SC_addResult_i_108_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_109
+ (.I0(\SR_shiftRegister_reg[3] [3]),
+ .I1(\SR_shiftRegister_reg[2] [3]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [3]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [3]),
+ .O(SC_addResult_i_109_n_0));
+ LUT4 #(
+ .INIT(16'h581A))
+ SC_addResult_i_11
+ (.I0(SR_readAddress[3]),
+ .I1(SR_readAddress[1]),
+ .I2(SR_readAddress[2]),
+ .I3(SR_readAddress[0]),
+ .O(SC_multOperand2[1]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_110
+ (.I0(\SR_shiftRegister_reg[7] [3]),
+ .I1(\SR_shiftRegister_reg[6] [3]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [3]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [3]),
+ .O(SC_addResult_i_110_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_111
+ (.I0(\SR_shiftRegister_reg[11] [3]),
+ .I1(\SR_shiftRegister_reg[10] [3]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [3]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [3]),
+ .O(SC_addResult_i_111_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_112
+ (.I0(\SR_shiftRegister_reg[15] [3]),
+ .I1(\SR_shiftRegister_reg[14] [3]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [3]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [3]),
+ .O(SC_addResult_i_112_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_113
+ (.I0(\SR_shiftRegister_reg[3] [2]),
+ .I1(\SR_shiftRegister_reg[2] [2]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [2]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [2]),
+ .O(SC_addResult_i_113_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_114
+ (.I0(\SR_shiftRegister_reg[7] [2]),
+ .I1(\SR_shiftRegister_reg[6] [2]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [2]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [2]),
+ .O(SC_addResult_i_114_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_115
+ (.I0(\SR_shiftRegister_reg[11] [2]),
+ .I1(\SR_shiftRegister_reg[10] [2]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [2]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [2]),
+ .O(SC_addResult_i_115_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_116
+ (.I0(\SR_shiftRegister_reg[15] [2]),
+ .I1(\SR_shiftRegister_reg[14] [2]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [2]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [2]),
+ .O(SC_addResult_i_116_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_117
+ (.I0(\SR_shiftRegister_reg[3] [1]),
+ .I1(\SR_shiftRegister_reg[2] [1]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [1]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [1]),
+ .O(SC_addResult_i_117_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_118
+ (.I0(\SR_shiftRegister_reg[7] [1]),
+ .I1(\SR_shiftRegister_reg[6] [1]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [1]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [1]),
+ .O(SC_addResult_i_118_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_119
+ (.I0(\SR_shiftRegister_reg[11] [1]),
+ .I1(\SR_shiftRegister_reg[10] [1]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [1]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [1]),
+ .O(SC_addResult_i_119_n_0));
+ LUT4 #(
+ .INIT(16'hF66F))
+ SC_addResult_i_12
+ (.I0(SR_readAddress[3]),
+ .I1(SR_readAddress[1]),
+ .I2(SR_readAddress[2]),
+ .I3(SR_readAddress[0]),
+ .O(SC_multOperand2[0]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_120
+ (.I0(\SR_shiftRegister_reg[15] [1]),
+ .I1(\SR_shiftRegister_reg[14] [1]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [1]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [1]),
+ .O(SC_addResult_i_120_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_121
+ (.I0(\SR_shiftRegister_reg[3] [0]),
+ .I1(\SR_shiftRegister_reg[2] [0]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [0]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [0]),
+ .O(SC_addResult_i_121_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_122
+ (.I0(\SR_shiftRegister_reg[7] [0]),
+ .I1(\SR_shiftRegister_reg[6] [0]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [0]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [0]),
+ .O(SC_addResult_i_122_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_123
+ (.I0(\SR_shiftRegister_reg[11] [0]),
+ .I1(\SR_shiftRegister_reg[10] [0]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [0]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [0]),
+ .O(SC_addResult_i_123_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_124
+ (.I0(\SR_shiftRegister_reg[15] [0]),
+ .I1(\SR_shiftRegister_reg[14] [0]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [0]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [0]),
+ .O(SC_addResult_i_124_n_0));
+ MUXF8 SC_addResult_i_13
+ (.I0(SC_addResult_i_29_n_0),
+ .I1(SC_addResult_i_30_n_0),
+ .O(\SR_shiftRegister[0] [15]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_14
+ (.I0(SC_addResult_i_31_n_0),
+ .I1(SC_addResult_i_32_n_0),
+ .O(\SR_shiftRegister[0] [14]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_15
+ (.I0(SC_addResult_i_33_n_0),
+ .I1(SC_addResult_i_34_n_0),
+ .O(\SR_shiftRegister[0] [13]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_16
+ (.I0(SC_addResult_i_35_n_0),
+ .I1(SC_addResult_i_36_n_0),
+ .O(\SR_shiftRegister[0] [12]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_17
+ (.I0(SC_addResult_i_37_n_0),
+ .I1(SC_addResult_i_38_n_0),
+ .O(\SR_shiftRegister[0] [11]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_18
+ (.I0(SC_addResult_i_39_n_0),
+ .I1(SC_addResult_i_40_n_0),
+ .O(\SR_shiftRegister[0] [10]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_19
+ (.I0(SC_addResult_i_41_n_0),
+ .I1(SC_addResult_i_42_n_0),
+ .O(\SR_shiftRegister[0] [9]),
+ .S(SR_readAddress[3]));
+ LUT4 #(
+ .INIT(16'h1E78))
+ SC_addResult_i_2
+ (.I0(SR_readAddress[2]),
+ .I1(SR_readAddress[1]),
+ .I2(SR_readAddress[3]),
+ .I3(SR_readAddress[0]),
+ .O(SC_multOperand2[10]));
+ MUXF8 SC_addResult_i_20
+ (.I0(SC_addResult_i_43_n_0),
+ .I1(SC_addResult_i_44_n_0),
+ .O(\SR_shiftRegister[0] [8]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_21
+ (.I0(SC_addResult_i_45_n_0),
+ .I1(SC_addResult_i_46_n_0),
+ .O(\SR_shiftRegister[0] [7]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_22
+ (.I0(SC_addResult_i_47_n_0),
+ .I1(SC_addResult_i_48_n_0),
+ .O(\SR_shiftRegister[0] [6]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_23
+ (.I0(SC_addResult_i_49_n_0),
+ .I1(SC_addResult_i_50_n_0),
+ .O(\SR_shiftRegister[0] [5]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_24
+ (.I0(SC_addResult_i_51_n_0),
+ .I1(SC_addResult_i_52_n_0),
+ .O(\SR_shiftRegister[0] [4]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_25
+ (.I0(SC_addResult_i_53_n_0),
+ .I1(SC_addResult_i_54_n_0),
+ .O(\SR_shiftRegister[0] [3]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_26
+ (.I0(SC_addResult_i_55_n_0),
+ .I1(SC_addResult_i_56_n_0),
+ .O(\SR_shiftRegister[0] [2]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_27
+ (.I0(SC_addResult_i_57_n_0),
+ .I1(SC_addResult_i_58_n_0),
+ .O(\SR_shiftRegister[0] [1]),
+ .S(SR_readAddress[3]));
+ MUXF8 SC_addResult_i_28
+ (.I0(SC_addResult_i_59_n_0),
+ .I1(SC_addResult_i_60_n_0),
+ .O(\SR_shiftRegister[0] [0]),
+ .S(SR_readAddress[3]));
+ MUXF7 SC_addResult_i_29
+ (.I0(SC_addResult_i_61_n_0),
+ .I1(SC_addResult_i_62_n_0),
+ .O(SC_addResult_i_29_n_0),
+ .S(SR_readAddress[2]));
+ LUT2 #(
+ .INIT(4'h6))
+ SC_addResult_i_3
+ (.I0(SR_readAddress[1]),
+ .I1(SR_readAddress[3]),
+ .O(SC_multOperand2[9]));
+ MUXF7 SC_addResult_i_30
+ (.I0(SC_addResult_i_63_n_0),
+ .I1(SC_addResult_i_64_n_0),
+ .O(SC_addResult_i_30_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_31
+ (.I0(SC_addResult_i_65_n_0),
+ .I1(SC_addResult_i_66_n_0),
+ .O(SC_addResult_i_31_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_32
+ (.I0(SC_addResult_i_67_n_0),
+ .I1(SC_addResult_i_68_n_0),
+ .O(SC_addResult_i_32_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_33
+ (.I0(SC_addResult_i_69_n_0),
+ .I1(SC_addResult_i_70_n_0),
+ .O(SC_addResult_i_33_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_34
+ (.I0(SC_addResult_i_71_n_0),
+ .I1(SC_addResult_i_72_n_0),
+ .O(SC_addResult_i_34_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_35
+ (.I0(SC_addResult_i_73_n_0),
+ .I1(SC_addResult_i_74_n_0),
+ .O(SC_addResult_i_35_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_36
+ (.I0(SC_addResult_i_75_n_0),
+ .I1(SC_addResult_i_76_n_0),
+ .O(SC_addResult_i_36_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_37
+ (.I0(SC_addResult_i_77_n_0),
+ .I1(SC_addResult_i_78_n_0),
+ .O(SC_addResult_i_37_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_38
+ (.I0(SC_addResult_i_79_n_0),
+ .I1(SC_addResult_i_80_n_0),
+ .O(SC_addResult_i_38_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_39
+ (.I0(SC_addResult_i_81_n_0),
+ .I1(SC_addResult_i_82_n_0),
+ .O(SC_addResult_i_39_n_0),
+ .S(SR_readAddress[2]));
+ LUT4 #(
+ .INIT(16'hE997))
+ SC_addResult_i_4
+ (.I0(SR_readAddress[1]),
+ .I1(SR_readAddress[3]),
+ .I2(SR_readAddress[2]),
+ .I3(SR_readAddress[0]),
+ .O(SC_multOperand2[8]));
+ MUXF7 SC_addResult_i_40
+ (.I0(SC_addResult_i_83_n_0),
+ .I1(SC_addResult_i_84_n_0),
+ .O(SC_addResult_i_40_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_41
+ (.I0(SC_addResult_i_85_n_0),
+ .I1(SC_addResult_i_86_n_0),
+ .O(SC_addResult_i_41_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_42
+ (.I0(SC_addResult_i_87_n_0),
+ .I1(SC_addResult_i_88_n_0),
+ .O(SC_addResult_i_42_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_43
+ (.I0(SC_addResult_i_89_n_0),
+ .I1(SC_addResult_i_90_n_0),
+ .O(SC_addResult_i_43_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_44
+ (.I0(SC_addResult_i_91_n_0),
+ .I1(SC_addResult_i_92_n_0),
+ .O(SC_addResult_i_44_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_45
+ (.I0(SC_addResult_i_93_n_0),
+ .I1(SC_addResult_i_94_n_0),
+ .O(SC_addResult_i_45_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_46
+ (.I0(SC_addResult_i_95_n_0),
+ .I1(SC_addResult_i_96_n_0),
+ .O(SC_addResult_i_46_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_47
+ (.I0(SC_addResult_i_97_n_0),
+ .I1(SC_addResult_i_98_n_0),
+ .O(SC_addResult_i_47_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_48
+ (.I0(SC_addResult_i_99_n_0),
+ .I1(SC_addResult_i_100_n_0),
+ .O(SC_addResult_i_48_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_49
+ (.I0(SC_addResult_i_101_n_0),
+ .I1(SC_addResult_i_102_n_0),
+ .O(SC_addResult_i_49_n_0),
+ .S(SR_readAddress[2]));
+ LUT4 #(
+ .INIT(16'h6186))
+ SC_addResult_i_5
+ (.I0(SR_readAddress[1]),
+ .I1(SR_readAddress[3]),
+ .I2(SR_readAddress[2]),
+ .I3(SR_readAddress[0]),
+ .O(SC_multOperand2[7]));
+ MUXF7 SC_addResult_i_50
+ (.I0(SC_addResult_i_103_n_0),
+ .I1(SC_addResult_i_104_n_0),
+ .O(SC_addResult_i_50_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_51
+ (.I0(SC_addResult_i_105_n_0),
+ .I1(SC_addResult_i_106_n_0),
+ .O(SC_addResult_i_51_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_52
+ (.I0(SC_addResult_i_107_n_0),
+ .I1(SC_addResult_i_108_n_0),
+ .O(SC_addResult_i_52_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_53
+ (.I0(SC_addResult_i_109_n_0),
+ .I1(SC_addResult_i_110_n_0),
+ .O(SC_addResult_i_53_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_54
+ (.I0(SC_addResult_i_111_n_0),
+ .I1(SC_addResult_i_112_n_0),
+ .O(SC_addResult_i_54_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_55
+ (.I0(SC_addResult_i_113_n_0),
+ .I1(SC_addResult_i_114_n_0),
+ .O(SC_addResult_i_55_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_56
+ (.I0(SC_addResult_i_115_n_0),
+ .I1(SC_addResult_i_116_n_0),
+ .O(SC_addResult_i_56_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_57
+ (.I0(SC_addResult_i_117_n_0),
+ .I1(SC_addResult_i_118_n_0),
+ .O(SC_addResult_i_57_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_58
+ (.I0(SC_addResult_i_119_n_0),
+ .I1(SC_addResult_i_120_n_0),
+ .O(SC_addResult_i_58_n_0),
+ .S(SR_readAddress[2]));
+ MUXF7 SC_addResult_i_59
+ (.I0(SC_addResult_i_121_n_0),
+ .I1(SC_addResult_i_122_n_0),
+ .O(SC_addResult_i_59_n_0),
+ .S(SR_readAddress[2]));
+ LUT3 #(
+ .INIT(8'h42))
+ SC_addResult_i_6
+ (.I0(SR_readAddress[0]),
+ .I1(SR_readAddress[1]),
+ .I2(SR_readAddress[2]),
+ .O(SC_multOperand2[6]));
+ MUXF7 SC_addResult_i_60
+ (.I0(SC_addResult_i_123_n_0),
+ .I1(SC_addResult_i_124_n_0),
+ .O(SC_addResult_i_60_n_0),
+ .S(SR_readAddress[2]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_61
+ (.I0(\SR_shiftRegister_reg[3] [15]),
+ .I1(\SR_shiftRegister_reg[2] [15]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [15]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [15]),
+ .O(SC_addResult_i_61_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_62
+ (.I0(\SR_shiftRegister_reg[7] [15]),
+ .I1(\SR_shiftRegister_reg[6] [15]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [15]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [15]),
+ .O(SC_addResult_i_62_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_63
+ (.I0(\SR_shiftRegister_reg[11] [15]),
+ .I1(\SR_shiftRegister_reg[10] [15]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [15]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [15]),
+ .O(SC_addResult_i_63_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_64
+ (.I0(\SR_shiftRegister_reg[15] [15]),
+ .I1(\SR_shiftRegister_reg[14] [15]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [15]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [15]),
+ .O(SC_addResult_i_64_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_65
+ (.I0(\SR_shiftRegister_reg[3] [14]),
+ .I1(\SR_shiftRegister_reg[2] [14]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [14]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [14]),
+ .O(SC_addResult_i_65_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_66
+ (.I0(\SR_shiftRegister_reg[7] [14]),
+ .I1(\SR_shiftRegister_reg[6] [14]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [14]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [14]),
+ .O(SC_addResult_i_66_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_67
+ (.I0(\SR_shiftRegister_reg[11] [14]),
+ .I1(\SR_shiftRegister_reg[10] [14]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [14]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [14]),
+ .O(SC_addResult_i_67_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_68
+ (.I0(\SR_shiftRegister_reg[15] [14]),
+ .I1(\SR_shiftRegister_reg[14] [14]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [14]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [14]),
+ .O(SC_addResult_i_68_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_69
+ (.I0(\SR_shiftRegister_reg[3] [13]),
+ .I1(\SR_shiftRegister_reg[2] [13]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [13]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [13]),
+ .O(SC_addResult_i_69_n_0));
+ LUT4 #(
+ .INIT(16'hA245))
+ SC_addResult_i_7
+ (.I0(SR_readAddress[0]),
+ .I1(SR_readAddress[2]),
+ .I2(SR_readAddress[3]),
+ .I3(SR_readAddress[1]),
+ .O(SC_multOperand2[5]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_70
+ (.I0(\SR_shiftRegister_reg[7] [13]),
+ .I1(\SR_shiftRegister_reg[6] [13]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [13]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [13]),
+ .O(SC_addResult_i_70_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_71
+ (.I0(\SR_shiftRegister_reg[11] [13]),
+ .I1(\SR_shiftRegister_reg[10] [13]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [13]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [13]),
+ .O(SC_addResult_i_71_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_72
+ (.I0(\SR_shiftRegister_reg[15] [13]),
+ .I1(\SR_shiftRegister_reg[14] [13]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [13]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [13]),
+ .O(SC_addResult_i_72_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_73
+ (.I0(\SR_shiftRegister_reg[3] [12]),
+ .I1(\SR_shiftRegister_reg[2] [12]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [12]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [12]),
+ .O(SC_addResult_i_73_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_74
+ (.I0(\SR_shiftRegister_reg[7] [12]),
+ .I1(\SR_shiftRegister_reg[6] [12]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [12]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [12]),
+ .O(SC_addResult_i_74_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_75
+ (.I0(\SR_shiftRegister_reg[11] [12]),
+ .I1(\SR_shiftRegister_reg[10] [12]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [12]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [12]),
+ .O(SC_addResult_i_75_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_76
+ (.I0(\SR_shiftRegister_reg[15] [12]),
+ .I1(\SR_shiftRegister_reg[14] [12]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [12]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [12]),
+ .O(SC_addResult_i_76_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_77
+ (.I0(\SR_shiftRegister_reg[3] [11]),
+ .I1(\SR_shiftRegister_reg[2] [11]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [11]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [11]),
+ .O(SC_addResult_i_77_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_78
+ (.I0(\SR_shiftRegister_reg[7] [11]),
+ .I1(\SR_shiftRegister_reg[6] [11]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [11]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [11]),
+ .O(SC_addResult_i_78_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_79
+ (.I0(\SR_shiftRegister_reg[11] [11]),
+ .I1(\SR_shiftRegister_reg[10] [11]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [11]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [11]),
+ .O(SC_addResult_i_79_n_0));
+ LUT4 #(
+ .INIT(16'hF18F))
+ SC_addResult_i_8
+ (.I0(SR_readAddress[0]),
+ .I1(SR_readAddress[1]),
+ .I2(SR_readAddress[3]),
+ .I3(SR_readAddress[2]),
+ .O(SC_multOperand2[4]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_80
+ (.I0(\SR_shiftRegister_reg[15] [11]),
+ .I1(\SR_shiftRegister_reg[14] [11]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [11]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [11]),
+ .O(SC_addResult_i_80_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_81
+ (.I0(\SR_shiftRegister_reg[3] [10]),
+ .I1(\SR_shiftRegister_reg[2] [10]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [10]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [10]),
+ .O(SC_addResult_i_81_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_82
+ (.I0(\SR_shiftRegister_reg[7] [10]),
+ .I1(\SR_shiftRegister_reg[6] [10]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [10]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [10]),
+ .O(SC_addResult_i_82_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_83
+ (.I0(\SR_shiftRegister_reg[11] [10]),
+ .I1(\SR_shiftRegister_reg[10] [10]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [10]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [10]),
+ .O(SC_addResult_i_83_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_84
+ (.I0(\SR_shiftRegister_reg[15] [10]),
+ .I1(\SR_shiftRegister_reg[14] [10]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [10]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [10]),
+ .O(SC_addResult_i_84_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_85
+ (.I0(\SR_shiftRegister_reg[3] [9]),
+ .I1(\SR_shiftRegister_reg[2] [9]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [9]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [9]),
+ .O(SC_addResult_i_85_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_86
+ (.I0(\SR_shiftRegister_reg[7] [9]),
+ .I1(\SR_shiftRegister_reg[6] [9]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [9]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [9]),
+ .O(SC_addResult_i_86_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_87
+ (.I0(\SR_shiftRegister_reg[11] [9]),
+ .I1(\SR_shiftRegister_reg[10] [9]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [9]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [9]),
+ .O(SC_addResult_i_87_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_88
+ (.I0(\SR_shiftRegister_reg[15] [9]),
+ .I1(\SR_shiftRegister_reg[14] [9]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [9]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [9]),
+ .O(SC_addResult_i_88_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_89
+ (.I0(\SR_shiftRegister_reg[3] [8]),
+ .I1(\SR_shiftRegister_reg[2] [8]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [8]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [8]),
+ .O(SC_addResult_i_89_n_0));
+ LUT4 #(
+ .INIT(16'hD5AB))
+ SC_addResult_i_9
+ (.I0(SR_readAddress[0]),
+ .I1(SR_readAddress[2]),
+ .I2(SR_readAddress[3]),
+ .I3(SR_readAddress[1]),
+ .O(SC_multOperand2[3]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_90
+ (.I0(\SR_shiftRegister_reg[7] [8]),
+ .I1(\SR_shiftRegister_reg[6] [8]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [8]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [8]),
+ .O(SC_addResult_i_90_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_91
+ (.I0(\SR_shiftRegister_reg[11] [8]),
+ .I1(\SR_shiftRegister_reg[10] [8]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [8]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [8]),
+ .O(SC_addResult_i_91_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_92
+ (.I0(\SR_shiftRegister_reg[15] [8]),
+ .I1(\SR_shiftRegister_reg[14] [8]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [8]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [8]),
+ .O(SC_addResult_i_92_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_93
+ (.I0(\SR_shiftRegister_reg[3] [7]),
+ .I1(\SR_shiftRegister_reg[2] [7]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [7]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [7]),
+ .O(SC_addResult_i_93_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_94
+ (.I0(\SR_shiftRegister_reg[7] [7]),
+ .I1(\SR_shiftRegister_reg[6] [7]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [7]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [7]),
+ .O(SC_addResult_i_94_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_95
+ (.I0(\SR_shiftRegister_reg[11] [7]),
+ .I1(\SR_shiftRegister_reg[10] [7]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [7]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [7]),
+ .O(SC_addResult_i_95_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_96
+ (.I0(\SR_shiftRegister_reg[15] [7]),
+ .I1(\SR_shiftRegister_reg[14] [7]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[13] [7]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[12] [7]),
+ .O(SC_addResult_i_96_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_97
+ (.I0(\SR_shiftRegister_reg[3] [6]),
+ .I1(\SR_shiftRegister_reg[2] [6]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[1] [6]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[0] [6]),
+ .O(SC_addResult_i_97_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_98
+ (.I0(\SR_shiftRegister_reg[7] [6]),
+ .I1(\SR_shiftRegister_reg[6] [6]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[5] [6]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[4] [6]),
+ .O(SC_addResult_i_98_n_0));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ SC_addResult_i_99
+ (.I0(\SR_shiftRegister_reg[11] [6]),
+ .I1(\SR_shiftRegister_reg[10] [6]),
+ .I2(SR_readAddress[1]),
+ .I3(\SR_shiftRegister_reg[9] [6]),
+ .I4(SR_readAddress[0]),
+ .I5(\SR_shiftRegister_reg[8] [6]),
+ .O(SC_addResult_i_99_n_0));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_filteredSample[3]_i_2
+ (.I0(SC_addResult_n_91),
+ .I1(L[15]),
+ .O(\SR_filteredSample[3]_i_2_n_0 ));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[0]),
+ .Q(O_filteredSample_OBUF[0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[10]),
+ .Q(O_filteredSample_OBUF[10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[11]),
+ .Q(O_filteredSample_OBUF[11]));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 \SR_filteredSample_reg[11]_i_1
+ (.CI(\SR_filteredSample_reg[7]_i_1_n_0 ),
+ .CO({\SR_filteredSample_reg[11]_i_1_n_0 ,\SR_filteredSample_reg[11]_i_1_n_1 ,\SR_filteredSample_reg[11]_i_1_n_2 ,\SR_filteredSample_reg[11]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .O(p_0_in[11:8]),
+ .S(L[26:23]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[12]),
+ .Q(O_filteredSample_OBUF[12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[13]),
+ .Q(O_filteredSample_OBUF[13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[14]),
+ .Q(O_filteredSample_OBUF[14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[15]),
+ .Q(O_filteredSample_OBUF[15]));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 \SR_filteredSample_reg[15]_i_1
+ (.CI(\SR_filteredSample_reg[11]_i_1_n_0 ),
+ .CO({\SR_filteredSample_reg[15]_i_1_n_1 ,\SR_filteredSample_reg[15]_i_1_n_2 ,\SR_filteredSample_reg[15]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .O(p_0_in[15:12]),
+ .S(L[30:27]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[1]),
+ .Q(O_filteredSample_OBUF[1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[2]),
+ .Q(O_filteredSample_OBUF[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[3]),
+ .Q(O_filteredSample_OBUF[3]));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 \SR_filteredSample_reg[3]_i_1
+ (.CI(\<const0> ),
+ .CO({\SR_filteredSample_reg[3]_i_1_n_0 ,\SR_filteredSample_reg[3]_i_1_n_1 ,\SR_filteredSample_reg[3]_i_1_n_2 ,\SR_filteredSample_reg[3]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\<const0> ,SC_addResult_n_91}),
+ .O(p_0_in[3:0]),
+ .S({L[18:16],\SR_filteredSample[3]_i_2_n_0 }));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[4]),
+ .Q(O_filteredSample_OBUF[4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[5]),
+ .Q(O_filteredSample_OBUF[5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[6]),
+ .Q(O_filteredSample_OBUF[6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[7]),
+ .Q(O_filteredSample_OBUF[7]));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 \SR_filteredSample_reg[7]_i_1
+ (.CI(\SR_filteredSample_reg[3]_i_1_n_0 ),
+ .CO({\SR_filteredSample_reg[7]_i_1_n_0 ,\SR_filteredSample_reg[7]_i_1_n_1 ,\SR_filteredSample_reg[7]_i_1_n_2 ,\SR_filteredSample_reg[7]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
+ .O(p_0_in[7:4]),
+ .S(L[22:19]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[8]),
+ .Q(O_filteredSample_OBUF[8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_filteredSample_reg[9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadOutput_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[9]),
+ .Q(O_filteredSample_OBUF[9]));
+ LUT2 #(
+ .INIT(4'h1))
+ \SR_readAddress[0]_i_1
+ (.I0(SR_readAddress[0]),
+ .I1(I_initAddress_IBUF),
+ .O(\SR_readAddress[0]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'h06))
+ \SR_readAddress[1]_i_1
+ (.I0(SR_readAddress[1]),
+ .I1(SR_readAddress[0]),
+ .I2(I_initAddress_IBUF),
+ .O(\SR_readAddress[1]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h006A))
+ \SR_readAddress[2]_i_1
+ (.I0(SR_readAddress[2]),
+ .I1(SR_readAddress[1]),
+ .I2(SR_readAddress[0]),
+ .I3(I_initAddress_IBUF),
+ .O(\SR_readAddress[2]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \SR_readAddress[3]_i_1
+ (.I0(I_incrAddress_IBUF),
+ .I1(I_initAddress_IBUF),
+ .O(\SR_readAddress[3]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h00006AAA))
+ \SR_readAddress[3]_i_2
+ (.I0(SR_readAddress[3]),
+ .I1(SR_readAddress[2]),
+ .I2(SR_readAddress[0]),
+ .I3(SR_readAddress[1]),
+ .I4(I_initAddress_IBUF),
+ .O(\SR_readAddress[3]_i_2_n_0 ));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[0]_i_1_n_0 ),
+ .Q(SR_readAddress[0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[1]_i_1_n_0 ),
+ .Q(SR_readAddress[1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[2]_i_1_n_0 ),
+ .Q(SR_readAddress[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[3]_i_2_n_0 ),
+ .Q(SR_readAddress[3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[0]),
+ .Q(\SR_shiftRegister_reg[0] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[10]),
+ .Q(\SR_shiftRegister_reg[0] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[11]),
+ .Q(\SR_shiftRegister_reg[0] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[12]),
+ .Q(\SR_shiftRegister_reg[0] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[13]),
+ .Q(\SR_shiftRegister_reg[0] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[14]),
+ .Q(\SR_shiftRegister_reg[0] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[15]),
+ .Q(\SR_shiftRegister_reg[0] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[1]),
+ .Q(\SR_shiftRegister_reg[0] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[2]),
+ .Q(\SR_shiftRegister_reg[0] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[3]),
+ .Q(\SR_shiftRegister_reg[0] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[4]),
+ .Q(\SR_shiftRegister_reg[0] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[5]),
+ .Q(\SR_shiftRegister_reg[0] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[6]),
+ .Q(\SR_shiftRegister_reg[0] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[7]),
+ .Q(\SR_shiftRegister_reg[0] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[8]),
+ .Q(\SR_shiftRegister_reg[0] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[9]),
+ .Q(\SR_shiftRegister_reg[0] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [0]),
+ .Q(\SR_shiftRegister_reg[10] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [10]),
+ .Q(\SR_shiftRegister_reg[10] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [11]),
+ .Q(\SR_shiftRegister_reg[10] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [12]),
+ .Q(\SR_shiftRegister_reg[10] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [13]),
+ .Q(\SR_shiftRegister_reg[10] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [14]),
+ .Q(\SR_shiftRegister_reg[10] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [15]),
+ .Q(\SR_shiftRegister_reg[10] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [1]),
+ .Q(\SR_shiftRegister_reg[10] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [2]),
+ .Q(\SR_shiftRegister_reg[10] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [3]),
+ .Q(\SR_shiftRegister_reg[10] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [4]),
+ .Q(\SR_shiftRegister_reg[10] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [5]),
+ .Q(\SR_shiftRegister_reg[10] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [6]),
+ .Q(\SR_shiftRegister_reg[10] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [7]),
+ .Q(\SR_shiftRegister_reg[10] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [8]),
+ .Q(\SR_shiftRegister_reg[10] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9] [9]),
+ .Q(\SR_shiftRegister_reg[10] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [0]),
+ .Q(\SR_shiftRegister_reg[11] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [10]),
+ .Q(\SR_shiftRegister_reg[11] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [11]),
+ .Q(\SR_shiftRegister_reg[11] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [12]),
+ .Q(\SR_shiftRegister_reg[11] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [13]),
+ .Q(\SR_shiftRegister_reg[11] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [14]),
+ .Q(\SR_shiftRegister_reg[11] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [15]),
+ .Q(\SR_shiftRegister_reg[11] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [1]),
+ .Q(\SR_shiftRegister_reg[11] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [2]),
+ .Q(\SR_shiftRegister_reg[11] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [3]),
+ .Q(\SR_shiftRegister_reg[11] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [4]),
+ .Q(\SR_shiftRegister_reg[11] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [5]),
+ .Q(\SR_shiftRegister_reg[11] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [6]),
+ .Q(\SR_shiftRegister_reg[11] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [7]),
+ .Q(\SR_shiftRegister_reg[11] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [8]),
+ .Q(\SR_shiftRegister_reg[11] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10] [9]),
+ .Q(\SR_shiftRegister_reg[11] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [0]),
+ .Q(\SR_shiftRegister_reg[12] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [10]),
+ .Q(\SR_shiftRegister_reg[12] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [11]),
+ .Q(\SR_shiftRegister_reg[12] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [12]),
+ .Q(\SR_shiftRegister_reg[12] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [13]),
+ .Q(\SR_shiftRegister_reg[12] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [14]),
+ .Q(\SR_shiftRegister_reg[12] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [15]),
+ .Q(\SR_shiftRegister_reg[12] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [1]),
+ .Q(\SR_shiftRegister_reg[12] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [2]),
+ .Q(\SR_shiftRegister_reg[12] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [3]),
+ .Q(\SR_shiftRegister_reg[12] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [4]),
+ .Q(\SR_shiftRegister_reg[12] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [5]),
+ .Q(\SR_shiftRegister_reg[12] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [6]),
+ .Q(\SR_shiftRegister_reg[12] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [7]),
+ .Q(\SR_shiftRegister_reg[12] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [8]),
+ .Q(\SR_shiftRegister_reg[12] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11] [9]),
+ .Q(\SR_shiftRegister_reg[12] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [0]),
+ .Q(\SR_shiftRegister_reg[13] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [10]),
+ .Q(\SR_shiftRegister_reg[13] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [11]),
+ .Q(\SR_shiftRegister_reg[13] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [12]),
+ .Q(\SR_shiftRegister_reg[13] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [13]),
+ .Q(\SR_shiftRegister_reg[13] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [14]),
+ .Q(\SR_shiftRegister_reg[13] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [15]),
+ .Q(\SR_shiftRegister_reg[13] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [1]),
+ .Q(\SR_shiftRegister_reg[13] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [2]),
+ .Q(\SR_shiftRegister_reg[13] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [3]),
+ .Q(\SR_shiftRegister_reg[13] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [4]),
+ .Q(\SR_shiftRegister_reg[13] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [5]),
+ .Q(\SR_shiftRegister_reg[13] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [6]),
+ .Q(\SR_shiftRegister_reg[13] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [7]),
+ .Q(\SR_shiftRegister_reg[13] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [8]),
+ .Q(\SR_shiftRegister_reg[13] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12] [9]),
+ .Q(\SR_shiftRegister_reg[13] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [0]),
+ .Q(\SR_shiftRegister_reg[14] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [10]),
+ .Q(\SR_shiftRegister_reg[14] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [11]),
+ .Q(\SR_shiftRegister_reg[14] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [12]),
+ .Q(\SR_shiftRegister_reg[14] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [13]),
+ .Q(\SR_shiftRegister_reg[14] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [14]),
+ .Q(\SR_shiftRegister_reg[14] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [15]),
+ .Q(\SR_shiftRegister_reg[14] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [1]),
+ .Q(\SR_shiftRegister_reg[14] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [2]),
+ .Q(\SR_shiftRegister_reg[14] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [3]),
+ .Q(\SR_shiftRegister_reg[14] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [4]),
+ .Q(\SR_shiftRegister_reg[14] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [5]),
+ .Q(\SR_shiftRegister_reg[14] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [6]),
+ .Q(\SR_shiftRegister_reg[14] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [7]),
+ .Q(\SR_shiftRegister_reg[14] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [8]),
+ .Q(\SR_shiftRegister_reg[14] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13] [9]),
+ .Q(\SR_shiftRegister_reg[14] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [0]),
+ .Q(\SR_shiftRegister_reg[15] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [10]),
+ .Q(\SR_shiftRegister_reg[15] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [11]),
+ .Q(\SR_shiftRegister_reg[15] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [12]),
+ .Q(\SR_shiftRegister_reg[15] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [13]),
+ .Q(\SR_shiftRegister_reg[15] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [14]),
+ .Q(\SR_shiftRegister_reg[15] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [15]),
+ .Q(\SR_shiftRegister_reg[15] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [1]),
+ .Q(\SR_shiftRegister_reg[15] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [2]),
+ .Q(\SR_shiftRegister_reg[15] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [3]),
+ .Q(\SR_shiftRegister_reg[15] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [4]),
+ .Q(\SR_shiftRegister_reg[15] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [5]),
+ .Q(\SR_shiftRegister_reg[15] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [6]),
+ .Q(\SR_shiftRegister_reg[15] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [7]),
+ .Q(\SR_shiftRegister_reg[15] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [8]),
+ .Q(\SR_shiftRegister_reg[15] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14] [9]),
+ .Q(\SR_shiftRegister_reg[15] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [0]),
+ .Q(\SR_shiftRegister_reg[1] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [10]),
+ .Q(\SR_shiftRegister_reg[1] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [11]),
+ .Q(\SR_shiftRegister_reg[1] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [12]),
+ .Q(\SR_shiftRegister_reg[1] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [13]),
+ .Q(\SR_shiftRegister_reg[1] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [14]),
+ .Q(\SR_shiftRegister_reg[1] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [15]),
+ .Q(\SR_shiftRegister_reg[1] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [1]),
+ .Q(\SR_shiftRegister_reg[1] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [2]),
+ .Q(\SR_shiftRegister_reg[1] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [3]),
+ .Q(\SR_shiftRegister_reg[1] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [4]),
+ .Q(\SR_shiftRegister_reg[1] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [5]),
+ .Q(\SR_shiftRegister_reg[1] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [6]),
+ .Q(\SR_shiftRegister_reg[1] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [7]),
+ .Q(\SR_shiftRegister_reg[1] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [8]),
+ .Q(\SR_shiftRegister_reg[1] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0] [9]),
+ .Q(\SR_shiftRegister_reg[1] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [0]),
+ .Q(\SR_shiftRegister_reg[2] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [10]),
+ .Q(\SR_shiftRegister_reg[2] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [11]),
+ .Q(\SR_shiftRegister_reg[2] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [12]),
+ .Q(\SR_shiftRegister_reg[2] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [13]),
+ .Q(\SR_shiftRegister_reg[2] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [14]),
+ .Q(\SR_shiftRegister_reg[2] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [15]),
+ .Q(\SR_shiftRegister_reg[2] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [1]),
+ .Q(\SR_shiftRegister_reg[2] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [2]),
+ .Q(\SR_shiftRegister_reg[2] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [3]),
+ .Q(\SR_shiftRegister_reg[2] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [4]),
+ .Q(\SR_shiftRegister_reg[2] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [5]),
+ .Q(\SR_shiftRegister_reg[2] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [6]),
+ .Q(\SR_shiftRegister_reg[2] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [7]),
+ .Q(\SR_shiftRegister_reg[2] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [8]),
+ .Q(\SR_shiftRegister_reg[2] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1] [9]),
+ .Q(\SR_shiftRegister_reg[2] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [0]),
+ .Q(\SR_shiftRegister_reg[3] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [10]),
+ .Q(\SR_shiftRegister_reg[3] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [11]),
+ .Q(\SR_shiftRegister_reg[3] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [12]),
+ .Q(\SR_shiftRegister_reg[3] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [13]),
+ .Q(\SR_shiftRegister_reg[3] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [14]),
+ .Q(\SR_shiftRegister_reg[3] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [15]),
+ .Q(\SR_shiftRegister_reg[3] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [1]),
+ .Q(\SR_shiftRegister_reg[3] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [2]),
+ .Q(\SR_shiftRegister_reg[3] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [3]),
+ .Q(\SR_shiftRegister_reg[3] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [4]),
+ .Q(\SR_shiftRegister_reg[3] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [5]),
+ .Q(\SR_shiftRegister_reg[3] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [6]),
+ .Q(\SR_shiftRegister_reg[3] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [7]),
+ .Q(\SR_shiftRegister_reg[3] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [8]),
+ .Q(\SR_shiftRegister_reg[3] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2] [9]),
+ .Q(\SR_shiftRegister_reg[3] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [0]),
+ .Q(\SR_shiftRegister_reg[4] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [10]),
+ .Q(\SR_shiftRegister_reg[4] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [11]),
+ .Q(\SR_shiftRegister_reg[4] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [12]),
+ .Q(\SR_shiftRegister_reg[4] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [13]),
+ .Q(\SR_shiftRegister_reg[4] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [14]),
+ .Q(\SR_shiftRegister_reg[4] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [15]),
+ .Q(\SR_shiftRegister_reg[4] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [1]),
+ .Q(\SR_shiftRegister_reg[4] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [2]),
+ .Q(\SR_shiftRegister_reg[4] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [3]),
+ .Q(\SR_shiftRegister_reg[4] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [4]),
+ .Q(\SR_shiftRegister_reg[4] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [5]),
+ .Q(\SR_shiftRegister_reg[4] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [6]),
+ .Q(\SR_shiftRegister_reg[4] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [7]),
+ .Q(\SR_shiftRegister_reg[4] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [8]),
+ .Q(\SR_shiftRegister_reg[4] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3] [9]),
+ .Q(\SR_shiftRegister_reg[4] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [0]),
+ .Q(\SR_shiftRegister_reg[5] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [10]),
+ .Q(\SR_shiftRegister_reg[5] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [11]),
+ .Q(\SR_shiftRegister_reg[5] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [12]),
+ .Q(\SR_shiftRegister_reg[5] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [13]),
+ .Q(\SR_shiftRegister_reg[5] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [14]),
+ .Q(\SR_shiftRegister_reg[5] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [15]),
+ .Q(\SR_shiftRegister_reg[5] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [1]),
+ .Q(\SR_shiftRegister_reg[5] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [2]),
+ .Q(\SR_shiftRegister_reg[5] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [3]),
+ .Q(\SR_shiftRegister_reg[5] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [4]),
+ .Q(\SR_shiftRegister_reg[5] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [5]),
+ .Q(\SR_shiftRegister_reg[5] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [6]),
+ .Q(\SR_shiftRegister_reg[5] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [7]),
+ .Q(\SR_shiftRegister_reg[5] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [8]),
+ .Q(\SR_shiftRegister_reg[5] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4] [9]),
+ .Q(\SR_shiftRegister_reg[5] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [0]),
+ .Q(\SR_shiftRegister_reg[6] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [10]),
+ .Q(\SR_shiftRegister_reg[6] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [11]),
+ .Q(\SR_shiftRegister_reg[6] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [12]),
+ .Q(\SR_shiftRegister_reg[6] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [13]),
+ .Q(\SR_shiftRegister_reg[6] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [14]),
+ .Q(\SR_shiftRegister_reg[6] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [15]),
+ .Q(\SR_shiftRegister_reg[6] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [1]),
+ .Q(\SR_shiftRegister_reg[6] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [2]),
+ .Q(\SR_shiftRegister_reg[6] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [3]),
+ .Q(\SR_shiftRegister_reg[6] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [4]),
+ .Q(\SR_shiftRegister_reg[6] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [5]),
+ .Q(\SR_shiftRegister_reg[6] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [6]),
+ .Q(\SR_shiftRegister_reg[6] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [7]),
+ .Q(\SR_shiftRegister_reg[6] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [8]),
+ .Q(\SR_shiftRegister_reg[6] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5] [9]),
+ .Q(\SR_shiftRegister_reg[6] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [0]),
+ .Q(\SR_shiftRegister_reg[7] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [10]),
+ .Q(\SR_shiftRegister_reg[7] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [11]),
+ .Q(\SR_shiftRegister_reg[7] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [12]),
+ .Q(\SR_shiftRegister_reg[7] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [13]),
+ .Q(\SR_shiftRegister_reg[7] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [14]),
+ .Q(\SR_shiftRegister_reg[7] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [15]),
+ .Q(\SR_shiftRegister_reg[7] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [1]),
+ .Q(\SR_shiftRegister_reg[7] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [2]),
+ .Q(\SR_shiftRegister_reg[7] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [3]),
+ .Q(\SR_shiftRegister_reg[7] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [4]),
+ .Q(\SR_shiftRegister_reg[7] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [5]),
+ .Q(\SR_shiftRegister_reg[7] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [6]),
+ .Q(\SR_shiftRegister_reg[7] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [7]),
+ .Q(\SR_shiftRegister_reg[7] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [8]),
+ .Q(\SR_shiftRegister_reg[7] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6] [9]),
+ .Q(\SR_shiftRegister_reg[7] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [0]),
+ .Q(\SR_shiftRegister_reg[8] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [10]),
+ .Q(\SR_shiftRegister_reg[8] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [11]),
+ .Q(\SR_shiftRegister_reg[8] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [12]),
+ .Q(\SR_shiftRegister_reg[8] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [13]),
+ .Q(\SR_shiftRegister_reg[8] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [14]),
+ .Q(\SR_shiftRegister_reg[8] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [15]),
+ .Q(\SR_shiftRegister_reg[8] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [1]),
+ .Q(\SR_shiftRegister_reg[8] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [2]),
+ .Q(\SR_shiftRegister_reg[8] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [3]),
+ .Q(\SR_shiftRegister_reg[8] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [4]),
+ .Q(\SR_shiftRegister_reg[8] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [5]),
+ .Q(\SR_shiftRegister_reg[8] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [6]),
+ .Q(\SR_shiftRegister_reg[8] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [7]),
+ .Q(\SR_shiftRegister_reg[8] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [8]),
+ .Q(\SR_shiftRegister_reg[8] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7] [9]),
+ .Q(\SR_shiftRegister_reg[8] [9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [0]),
+ .Q(\SR_shiftRegister_reg[9] [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [10]),
+ .Q(\SR_shiftRegister_reg[9] [10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [11]),
+ .Q(\SR_shiftRegister_reg[9] [11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [12]),
+ .Q(\SR_shiftRegister_reg[9] [12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [13]),
+ .Q(\SR_shiftRegister_reg[9] [13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [14]),
+ .Q(\SR_shiftRegister_reg[9] [14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [15]),
+ .Q(\SR_shiftRegister_reg[9] [15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [1]),
+ .Q(\SR_shiftRegister_reg[9] [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [2]),
+ .Q(\SR_shiftRegister_reg[9] [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [3]),
+ .Q(\SR_shiftRegister_reg[9] [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [4]),
+ .Q(\SR_shiftRegister_reg[9] [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [5]),
+ .Q(\SR_shiftRegister_reg[9] [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [6]),
+ .Q(\SR_shiftRegister_reg[9] [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [7]),
+ .Q(\SR_shiftRegister_reg[9] [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [8]),
+ .Q(\SR_shiftRegister_reg[9] [8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8] [9]),
+ .Q(\SR_shiftRegister_reg[9] [9]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[0]_i_1
+ (.I0(SC_addResult_n_105),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[0]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[10]_i_1
+ (.I0(SC_addResult_n_95),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[10]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[11]_i_1
+ (.I0(SC_addResult_n_94),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[11]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[12]_i_1
+ (.I0(SC_addResult_n_93),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[12]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[13]_i_1
+ (.I0(SC_addResult_n_92),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[13]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[14]_i_1
+ (.I0(SC_addResult_n_91),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[14]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[15]_i_1
+ (.I0(L[15]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[15]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[16]_i_1
+ (.I0(L[16]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[16]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[17]_i_1
+ (.I0(L[17]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[17]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[18]_i_1
+ (.I0(L[18]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[18]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[19]_i_1
+ (.I0(L[19]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[19]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[1]_i_1
+ (.I0(SC_addResult_n_104),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[1]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[20]_i_1
+ (.I0(L[20]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[20]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[21]_i_1
+ (.I0(L[21]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[21]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[22]_i_1
+ (.I0(L[22]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[22]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[23]_i_1
+ (.I0(L[23]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[23]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[24]_i_1
+ (.I0(L[24]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[24]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[25]_i_1
+ (.I0(L[25]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[25]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[26]_i_1
+ (.I0(L[26]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[26]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[27]_i_1
+ (.I0(L[27]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[27]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[28]_i_1
+ (.I0(L[28]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[28]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[29]_i_1
+ (.I0(L[29]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[29]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[2]_i_1
+ (.I0(SC_addResult_n_103),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[2]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[30]_i_1
+ (.I0(L[30]),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[30]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[31]_i_1
+ (.I0(SC_addResult_n_74),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[31]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[32]_i_1
+ (.I0(SC_addResult_n_73),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[32]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[33]_i_1
+ (.I0(SC_addResult_n_72),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[33]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[34]_i_1
+ (.I0(SC_addResult_n_71),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[34]));
+ LUT2 #(
+ .INIT(4'hE))
+ \SR_sum[35]_i_1
+ (.I0(I_loadSum_IBUF),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[35]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[35]_i_2
+ (.I0(SC_addResult_n_70),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[35]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[3]_i_1
+ (.I0(SC_addResult_n_102),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[3]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[4]_i_1
+ (.I0(SC_addResult_n_101),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[4]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[5]_i_1
+ (.I0(SC_addResult_n_100),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[5]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[6]_i_1
+ (.I0(SC_addResult_n_99),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[6]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[7]_i_1
+ (.I0(SC_addResult_n_98),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[7]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[8]_i_1
+ (.I0(SC_addResult_n_97),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[8]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[9]_i_1
+ (.I0(SC_addResult_n_96),
+ .I1(I_initSum_IBUF),
+ .O(p_1_in[9]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[0]),
+ .Q(SR_sum[0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[10]),
+ .Q(SR_sum[10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[11]),
+ .Q(SR_sum[11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[12]),
+ .Q(SR_sum[12]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[13]),
+ .Q(SR_sum[13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[14]),
+ .Q(SR_sum[14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[15]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[15]),
+ .Q(SR_sum[15]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[16]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[16]),
+ .Q(SR_sum[16]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[17]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[17]),
+ .Q(SR_sum[17]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[18]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[18]),
+ .Q(SR_sum[18]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[19]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[19]),
+ .Q(SR_sum[19]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[1]),
+ .Q(SR_sum[1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[20]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[20]),
+ .Q(SR_sum[20]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[21]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[21]),
+ .Q(SR_sum[21]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[22]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[22]),
+ .Q(SR_sum[22]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[23]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[23]),
+ .Q(SR_sum[23]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[24]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[24]),
+ .Q(SR_sum[24]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[25]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[25]),
+ .Q(SR_sum[25]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[26]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[26]),
+ .Q(SR_sum[26]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[27]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[27]),
+ .Q(SR_sum[27]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[28]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[28]),
+ .Q(SR_sum[28]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[29]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[29]),
+ .Q(SR_sum[29]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[2]),
+ .Q(SR_sum[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[30]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[30]),
+ .Q(SR_sum[30]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[31]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[31]),
+ .Q(SR_sum[31]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[32]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[32]),
+ .Q(SR_sum[32]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[33]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[33]),
+ .Q(SR_sum[33]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[34]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[34]),
+ .Q(SR_sum[34]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[35]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[35]),
+ .Q(SR_sum[35]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[3]),
+ .Q(SR_sum[3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[4]),
+ .Q(SR_sum[4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[5]),
+ .Q(SR_sum[5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[6]),
+ .Q(SR_sum[6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[7]),
+ .Q(SR_sum[7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[8]),
+ .Q(SR_sum[8]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[35]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(p_1_in[9]),
+ .Q(SR_sum[9]));
+ VCC VCC
+ (.P(\<const1> ));
+endmodule
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 7d08c1bb8592058ee92cb298cc40e7d82cc104cf..fe12a2e40d899e53218df9bccbf9aab36f8170bd 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -17,7 +17,12 @@
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
--- Date Version Author Description
+-- Date Version A
+-- 2025-04-09 1.2 marzel Renamed some signals and port names to match
+-- the description of lab activity
+-- Modified the sample width to 16 bits
+-- Changed the filter coefficients to have abetter
+-- low-pass filter
-- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve
-- the user experience ;)
-- 2018-04-11 1.0 jnbazin Created
@@ -34,7 +39,7 @@ entity operativeUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(15 downto 0); -- 16 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_initAddress : in std_logic; -- Control signal to initialize register read address
I_incrAddress : in std_logic; -- Control signal to increment register read address
@@ -42,52 +47,73 @@ entity operativeUnit is
I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done
- O_Y : out std_logic_vector(7 downto 0) -- filtered sample
+ O_filteredSample : out std_logic_vector(15 downto 0) -- filtered sample
);
end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
- type registerFile is array(0 to 15) of signed(7 downto 0);
+ type registerFile is array(0 to 15) of signed(15 downto 0);
signal SR_coefRegister : registerFile;
signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples
- signal SC_multOperand1 : signed(7 downto 0);
- signal SC_multOperand2 : signed(7 downto 0);
- signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi
- signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition
- signal SR_sum : signed(19 downto 0); -- Accumulation register
- signal SR_Y : signed(7 downto 0); -- filtered sample storage register
+ signal SC_multOperand1 : signed(15 downto 0);
+ signal SC_multOperand2 : signed(15 downto 0);
+ signal SC_MultResult : signed(31 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(35 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(35 downto 0); -- Accumulation register
+ signal SR_filteredSample: signed(15 downto 0); -- filtered sample storage register
signal SR_readAddress : integer range 0 to 15; -- register files read address
begin
- -- Low-pass filter provided with octave (or Matlab ;)) command
- -- fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
- -- Or python with (import signal from scipy and math)
- -- [round(elem/math.sqrt(sum(signal.firwin(16, .001)**2)) * 2**6) for elem in signal.firwin(16, .001)]
-
- SR_coefRegister <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
- to_signed(3, 8),
- to_signed(6, 8),
- to_signed(10, 8),
- to_signed(15, 8),
- to_signed(20, 8),
- to_signed(24, 8),
- to_signed(26, 8),
- to_signed(26, 8),
- to_signed(24, 8),
- to_signed(20, 8),
- to_signed(15, 8),
- to_signed(10, 8),
- to_signed(6, 8),
- to_signed(3, 8),
- to_signed(2, 8)
+ -- Low-pass filter provided with octave (or Matlab ;)) script :
+ -- pkg load signal
+ --
+ -- fs=44100
+ -- fn=fs/2
+ -- n=16
+ -- fc=300
+ -- fLP=fir1(n-1,fc/fn,"low");
+ --
+ -- function quantized_signal = quantize(signal, q)
+ -- % Quantize the signal to q bits
+ -- max_val = 2^(q-1) - 1;
+ -- min_val = -2^(q-1);
+ -- quantized_signal = round(min(max(signal * 2^(q-1), min_val), max_val)) / 2^(q-1);
+ -- end
+ --
+ -- q=16
+ --
+ -- fLPq= quantize(fLP,q);
+ --
+ -- for i=1:n
+ -- printf("to_signed(%d,%d),\n", fLPq(i)*2^(q-1),q);
+ -- endfor
+
+ -- Table to store the filter coefficients obtained with the previous script
+ SR_coefRegister <= (to_signed(317,16),
+ to_signed(476,16),
+ to_signed(925,16),
+ to_signed(1589,16),
+ to_signed(2354,16),
+ to_signed(3087,16),
+ to_signed(3661,16),
+ to_signed(3975,16),
+ to_signed(3975,16),
+ to_signed(3661,16),
+ to_signed(3087,16),
+ to_signed(2354,16),
+ to_signed(1589,16),
+ to_signed(925,16),
+ to_signed(476,16),
+ to_signed(317,16)
);
-
+
+ -- Process to describe the shift register storing the input samples
shift : process (_BLANK_) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
@@ -97,6 +123,8 @@ begin
end if;
end process shift;
+ -- Process to describe the counter providing the selection adresses
+ -- of the multiplexers
incr_address : process (_BLANK_) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
@@ -106,13 +134,23 @@ begin
end if;
end process incr_address;
+ -- Signal detecting that the next cycle will be the one
+ -- providing the last product used to compute the convolution
O_processingDone <= '1' when _BLANK_;
- SC_multOperand1 <= _BLANK_; -- 8 bits
- SC_multOperand2 <= _BLANK_; -- 8 bits
- SC_MultResult <= _BLANK_; -- 16 bits
+ -- Signals connected with multiplexers (SIMPLY inferred with table indices)
+ SC_multOperand1 <= _BLANK_; -- 16 bits
+ SC_multOperand2 <= _BLANK_; -- 16 bits
+
+ -- Multiplication of the operands
+ SC_MultResult <= _BLANK_; -- 32 bits
+
+ -- Sum of the multiplication result and the accumulated value
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+ -- Register to store the accumulated value if the loadSum is active
+ -- It also reduces the width of the sum to fit to the input and output
+ -- signal widths (be careful with truncating/rounding)
sum_acc : process (_BLANK_) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
@@ -121,12 +159,13 @@ begin
end if;
end process sum_acc;
+ -- Register to store the final result if the loadOuput is active
store_result : process (_BLANK_) is
begin
_BLANK_
end process store_result;
- O_Y <= std_logic_vector(SR_Y);
+ O_filteredSample <= std_logic_vector(SR_filteredSample);
end architecture arch_operativeUnit;
diff --git a/src/hdl/processingUnitIP.v b/src/hdl/processingUnitIP.v
deleted file mode 100644
index 8ca1850662db62f5cc46beeed26fa9fef75e7d4c..0000000000000000000000000000000000000000
--- a/src/hdl/processingUnitIP.v
+++ /dev/null
@@ -1,3270 +0,0 @@
-// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
-// Date : Mon Feb 25 17:59:18 2019
-// Host : marzel-XPS-13-9350 running 64-bit Ubuntu 18.04.2 LTS
-// Command : write_verilog
-// /home/marzel/Documents/enseignements/IMTA_ELEC_A1S2_TAF/UV_ELEC_A1S2/TP_loto_ProcSon/ProcSon/NexysVideo/src/hdl/processingUnitIP.v
-// Design : operativeUnit
-// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
-// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
-// design files.
-// Device : xc7a200tsbg484-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* STRUCTURAL_NETLIST = "yes" *)
-module operativeUnit
- (I_clock,
- I_reset,
- I_inputSample,
- I_loadShift,
- I_initAddress,
- I_incrAddress,
- I_initSum,
- I_loadSum,
- I_loadY,
- O_processingDone,
- O_Y);
- input I_clock;
- input I_reset;
- input [7:0]I_inputSample;
- input I_loadShift;
- input I_initAddress;
- input I_incrAddress;
- input I_initSum;
- input I_loadSum;
- input I_loadY;
- output O_processingDone;
- output [7:0]O_Y;
-
- wire \<const0> ;
- wire \<const1> ;
- wire I_clock;
- wire I_clock_IBUF;
- wire I_clock_IBUF_BUFG;
- wire I_incrAddress;
- wire I_incrAddress_IBUF;
- wire I_initAddress;
- wire I_initAddress_IBUF;
- wire I_initSum;
- wire I_initSum_IBUF;
- wire [7:0]I_inputSample;
- wire [7:0]I_inputSample_IBUF;
- wire I_loadShift;
- wire I_loadShift_IBUF;
- wire I_loadSum;
- wire I_loadSum_IBUF;
- wire I_loadY;
- wire I_loadY_IBUF;
- wire I_reset;
- wire I_reset_IBUF;
- wire [14:7]L;
- wire [7:0]O_Y;
- wire [7:0]O_Y_OBUF;
- wire O_processingDone;
- wire O_processingDone_OBUF;
- wire [14:0]SC_MultResult;
- wire [4:0]SC_multOperand2;
- wire \SR_Y[4]_i_11_n_0 ;
- wire \SR_Y[4]_i_12_n_0 ;
- wire \SR_Y[4]_i_13_n_0 ;
- wire \SR_Y[4]_i_14_n_0 ;
- wire \SR_Y[4]_i_15_n_0 ;
- wire \SR_Y[4]_i_16_n_0 ;
- wire \SR_Y[4]_i_17_n_0 ;
- wire \SR_Y[4]_i_18_n_0 ;
- wire \SR_Y[4]_i_19_n_0 ;
- wire \SR_Y[4]_i_20_n_0 ;
- wire \SR_Y[4]_i_21_n_0 ;
- wire \SR_Y[4]_i_22_n_0 ;
- wire \SR_Y[4]_i_23_n_0 ;
- wire \SR_Y[4]_i_24_n_0 ;
- wire \SR_Y[4]_i_25_n_0 ;
- wire \SR_Y[4]_i_26_n_0 ;
- wire \SR_Y[4]_i_28_n_0 ;
- wire \SR_Y[4]_i_29_n_0 ;
- wire \SR_Y[4]_i_30_n_0 ;
- wire \SR_Y[4]_i_32_n_0 ;
- wire \SR_Y[4]_i_33_n_0 ;
- wire \SR_Y[4]_i_34_n_0 ;
- wire \SR_Y[4]_i_35_n_0 ;
- wire \SR_Y[4]_i_36_n_0 ;
- wire \SR_Y[4]_i_37_n_0 ;
- wire \SR_Y[4]_i_38_n_0 ;
- wire \SR_Y[4]_i_39_n_0 ;
- wire \SR_Y[4]_i_40_n_0 ;
- wire \SR_Y[4]_i_41_n_0 ;
- wire \SR_Y[4]_i_42_n_0 ;
- wire \SR_Y[4]_i_43_n_0 ;
- wire \SR_Y[4]_i_44_n_0 ;
- wire \SR_Y[4]_i_45_n_0 ;
- wire \SR_Y[4]_i_46_n_0 ;
- wire \SR_Y[4]_i_47_n_0 ;
- wire \SR_Y[4]_i_48_n_0 ;
- wire \SR_Y[4]_i_49_n_0 ;
- wire \SR_Y[4]_i_50_n_0 ;
- wire \SR_Y[4]_i_51_n_0 ;
- wire \SR_Y[4]_i_5_n_0 ;
- wire \SR_Y[4]_i_6_n_0 ;
- wire \SR_Y[4]_i_7_n_0 ;
- wire \SR_Y[4]_i_8_n_0 ;
- wire \SR_Y[7]_i_11_n_0 ;
- wire \SR_Y[7]_i_12_n_0 ;
- wire \SR_Y[7]_i_13_n_0 ;
- wire \SR_Y[7]_i_15_n_0 ;
- wire \SR_Y[7]_i_16_n_0 ;
- wire \SR_Y[7]_i_17_n_0 ;
- wire \SR_Y[7]_i_18_n_0 ;
- wire \SR_Y[7]_i_19_n_0 ;
- wire \SR_Y[7]_i_20_n_0 ;
- wire \SR_Y[7]_i_21_n_0 ;
- wire \SR_Y[7]_i_22_n_0 ;
- wire \SR_Y[7]_i_25_n_0 ;
- wire \SR_Y[7]_i_26_n_0 ;
- wire \SR_Y[7]_i_27_n_0 ;
- wire \SR_Y[7]_i_28_n_0 ;
- wire \SR_Y[7]_i_3_n_0 ;
- wire \SR_Y[7]_i_42_n_0 ;
- wire \SR_Y[7]_i_43_n_0 ;
- wire \SR_Y[7]_i_44_n_0 ;
- wire \SR_Y[7]_i_45_n_0 ;
- wire \SR_Y[7]_i_46_n_0 ;
- wire \SR_Y[7]_i_47_n_0 ;
- wire \SR_Y[7]_i_48_n_0 ;
- wire \SR_Y[7]_i_49_n_0 ;
- wire \SR_Y[7]_i_50_n_0 ;
- wire \SR_Y[7]_i_51_n_0 ;
- wire \SR_Y[7]_i_52_n_0 ;
- wire \SR_Y[7]_i_53_n_0 ;
- wire \SR_Y[7]_i_54_n_0 ;
- wire \SR_Y[7]_i_55_n_0 ;
- wire \SR_Y[7]_i_56_n_0 ;
- wire \SR_Y[7]_i_57_n_0 ;
- wire \SR_Y[7]_i_5_n_0 ;
- wire \SR_Y[7]_i_6_n_0 ;
- wire \SR_Y[7]_i_7_n_0 ;
- wire \SR_Y[7]_i_9_n_0 ;
- wire \SR_Y_reg[4]_i_10_n_0 ;
- wire \SR_Y_reg[4]_i_10_n_1 ;
- wire \SR_Y_reg[4]_i_10_n_2 ;
- wire \SR_Y_reg[4]_i_10_n_3 ;
- wire \SR_Y_reg[4]_i_27_n_0 ;
- wire \SR_Y_reg[4]_i_27_n_1 ;
- wire \SR_Y_reg[4]_i_27_n_2 ;
- wire \SR_Y_reg[4]_i_27_n_3 ;
- wire \SR_Y_reg[4]_i_27_n_4 ;
- wire \SR_Y_reg[4]_i_27_n_5 ;
- wire \SR_Y_reg[4]_i_27_n_6 ;
- wire \SR_Y_reg[4]_i_27_n_7 ;
- wire \SR_Y_reg[4]_i_2_n_0 ;
- wire \SR_Y_reg[4]_i_2_n_1 ;
- wire \SR_Y_reg[4]_i_2_n_2 ;
- wire \SR_Y_reg[4]_i_2_n_3 ;
- wire \SR_Y_reg[4]_i_3_n_0 ;
- wire \SR_Y_reg[4]_i_3_n_1 ;
- wire \SR_Y_reg[4]_i_3_n_2 ;
- wire \SR_Y_reg[4]_i_3_n_3 ;
- wire \SR_Y_reg[4]_i_3_n_5 ;
- wire \SR_Y_reg[4]_i_4_n_0 ;
- wire \SR_Y_reg[4]_i_4_n_1 ;
- wire \SR_Y_reg[4]_i_4_n_2 ;
- wire \SR_Y_reg[4]_i_4_n_3 ;
- wire \SR_Y_reg[4]_i_9_n_0 ;
- wire \SR_Y_reg[4]_i_9_n_1 ;
- wire \SR_Y_reg[4]_i_9_n_2 ;
- wire \SR_Y_reg[4]_i_9_n_3 ;
- wire \SR_Y_reg[7]_i_10_n_0 ;
- wire \SR_Y_reg[7]_i_10_n_1 ;
- wire \SR_Y_reg[7]_i_10_n_2 ;
- wire \SR_Y_reg[7]_i_10_n_3 ;
- wire \SR_Y_reg[7]_i_10_n_4 ;
- wire \SR_Y_reg[7]_i_10_n_5 ;
- wire \SR_Y_reg[7]_i_10_n_6 ;
- wire \SR_Y_reg[7]_i_10_n_7 ;
- wire \SR_Y_reg[7]_i_14_n_1 ;
- wire \SR_Y_reg[7]_i_14_n_3 ;
- wire \SR_Y_reg[7]_i_14_n_6 ;
- wire \SR_Y_reg[7]_i_14_n_7 ;
- wire \SR_Y_reg[7]_i_2_n_2 ;
- wire \SR_Y_reg[7]_i_2_n_3 ;
- wire \SR_Y_reg[7]_i_33_n_0 ;
- wire \SR_Y_reg[7]_i_34_n_0 ;
- wire \SR_Y_reg[7]_i_35_n_0 ;
- wire \SR_Y_reg[7]_i_36_n_0 ;
- wire \SR_Y_reg[7]_i_38_n_0 ;
- wire \SR_Y_reg[7]_i_39_n_0 ;
- wire \SR_Y_reg[7]_i_40_n_0 ;
- wire \SR_Y_reg[7]_i_41_n_0 ;
- wire \SR_Y_reg[7]_i_4_n_1 ;
- wire \SR_Y_reg[7]_i_4_n_2 ;
- wire \SR_Y_reg[7]_i_4_n_3 ;
- wire \SR_Y_reg[7]_i_8_n_2 ;
- wire \SR_Y_reg[7]_i_8_n_3 ;
- wire \SR_Y_reg[7]_i_8_n_5 ;
- wire \SR_Y_reg[7]_i_8_n_6 ;
- wire \SR_Y_reg[7]_i_8_n_7 ;
- wire \SR_readAddress[0]_i_1_n_0 ;
- wire \SR_readAddress[1]_i_1_n_0 ;
- wire \SR_readAddress[2]_i_1_n_0 ;
- wire \SR_readAddress[3]_i_1_n_0 ;
- wire \SR_readAddress[3]_i_2_n_0 ;
- wire [3:0]SR_readAddress_reg__0;
- wire [7:0]\SR_shiftRegister[0] ;
- wire [7:0]\SR_shiftRegister_reg[0]__0 ;
- wire [7:0]\SR_shiftRegister_reg[10]__0 ;
- wire [7:0]\SR_shiftRegister_reg[11]__0 ;
- wire [7:0]\SR_shiftRegister_reg[12]__0 ;
- wire [7:0]\SR_shiftRegister_reg[13]__0 ;
- wire [7:0]\SR_shiftRegister_reg[14]__0 ;
- wire [7:0]\SR_shiftRegister_reg[15]__0 ;
- wire [7:0]\SR_shiftRegister_reg[1]__0 ;
- wire [7:0]\SR_shiftRegister_reg[2]__0 ;
- wire [7:0]\SR_shiftRegister_reg[3]__0 ;
- wire [7:0]\SR_shiftRegister_reg[4]__0 ;
- wire [7:0]\SR_shiftRegister_reg[5]__0 ;
- wire [7:0]\SR_shiftRegister_reg[6]__0 ;
- wire [7:0]\SR_shiftRegister_reg[7]__0 ;
- wire [7:0]\SR_shiftRegister_reg[8]__0 ;
- wire [7:0]\SR_shiftRegister_reg[9]__0 ;
- wire \SR_sum[0]_i_10_n_0 ;
- wire \SR_sum[0]_i_13_n_0 ;
- wire \SR_sum[0]_i_14_n_0 ;
- wire \SR_sum[0]_i_15_n_0 ;
- wire \SR_sum[0]_i_16_n_0 ;
- wire \SR_sum[0]_i_17_n_0 ;
- wire \SR_sum[0]_i_18_n_0 ;
- wire \SR_sum[0]_i_19_n_0 ;
- wire \SR_sum[0]_i_1_n_0 ;
- wire \SR_sum[0]_i_20_n_0 ;
- wire \SR_sum[0]_i_21_n_0 ;
- wire \SR_sum[0]_i_22_n_0 ;
- wire \SR_sum[0]_i_23_n_0 ;
- wire \SR_sum[0]_i_24_n_0 ;
- wire \SR_sum[0]_i_25_n_0 ;
- wire \SR_sum[0]_i_26_n_0 ;
- wire \SR_sum[0]_i_27_n_0 ;
- wire \SR_sum[0]_i_31_n_0 ;
- wire \SR_sum[0]_i_32_n_0 ;
- wire \SR_sum[0]_i_33_n_0 ;
- wire \SR_sum[0]_i_3_n_0 ;
- wire \SR_sum[0]_i_45_n_0 ;
- wire \SR_sum[0]_i_46_n_0 ;
- wire \SR_sum[0]_i_47_n_0 ;
- wire \SR_sum[0]_i_48_n_0 ;
- wire \SR_sum[0]_i_49_n_0 ;
- wire \SR_sum[0]_i_4_n_0 ;
- wire \SR_sum[0]_i_50_n_0 ;
- wire \SR_sum[0]_i_51_n_0 ;
- wire \SR_sum[0]_i_52_n_0 ;
- wire \SR_sum[0]_i_53_n_0 ;
- wire \SR_sum[0]_i_54_n_0 ;
- wire \SR_sum[0]_i_55_n_0 ;
- wire \SR_sum[0]_i_56_n_0 ;
- wire \SR_sum[0]_i_57_n_0 ;
- wire \SR_sum[0]_i_58_n_0 ;
- wire \SR_sum[0]_i_59_n_0 ;
- wire \SR_sum[0]_i_5_n_0 ;
- wire \SR_sum[0]_i_60_n_0 ;
- wire \SR_sum[0]_i_6_n_0 ;
- wire \SR_sum[0]_i_7_n_0 ;
- wire \SR_sum[0]_i_8_n_0 ;
- wire \SR_sum[0]_i_9_n_0 ;
- wire \SR_sum[12]_i_2_n_0 ;
- wire \SR_sum[12]_i_3_n_0 ;
- wire \SR_sum[12]_i_4_n_0 ;
- wire \SR_sum[12]_i_5_n_0 ;
- wire \SR_sum[12]_i_6_n_0 ;
- wire \SR_sum[4]_i_2_n_0 ;
- wire \SR_sum[4]_i_3_n_0 ;
- wire \SR_sum[4]_i_4_n_0 ;
- wire \SR_sum[4]_i_5_n_0 ;
- wire \SR_sum[4]_i_6_n_0 ;
- wire \SR_sum[4]_i_7_n_0 ;
- wire \SR_sum[4]_i_8_n_0 ;
- wire \SR_sum[4]_i_9_n_0 ;
- wire \SR_sum[8]_i_2_n_0 ;
- wire \SR_sum[8]_i_3_n_0 ;
- wire \SR_sum[8]_i_4_n_0 ;
- wire \SR_sum[8]_i_5_n_0 ;
- wire \SR_sum[8]_i_6_n_0 ;
- wire \SR_sum[8]_i_7_n_0 ;
- wire \SR_sum[8]_i_8_n_0 ;
- wire \SR_sum[8]_i_9_n_0 ;
- wire [14:0]SR_sum_reg;
- wire \SR_sum_reg[0]_i_11_n_0 ;
- wire \SR_sum_reg[0]_i_11_n_1 ;
- wire \SR_sum_reg[0]_i_11_n_2 ;
- wire \SR_sum_reg[0]_i_11_n_3 ;
- wire \SR_sum_reg[0]_i_11_n_4 ;
- wire \SR_sum_reg[0]_i_11_n_5 ;
- wire \SR_sum_reg[0]_i_11_n_6 ;
- wire \SR_sum_reg[0]_i_11_n_7 ;
- wire \SR_sum_reg[0]_i_12_n_0 ;
- wire \SR_sum_reg[0]_i_12_n_1 ;
- wire \SR_sum_reg[0]_i_12_n_2 ;
- wire \SR_sum_reg[0]_i_12_n_3 ;
- wire \SR_sum_reg[0]_i_12_n_4 ;
- wire \SR_sum_reg[0]_i_2_n_0 ;
- wire \SR_sum_reg[0]_i_2_n_1 ;
- wire \SR_sum_reg[0]_i_2_n_2 ;
- wire \SR_sum_reg[0]_i_2_n_3 ;
- wire \SR_sum_reg[0]_i_2_n_4 ;
- wire \SR_sum_reg[0]_i_2_n_5 ;
- wire \SR_sum_reg[0]_i_2_n_6 ;
- wire \SR_sum_reg[0]_i_2_n_7 ;
- wire \SR_sum_reg[0]_i_37_n_0 ;
- wire \SR_sum_reg[0]_i_38_n_0 ;
- wire \SR_sum_reg[0]_i_39_n_0 ;
- wire \SR_sum_reg[0]_i_40_n_0 ;
- wire \SR_sum_reg[0]_i_41_n_0 ;
- wire \SR_sum_reg[0]_i_42_n_0 ;
- wire \SR_sum_reg[0]_i_43_n_0 ;
- wire \SR_sum_reg[0]_i_44_n_0 ;
- wire \SR_sum_reg[12]_i_1_n_2 ;
- wire \SR_sum_reg[12]_i_1_n_3 ;
- wire \SR_sum_reg[12]_i_1_n_5 ;
- wire \SR_sum_reg[12]_i_1_n_6 ;
- wire \SR_sum_reg[12]_i_1_n_7 ;
- wire \SR_sum_reg[4]_i_1_n_0 ;
- wire \SR_sum_reg[4]_i_1_n_1 ;
- wire \SR_sum_reg[4]_i_1_n_2 ;
- wire \SR_sum_reg[4]_i_1_n_3 ;
- wire \SR_sum_reg[4]_i_1_n_4 ;
- wire \SR_sum_reg[4]_i_1_n_5 ;
- wire \SR_sum_reg[4]_i_1_n_6 ;
- wire \SR_sum_reg[4]_i_1_n_7 ;
- wire \SR_sum_reg[8]_i_1_n_0 ;
- wire \SR_sum_reg[8]_i_1_n_1 ;
- wire \SR_sum_reg[8]_i_1_n_2 ;
- wire \SR_sum_reg[8]_i_1_n_3 ;
- wire \SR_sum_reg[8]_i_1_n_4 ;
- wire \SR_sum_reg[8]_i_1_n_5 ;
- wire \SR_sum_reg[8]_i_1_n_6 ;
- wire \SR_sum_reg[8]_i_1_n_7 ;
- wire [7:0]p_0_in;
- wire [3:0]\NLW_SR_Y_reg[4]_i_10_O_UNCONNECTED ;
- wire [3:0]\NLW_SR_Y_reg[4]_i_3_O_UNCONNECTED ;
- wire [3:0]\NLW_SR_Y_reg[7]_i_14_CO_UNCONNECTED ;
-
- GND GND
- (.G(\<const0> ));
- BUFG I_clock_IBUF_BUFG_inst
- (.I(I_clock_IBUF),
- .O(I_clock_IBUF_BUFG));
- IBUF I_clock_IBUF_inst
- (.I(I_clock),
- .O(I_clock_IBUF));
- IBUF I_incrAddress_IBUF_inst
- (.I(I_incrAddress),
- .O(I_incrAddress_IBUF));
- IBUF I_initAddress_IBUF_inst
- (.I(I_initAddress),
- .O(I_initAddress_IBUF));
- IBUF I_initSum_IBUF_inst
- (.I(I_initSum),
- .O(I_initSum_IBUF));
- IBUF \I_inputSample_IBUF[0]_inst
- (.I(I_inputSample[0]),
- .O(I_inputSample_IBUF[0]));
- IBUF \I_inputSample_IBUF[1]_inst
- (.I(I_inputSample[1]),
- .O(I_inputSample_IBUF[1]));
- IBUF \I_inputSample_IBUF[2]_inst
- (.I(I_inputSample[2]),
- .O(I_inputSample_IBUF[2]));
- IBUF \I_inputSample_IBUF[3]_inst
- (.I(I_inputSample[3]),
- .O(I_inputSample_IBUF[3]));
- IBUF \I_inputSample_IBUF[4]_inst
- (.I(I_inputSample[4]),
- .O(I_inputSample_IBUF[4]));
- IBUF \I_inputSample_IBUF[5]_inst
- (.I(I_inputSample[5]),
- .O(I_inputSample_IBUF[5]));
- IBUF \I_inputSample_IBUF[6]_inst
- (.I(I_inputSample[6]),
- .O(I_inputSample_IBUF[6]));
- IBUF \I_inputSample_IBUF[7]_inst
- (.I(I_inputSample[7]),
- .O(I_inputSample_IBUF[7]));
- IBUF I_loadShift_IBUF_inst
- (.I(I_loadShift),
- .O(I_loadShift_IBUF));
- IBUF I_loadSum_IBUF_inst
- (.I(I_loadSum),
- .O(I_loadSum_IBUF));
- IBUF I_loadY_IBUF_inst
- (.I(I_loadY),
- .O(I_loadY_IBUF));
- IBUF I_reset_IBUF_inst
- (.I(I_reset),
- .O(I_reset_IBUF));
- OBUF \O_Y_OBUF[0]_inst
- (.I(O_Y_OBUF[0]),
- .O(O_Y[0]));
- OBUF \O_Y_OBUF[1]_inst
- (.I(O_Y_OBUF[1]),
- .O(O_Y[1]));
- OBUF \O_Y_OBUF[2]_inst
- (.I(O_Y_OBUF[2]),
- .O(O_Y[2]));
- OBUF \O_Y_OBUF[3]_inst
- (.I(O_Y_OBUF[3]),
- .O(O_Y[3]));
- OBUF \O_Y_OBUF[4]_inst
- (.I(O_Y_OBUF[4]),
- .O(O_Y[4]));
- OBUF \O_Y_OBUF[5]_inst
- (.I(O_Y_OBUF[5]),
- .O(O_Y[5]));
- OBUF \O_Y_OBUF[6]_inst
- (.I(O_Y_OBUF[6]),
- .O(O_Y[6]));
- OBUF \O_Y_OBUF[7]_inst
- (.I(O_Y_OBUF[7]),
- .O(O_Y[7]));
- OBUF O_processingDone_OBUF_inst
- (.I(O_processingDone_OBUF),
- .O(O_processingDone));
- LUT3 #(
- .INIT(8'h80))
- O_processingDone_OBUF_inst_i_1
- (.I0(SR_readAddress_reg__0[1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[2]),
- .O(O_processingDone_OBUF));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[0]_i_1
- (.I0(\SR_Y_reg[4]_i_3_n_5 ),
- .I1(L[7]),
- .O(p_0_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT3 #(
- .INIT(8'h78))
- \SR_Y[1]_i_1
- (.I0(\SR_Y_reg[4]_i_3_n_5 ),
- .I1(L[7]),
- .I2(L[8]),
- .O(p_0_in[1]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h7F80))
- \SR_Y[2]_i_1
- (.I0(L[7]),
- .I1(\SR_Y_reg[4]_i_3_n_5 ),
- .I2(L[8]),
- .I3(L[9]),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \SR_Y[3]_i_1
- (.I0(L[8]),
- .I1(\SR_Y_reg[4]_i_3_n_5 ),
- .I2(L[7]),
- .I3(L[9]),
- .I4(L[10]),
- .O(p_0_in[3]));
- LUT6 #(
- .INIT(64'h7FFFFFFF80000000))
- \SR_Y[4]_i_1
- (.I0(L[9]),
- .I1(L[7]),
- .I2(\SR_Y_reg[4]_i_3_n_5 ),
- .I3(L[8]),
- .I4(L[10]),
- .I5(L[11]),
- .O(p_0_in[4]));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_11
- (.I0(SC_MultResult[7]),
- .I1(SR_sum_reg[7]),
- .O(\SR_Y[4]_i_11_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_12
- (.I0(SC_MultResult[6]),
- .I1(SR_sum_reg[6]),
- .O(\SR_Y[4]_i_12_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_13
- (.I0(SC_MultResult[5]),
- .I1(SR_sum_reg[5]),
- .O(\SR_Y[4]_i_13_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_14
- (.I0(SC_MultResult[4]),
- .I1(SR_sum_reg[4]),
- .O(\SR_Y[4]_i_14_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \SR_Y[4]_i_15
- (.I0(\SR_Y_reg[7]_i_10_n_5 ),
- .I1(\SR_Y_reg[7]_i_14_n_6 ),
- .O(\SR_Y[4]_i_15_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \SR_Y[4]_i_16
- (.I0(\SR_Y_reg[7]_i_10_n_6 ),
- .I1(\SR_Y_reg[7]_i_14_n_7 ),
- .O(\SR_Y[4]_i_16_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \SR_Y[4]_i_17
- (.I0(\SR_Y_reg[4]_i_27_n_4 ),
- .I1(\SR_Y_reg[7]_i_10_n_7 ),
- .O(\SR_Y[4]_i_17_n_0 ));
- LUT2 #(
- .INIT(4'h9))
- \SR_Y[4]_i_18
- (.I0(\SR_Y_reg[7]_i_10_n_7 ),
- .I1(\SR_Y_reg[4]_i_27_n_4 ),
- .O(\SR_Y[4]_i_18_n_0 ));
- LUT4 #(
- .INIT(16'h8778))
- \SR_Y[4]_i_19
- (.I0(\SR_Y_reg[7]_i_14_n_6 ),
- .I1(\SR_Y_reg[7]_i_10_n_5 ),
- .I2(\SR_Y_reg[7]_i_10_n_4 ),
- .I3(\SR_Y_reg[7]_i_14_n_1 ),
- .O(\SR_Y[4]_i_19_n_0 ));
- LUT4 #(
- .INIT(16'h8778))
- \SR_Y[4]_i_20
- (.I0(\SR_Y_reg[7]_i_14_n_7 ),
- .I1(\SR_Y_reg[7]_i_10_n_6 ),
- .I2(\SR_Y_reg[7]_i_10_n_5 ),
- .I3(\SR_Y_reg[7]_i_14_n_6 ),
- .O(\SR_Y[4]_i_20_n_0 ));
- LUT4 #(
- .INIT(16'hE11E))
- \SR_Y[4]_i_21
- (.I0(\SR_Y_reg[7]_i_10_n_7 ),
- .I1(\SR_Y_reg[4]_i_27_n_4 ),
- .I2(\SR_Y_reg[7]_i_10_n_6 ),
- .I3(\SR_Y_reg[7]_i_14_n_7 ),
- .O(\SR_Y[4]_i_21_n_0 ));
- LUT4 #(
- .INIT(16'h6999))
- \SR_Y[4]_i_22
- (.I0(\SR_Y_reg[7]_i_10_n_7 ),
- .I1(\SR_Y_reg[4]_i_27_n_4 ),
- .I2(\SR_Y_reg[4]_i_27_n_5 ),
- .I3(\SR_sum_reg[0]_i_11_n_4 ),
- .O(\SR_Y[4]_i_22_n_0 ));
- LUT3 #(
- .INIT(8'h96))
- \SR_Y[4]_i_23
- (.I0(\SR_sum_reg[0]_i_11_n_7 ),
- .I1(\SR_sum_reg[0]_i_12_n_4 ),
- .I2(SR_sum_reg[3]),
- .O(\SR_Y[4]_i_23_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_24
- (.I0(SC_MultResult[2]),
- .I1(SR_sum_reg[2]),
- .O(\SR_Y[4]_i_24_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_25
- (.I0(SC_MultResult[1]),
- .I1(SR_sum_reg[1]),
- .O(\SR_Y[4]_i_25_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_26
- (.I0(SC_MultResult[0]),
- .I1(SR_sum_reg[0]),
- .O(\SR_Y[4]_i_26_n_0 ));
- LUT3 #(
- .INIT(8'h96))
- \SR_Y[4]_i_28
- (.I0(\SR_sum_reg[0]_i_11_n_5 ),
- .I1(\SR_sum_reg[0]_i_11_n_4 ),
- .I2(\SR_Y_reg[4]_i_27_n_5 ),
- .O(\SR_Y[4]_i_28_n_0 ));
- LUT2 #(
- .INIT(4'h9))
- \SR_Y[4]_i_29
- (.I0(\SR_sum_reg[0]_i_11_n_5 ),
- .I1(\SR_Y_reg[4]_i_27_n_6 ),
- .O(\SR_Y[4]_i_29_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_30
- (.I0(\SR_Y_reg[4]_i_27_n_7 ),
- .I1(\SR_sum_reg[0]_i_11_n_6 ),
- .O(\SR_Y[4]_i_30_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_31
- (.I0(\SR_sum_reg[0]_i_12_n_4 ),
- .I1(\SR_sum_reg[0]_i_11_n_7 ),
- .O(SC_MultResult[3]));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_32
- (.I0(\SR_Y[4]_i_40_n_0 ),
- .I1(\SR_Y[4]_i_41_n_0 ),
- .I2(\SR_Y[4]_i_42_n_0 ),
- .O(\SR_Y[4]_i_32_n_0 ));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_33
- (.I0(\SR_Y[4]_i_43_n_0 ),
- .I1(\SR_Y[4]_i_44_n_0 ),
- .I2(\SR_Y[4]_i_45_n_0 ),
- .O(\SR_Y[4]_i_33_n_0 ));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_34
- (.I0(\SR_Y[4]_i_46_n_0 ),
- .I1(\SR_Y[4]_i_47_n_0 ),
- .I2(\SR_Y[4]_i_48_n_0 ),
- .O(\SR_Y[4]_i_34_n_0 ));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_35
- (.I0(\SR_sum[0]_i_32_n_0 ),
- .I1(\SR_sum[0]_i_31_n_0 ),
- .I2(\SR_sum[0]_i_33_n_0 ),
- .O(\SR_Y[4]_i_35_n_0 ));
- LUT4 #(
- .INIT(16'h6996))
- \SR_Y[4]_i_36
- (.I0(\SR_Y[4]_i_32_n_0 ),
- .I1(\SR_Y[4]_i_49_n_0 ),
- .I2(\SR_Y[4]_i_50_n_0 ),
- .I3(\SR_Y[4]_i_51_n_0 ),
- .O(\SR_Y[4]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'h17E8E817E81717E8))
- \SR_Y[4]_i_37
- (.I0(\SR_Y[4]_i_45_n_0 ),
- .I1(\SR_Y[4]_i_44_n_0 ),
- .I2(\SR_Y[4]_i_43_n_0 ),
- .I3(\SR_Y[4]_i_41_n_0 ),
- .I4(\SR_Y[4]_i_40_n_0 ),
- .I5(\SR_Y[4]_i_42_n_0 ),
- .O(\SR_Y[4]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'h17E8E817E81717E8))
- \SR_Y[4]_i_38
- (.I0(\SR_Y[4]_i_48_n_0 ),
- .I1(\SR_Y[4]_i_47_n_0 ),
- .I2(\SR_Y[4]_i_46_n_0 ),
- .I3(\SR_Y[4]_i_44_n_0 ),
- .I4(\SR_Y[4]_i_43_n_0 ),
- .I5(\SR_Y[4]_i_45_n_0 ),
- .O(\SR_Y[4]_i_38_n_0 ));
- LUT6 #(
- .INIT(64'h17E8E817E81717E8))
- \SR_Y[4]_i_39
- (.I0(\SR_sum[0]_i_33_n_0 ),
- .I1(\SR_sum[0]_i_31_n_0 ),
- .I2(\SR_sum[0]_i_32_n_0 ),
- .I3(\SR_Y[4]_i_47_n_0 ),
- .I4(\SR_Y[4]_i_46_n_0 ),
- .I5(\SR_Y[4]_i_48_n_0 ),
- .O(\SR_Y[4]_i_39_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_40
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_40_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_41
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_41_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_42
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_42_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_43
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_43_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_44
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_44_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_45
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_45_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_46
- (.I0(\SR_shiftRegister[0] [2]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_46_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_47
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_47_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_48
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_48_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_49
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_49_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_5
- (.I0(SC_MultResult[11]),
- .I1(SR_sum_reg[11]),
- .O(\SR_Y[4]_i_5_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_50
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_50_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_51
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_51_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_6
- (.I0(SC_MultResult[10]),
- .I1(SR_sum_reg[10]),
- .O(\SR_Y[4]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_7
- (.I0(SC_MultResult[9]),
- .I1(SR_sum_reg[9]),
- .O(\SR_Y[4]_i_7_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_8
- (.I0(SC_MultResult[8]),
- .I1(SR_sum_reg[8]),
- .O(\SR_Y[4]_i_8_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[5]_i_1
- (.I0(\SR_Y[7]_i_3_n_0 ),
- .I1(L[12]),
- .O(p_0_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT3 #(
- .INIT(8'h78))
- \SR_Y[6]_i_1
- (.I0(\SR_Y[7]_i_3_n_0 ),
- .I1(L[12]),
- .I2(L[13]),
- .O(p_0_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h7F80))
- \SR_Y[7]_i_1
- (.I0(L[12]),
- .I1(\SR_Y[7]_i_3_n_0 ),
- .I2(L[13]),
- .I3(L[14]),
- .O(p_0_in[7]));
- LUT6 #(
- .INIT(64'hFFF55FFFDDF55F77))
- \SR_Y[7]_i_11
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [6]),
- .O(\SR_Y[7]_i_11_n_0 ));
- LUT5 #(
- .INIT(32'hFDDD777F))
- \SR_Y[7]_i_12
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[7]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hDDC00377FFFFFFFF))
- \SR_Y[7]_i_13
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [7]),
- .O(\SR_Y[7]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_15
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [5]),
- .O(\SR_Y[7]_i_15_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_16
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [4]),
- .O(\SR_Y[7]_i_16_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_17
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [3]),
- .O(\SR_Y[7]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_18
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_Y[7]_i_18_n_0 ));
- LUT5 #(
- .INIT(32'hD32C6060))
- \SR_Y[7]_i_19
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(\SR_shiftRegister[0] [6]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [7]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h2CD39F9F))
- \SR_Y[7]_i_20
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(\SR_shiftRegister[0] [5]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [6]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_20_n_0 ));
- LUT5 #(
- .INIT(32'h2CD39F9F))
- \SR_Y[7]_i_21
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(\SR_shiftRegister[0] [4]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [5]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_21_n_0 ));
- LUT5 #(
- .INIT(32'h2CD39F9F))
- \SR_Y[7]_i_22
- (.I0(\SR_shiftRegister[0] [2]),
- .I1(\SR_shiftRegister[0] [3]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [4]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'h134001C400000000))
- \SR_Y[7]_i_25
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [6]),
- .O(\SR_Y[7]_i_25_n_0 ));
- LUT3 #(
- .INIT(8'h71))
- \SR_Y[7]_i_26
- (.I0(\SR_Y[4]_i_50_n_0 ),
- .I1(\SR_Y[4]_i_49_n_0 ),
- .I2(\SR_Y[4]_i_51_n_0 ),
- .O(\SR_Y[7]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hCE3FFCB3DD7FFD77))
- \SR_Y[7]_i_27
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [7]),
- .O(\SR_Y[7]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'h8171FC0C1EEE3CCC))
- \SR_Y[7]_i_28
- (.I0(SC_multOperand2[0]),
- .I1(\SR_Y[4]_i_50_n_0 ),
- .I2(\SR_shiftRegister[0] [6]),
- .I3(SC_multOperand2[2]),
- .I4(\SR_shiftRegister[0] [7]),
- .I5(SC_multOperand2[1]),
- .O(\SR_Y[7]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \SR_Y[7]_i_3
- (.I0(L[11]),
- .I1(L[9]),
- .I2(L[7]),
- .I3(\SR_Y_reg[4]_i_3_n_5 ),
- .I4(L[8]),
- .I5(L[10]),
- .O(\SR_Y[7]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h542A))
- \SR_Y[7]_i_31
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .O(SC_multOperand2[4]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT4 #(
- .INIT(16'h724E))
- \SR_Y[7]_i_32
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .O(SC_multOperand2[3]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT4 #(
- .INIT(16'h6006))
- \SR_Y[7]_i_37
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[1]),
- .O(SC_multOperand2[0]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_42
- (.I0(\SR_shiftRegister_reg[3]__0 [7]),
- .I1(\SR_shiftRegister_reg[2]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [7]),
- .O(\SR_Y[7]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_43
- (.I0(\SR_shiftRegister_reg[7]__0 [7]),
- .I1(\SR_shiftRegister_reg[6]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [7]),
- .O(\SR_Y[7]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_44
- (.I0(\SR_shiftRegister_reg[11]__0 [7]),
- .I1(\SR_shiftRegister_reg[10]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [7]),
- .O(\SR_Y[7]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_45
- (.I0(\SR_shiftRegister_reg[15]__0 [7]),
- .I1(\SR_shiftRegister_reg[14]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [7]),
- .O(\SR_Y[7]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_46
- (.I0(\SR_shiftRegister_reg[3]__0 [6]),
- .I1(\SR_shiftRegister_reg[2]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [6]),
- .O(\SR_Y[7]_i_46_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_47
- (.I0(\SR_shiftRegister_reg[7]__0 [6]),
- .I1(\SR_shiftRegister_reg[6]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [6]),
- .O(\SR_Y[7]_i_47_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_48
- (.I0(\SR_shiftRegister_reg[11]__0 [6]),
- .I1(\SR_shiftRegister_reg[10]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [6]),
- .O(\SR_Y[7]_i_48_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_49
- (.I0(\SR_shiftRegister_reg[15]__0 [6]),
- .I1(\SR_shiftRegister_reg[14]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [6]),
- .O(\SR_Y[7]_i_49_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[7]_i_5
- (.I0(SR_sum_reg[14]),
- .I1(SC_MultResult[14]),
- .O(\SR_Y[7]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_50
- (.I0(\SR_shiftRegister_reg[3]__0 [5]),
- .I1(\SR_shiftRegister_reg[2]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [5]),
- .O(\SR_Y[7]_i_50_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_51
- (.I0(\SR_shiftRegister_reg[7]__0 [5]),
- .I1(\SR_shiftRegister_reg[6]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [5]),
- .O(\SR_Y[7]_i_51_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_52
- (.I0(\SR_shiftRegister_reg[11]__0 [5]),
- .I1(\SR_shiftRegister_reg[10]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [5]),
- .O(\SR_Y[7]_i_52_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_53
- (.I0(\SR_shiftRegister_reg[15]__0 [5]),
- .I1(\SR_shiftRegister_reg[14]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [5]),
- .O(\SR_Y[7]_i_53_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_54
- (.I0(\SR_shiftRegister_reg[3]__0 [4]),
- .I1(\SR_shiftRegister_reg[2]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [4]),
- .O(\SR_Y[7]_i_54_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_55
- (.I0(\SR_shiftRegister_reg[7]__0 [4]),
- .I1(\SR_shiftRegister_reg[6]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [4]),
- .O(\SR_Y[7]_i_55_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_56
- (.I0(\SR_shiftRegister_reg[11]__0 [4]),
- .I1(\SR_shiftRegister_reg[10]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [4]),
- .O(\SR_Y[7]_i_56_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_57
- (.I0(\SR_shiftRegister_reg[15]__0 [4]),
- .I1(\SR_shiftRegister_reg[14]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [4]),
- .O(\SR_Y[7]_i_57_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[7]_i_6
- (.I0(SC_MultResult[13]),
- .I1(SR_sum_reg[13]),
- .O(\SR_Y[7]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[7]_i_7
- (.I0(SC_MultResult[12]),
- .I1(SR_sum_reg[12]),
- .O(\SR_Y[7]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h78))
- \SR_Y[7]_i_9
- (.I0(\SR_Y_reg[7]_i_14_n_1 ),
- .I1(\SR_Y_reg[7]_i_10_n_4 ),
- .I2(\SR_Y_reg[7]_i_8_n_7 ),
- .O(\SR_Y[7]_i_9_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[0]),
- .Q(O_Y_OBUF[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[1]),
- .Q(O_Y_OBUF[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[2]),
- .Q(O_Y_OBUF[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[3]),
- .Q(O_Y_OBUF[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[4]),
- .Q(O_Y_OBUF[4]));
- CARRY4 \SR_Y_reg[4]_i_10
- (.CI(\<const0> ),
- .CO({\SR_Y_reg[4]_i_10_n_0 ,\SR_Y_reg[4]_i_10_n_1 ,\SR_Y_reg[4]_i_10_n_2 ,\SR_Y_reg[4]_i_10_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum_reg[0]_i_11_n_5 ,\SR_Y_reg[4]_i_27_n_6 ,\SR_Y_reg[4]_i_27_n_7 ,\SR_sum_reg[0]_i_12_n_4 }),
- .O({SC_MultResult[6:4],\NLW_SR_Y_reg[4]_i_10_O_UNCONNECTED [0]}),
- .S({\SR_Y[4]_i_28_n_0 ,\SR_Y[4]_i_29_n_0 ,\SR_Y[4]_i_30_n_0 ,SC_MultResult[3]}));
- CARRY4 \SR_Y_reg[4]_i_2
- (.CI(\SR_Y_reg[4]_i_3_n_0 ),
- .CO({\SR_Y_reg[4]_i_2_n_0 ,\SR_Y_reg[4]_i_2_n_1 ,\SR_Y_reg[4]_i_2_n_2 ,\SR_Y_reg[4]_i_2_n_3 }),
- .CYINIT(\<const0> ),
- .DI(SC_MultResult[11:8]),
- .O(L[11:8]),
- .S({\SR_Y[4]_i_5_n_0 ,\SR_Y[4]_i_6_n_0 ,\SR_Y[4]_i_7_n_0 ,\SR_Y[4]_i_8_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_27
- (.CI(\SR_sum_reg[0]_i_12_n_0 ),
- .CO({\SR_Y_reg[4]_i_27_n_0 ,\SR_Y_reg[4]_i_27_n_1 ,\SR_Y_reg[4]_i_27_n_2 ,\SR_Y_reg[4]_i_27_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_Y[4]_i_32_n_0 ,\SR_Y[4]_i_33_n_0 ,\SR_Y[4]_i_34_n_0 ,\SR_Y[4]_i_35_n_0 }),
- .O({\SR_Y_reg[4]_i_27_n_4 ,\SR_Y_reg[4]_i_27_n_5 ,\SR_Y_reg[4]_i_27_n_6 ,\SR_Y_reg[4]_i_27_n_7 }),
- .S({\SR_Y[4]_i_36_n_0 ,\SR_Y[4]_i_37_n_0 ,\SR_Y[4]_i_38_n_0 ,\SR_Y[4]_i_39_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_3
- (.CI(\SR_Y_reg[4]_i_9_n_0 ),
- .CO({\SR_Y_reg[4]_i_3_n_0 ,\SR_Y_reg[4]_i_3_n_1 ,\SR_Y_reg[4]_i_3_n_2 ,\SR_Y_reg[4]_i_3_n_3 }),
- .CYINIT(\<const0> ),
- .DI(SC_MultResult[7:4]),
- .O({L[7],\SR_Y_reg[4]_i_3_n_5 ,\NLW_SR_Y_reg[4]_i_3_O_UNCONNECTED [1:0]}),
- .S({\SR_Y[4]_i_11_n_0 ,\SR_Y[4]_i_12_n_0 ,\SR_Y[4]_i_13_n_0 ,\SR_Y[4]_i_14_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_4
- (.CI(\SR_Y_reg[4]_i_10_n_0 ),
- .CO({\SR_Y_reg[4]_i_4_n_0 ,\SR_Y_reg[4]_i_4_n_1 ,\SR_Y_reg[4]_i_4_n_2 ,\SR_Y_reg[4]_i_4_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_Y[4]_i_15_n_0 ,\SR_Y[4]_i_16_n_0 ,\SR_Y[4]_i_17_n_0 ,\SR_Y[4]_i_18_n_0 }),
- .O(SC_MultResult[10:7]),
- .S({\SR_Y[4]_i_19_n_0 ,\SR_Y[4]_i_20_n_0 ,\SR_Y[4]_i_21_n_0 ,\SR_Y[4]_i_22_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_9
- (.CI(\<const0> ),
- .CO({\SR_Y_reg[4]_i_9_n_0 ,\SR_Y_reg[4]_i_9_n_1 ,\SR_Y_reg[4]_i_9_n_2 ,\SR_Y_reg[4]_i_9_n_3 }),
- .CYINIT(\<const0> ),
- .DI({SR_sum_reg[3],SC_MultResult[2:0]}),
- .S({\SR_Y[4]_i_23_n_0 ,\SR_Y[4]_i_24_n_0 ,\SR_Y[4]_i_25_n_0 ,\SR_Y[4]_i_26_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[5]),
- .Q(O_Y_OBUF[5]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[6]),
- .Q(O_Y_OBUF[6]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[7]),
- .Q(O_Y_OBUF[7]));
- CARRY4 \SR_Y_reg[7]_i_10
- (.CI(\SR_sum_reg[0]_i_11_n_0 ),
- .CO({\SR_Y_reg[7]_i_10_n_0 ,\SR_Y_reg[7]_i_10_n_1 ,\SR_Y_reg[7]_i_10_n_2 ,\SR_Y_reg[7]_i_10_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_Y[7]_i_15_n_0 ,\SR_Y[7]_i_16_n_0 ,\SR_Y[7]_i_17_n_0 ,\SR_Y[7]_i_18_n_0 }),
- .O({\SR_Y_reg[7]_i_10_n_4 ,\SR_Y_reg[7]_i_10_n_5 ,\SR_Y_reg[7]_i_10_n_6 ,\SR_Y_reg[7]_i_10_n_7 }),
- .S({\SR_Y[7]_i_19_n_0 ,\SR_Y[7]_i_20_n_0 ,\SR_Y[7]_i_21_n_0 ,\SR_Y[7]_i_22_n_0 }));
- CARRY4 \SR_Y_reg[7]_i_14
- (.CI(\SR_Y_reg[4]_i_27_n_0 ),
- .CO({\SR_Y_reg[7]_i_14_n_1 ,\NLW_SR_Y_reg[7]_i_14_CO_UNCONNECTED [1],\SR_Y_reg[7]_i_14_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\SR_Y[7]_i_25_n_0 ,\SR_Y[7]_i_26_n_0 }),
- .O({\SR_Y_reg[7]_i_14_n_6 ,\SR_Y_reg[7]_i_14_n_7 }),
- .S({\<const0> ,\<const1> ,\SR_Y[7]_i_27_n_0 ,\SR_Y[7]_i_28_n_0 }));
- CARRY4 \SR_Y_reg[7]_i_2
- (.CI(\SR_Y_reg[4]_i_2_n_0 ),
- .CO({\SR_Y_reg[7]_i_2_n_2 ,\SR_Y_reg[7]_i_2_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,SC_MultResult[13:12]}),
- .O(L[14:12]),
- .S({\<const0> ,\SR_Y[7]_i_5_n_0 ,\SR_Y[7]_i_6_n_0 ,\SR_Y[7]_i_7_n_0 }));
- MUXF8 \SR_Y_reg[7]_i_23
- (.I0(\SR_Y_reg[7]_i_33_n_0 ),
- .I1(\SR_Y_reg[7]_i_34_n_0 ),
- .O(\SR_shiftRegister[0] [7]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_Y_reg[7]_i_24
- (.I0(\SR_Y_reg[7]_i_35_n_0 ),
- .I1(\SR_Y_reg[7]_i_36_n_0 ),
- .O(\SR_shiftRegister[0] [6]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_Y_reg[7]_i_29
- (.I0(\SR_Y_reg[7]_i_38_n_0 ),
- .I1(\SR_Y_reg[7]_i_39_n_0 ),
- .O(\SR_shiftRegister[0] [5]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_Y_reg[7]_i_30
- (.I0(\SR_Y_reg[7]_i_40_n_0 ),
- .I1(\SR_Y_reg[7]_i_41_n_0 ),
- .O(\SR_shiftRegister[0] [4]),
- .S(SR_readAddress_reg__0[3]));
- MUXF7 \SR_Y_reg[7]_i_33
- (.I0(\SR_Y[7]_i_42_n_0 ),
- .I1(\SR_Y[7]_i_43_n_0 ),
- .O(\SR_Y_reg[7]_i_33_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_34
- (.I0(\SR_Y[7]_i_44_n_0 ),
- .I1(\SR_Y[7]_i_45_n_0 ),
- .O(\SR_Y_reg[7]_i_34_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_35
- (.I0(\SR_Y[7]_i_46_n_0 ),
- .I1(\SR_Y[7]_i_47_n_0 ),
- .O(\SR_Y_reg[7]_i_35_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_36
- (.I0(\SR_Y[7]_i_48_n_0 ),
- .I1(\SR_Y[7]_i_49_n_0 ),
- .O(\SR_Y_reg[7]_i_36_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_38
- (.I0(\SR_Y[7]_i_50_n_0 ),
- .I1(\SR_Y[7]_i_51_n_0 ),
- .O(\SR_Y_reg[7]_i_38_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_39
- (.I0(\SR_Y[7]_i_52_n_0 ),
- .I1(\SR_Y[7]_i_53_n_0 ),
- .O(\SR_Y_reg[7]_i_39_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- CARRY4 \SR_Y_reg[7]_i_4
- (.CI(\SR_Y_reg[4]_i_4_n_0 ),
- .CO({\SR_Y_reg[7]_i_4_n_1 ,\SR_Y_reg[7]_i_4_n_2 ,\SR_Y_reg[7]_i_4_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\SR_Y_reg[7]_i_8_n_5 ,\<const0> ,\SR_Y_reg[7]_i_8_n_7 }),
- .O(SC_MultResult[14:11]),
- .S({\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_6 ,\SR_Y[7]_i_9_n_0 }));
- MUXF7 \SR_Y_reg[7]_i_40
- (.I0(\SR_Y[7]_i_54_n_0 ),
- .I1(\SR_Y[7]_i_55_n_0 ),
- .O(\SR_Y_reg[7]_i_40_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_41
- (.I0(\SR_Y[7]_i_56_n_0 ),
- .I1(\SR_Y[7]_i_57_n_0 ),
- .O(\SR_Y_reg[7]_i_41_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- CARRY4 \SR_Y_reg[7]_i_8
- (.CI(\SR_Y_reg[7]_i_10_n_0 ),
- .CO({\SR_Y_reg[7]_i_8_n_2 ,\SR_Y_reg[7]_i_8_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\<const0> ,\SR_Y[7]_i_11_n_0 }),
- .O({\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_6 ,\SR_Y_reg[7]_i_8_n_7 }),
- .S({\<const0> ,\<const1> ,\SR_Y[7]_i_12_n_0 ,\SR_Y[7]_i_13_n_0 }));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT2 #(
- .INIT(4'h1))
- \SR_readAddress[0]_i_1
- (.I0(SR_readAddress_reg__0[0]),
- .I1(I_initAddress_IBUF),
- .O(\SR_readAddress[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT3 #(
- .INIT(8'h06))
- \SR_readAddress[1]_i_1
- (.I0(SR_readAddress_reg__0[1]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(I_initAddress_IBUF),
- .O(\SR_readAddress[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'h006A))
- \SR_readAddress[2]_i_1
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(I_initAddress_IBUF),
- .O(\SR_readAddress[2]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \SR_readAddress[3]_i_1
- (.I0(I_incrAddress_IBUF),
- .I1(I_initAddress_IBUF),
- .O(\SR_readAddress[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT5 #(
- .INIT(32'h00006AAA))
- \SR_readAddress[3]_i_2
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(I_initAddress_IBUF),
- .O(\SR_readAddress[3]_i_2_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[0]_i_1_n_0 ),
- .Q(SR_readAddress_reg__0[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[1]_i_1_n_0 ),
- .Q(SR_readAddress_reg__0[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[2]_i_1_n_0 ),
- .Q(SR_readAddress_reg__0[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[3]_i_2_n_0 ),
- .Q(SR_readAddress_reg__0[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[0]),
- .Q(\SR_shiftRegister_reg[0]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[1]),
- .Q(\SR_shiftRegister_reg[0]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[2]),
- .Q(\SR_shiftRegister_reg[0]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[3]),
- .Q(\SR_shiftRegister_reg[0]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[4]),
- .Q(\SR_shiftRegister_reg[0]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[5]),
- .Q(\SR_shiftRegister_reg[0]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[6]),
- .Q(\SR_shiftRegister_reg[0]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[7]),
- .Q(\SR_shiftRegister_reg[0]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [0]),
- .Q(\SR_shiftRegister_reg[10]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [1]),
- .Q(\SR_shiftRegister_reg[10]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [2]),
- .Q(\SR_shiftRegister_reg[10]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [3]),
- .Q(\SR_shiftRegister_reg[10]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [4]),
- .Q(\SR_shiftRegister_reg[10]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [5]),
- .Q(\SR_shiftRegister_reg[10]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [6]),
- .Q(\SR_shiftRegister_reg[10]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [7]),
- .Q(\SR_shiftRegister_reg[10]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [0]),
- .Q(\SR_shiftRegister_reg[11]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [1]),
- .Q(\SR_shiftRegister_reg[11]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [2]),
- .Q(\SR_shiftRegister_reg[11]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [3]),
- .Q(\SR_shiftRegister_reg[11]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [4]),
- .Q(\SR_shiftRegister_reg[11]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [5]),
- .Q(\SR_shiftRegister_reg[11]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [6]),
- .Q(\SR_shiftRegister_reg[11]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [7]),
- .Q(\SR_shiftRegister_reg[11]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [0]),
- .Q(\SR_shiftRegister_reg[12]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [1]),
- .Q(\SR_shiftRegister_reg[12]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [2]),
- .Q(\SR_shiftRegister_reg[12]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [3]),
- .Q(\SR_shiftRegister_reg[12]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [4]),
- .Q(\SR_shiftRegister_reg[12]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [5]),
- .Q(\SR_shiftRegister_reg[12]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [6]),
- .Q(\SR_shiftRegister_reg[12]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [7]),
- .Q(\SR_shiftRegister_reg[12]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [0]),
- .Q(\SR_shiftRegister_reg[13]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [1]),
- .Q(\SR_shiftRegister_reg[13]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [2]),
- .Q(\SR_shiftRegister_reg[13]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [3]),
- .Q(\SR_shiftRegister_reg[13]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [4]),
- .Q(\SR_shiftRegister_reg[13]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [5]),
- .Q(\SR_shiftRegister_reg[13]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [6]),
- .Q(\SR_shiftRegister_reg[13]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [7]),
- .Q(\SR_shiftRegister_reg[13]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [0]),
- .Q(\SR_shiftRegister_reg[14]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [1]),
- .Q(\SR_shiftRegister_reg[14]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [2]),
- .Q(\SR_shiftRegister_reg[14]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [3]),
- .Q(\SR_shiftRegister_reg[14]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [4]),
- .Q(\SR_shiftRegister_reg[14]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [5]),
- .Q(\SR_shiftRegister_reg[14]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [6]),
- .Q(\SR_shiftRegister_reg[14]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [7]),
- .Q(\SR_shiftRegister_reg[14]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [0]),
- .Q(\SR_shiftRegister_reg[15]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [1]),
- .Q(\SR_shiftRegister_reg[15]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [2]),
- .Q(\SR_shiftRegister_reg[15]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [3]),
- .Q(\SR_shiftRegister_reg[15]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [4]),
- .Q(\SR_shiftRegister_reg[15]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [5]),
- .Q(\SR_shiftRegister_reg[15]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [6]),
- .Q(\SR_shiftRegister_reg[15]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [7]),
- .Q(\SR_shiftRegister_reg[15]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [0]),
- .Q(\SR_shiftRegister_reg[1]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [1]),
- .Q(\SR_shiftRegister_reg[1]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [2]),
- .Q(\SR_shiftRegister_reg[1]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [3]),
- .Q(\SR_shiftRegister_reg[1]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [4]),
- .Q(\SR_shiftRegister_reg[1]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [5]),
- .Q(\SR_shiftRegister_reg[1]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [6]),
- .Q(\SR_shiftRegister_reg[1]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [7]),
- .Q(\SR_shiftRegister_reg[1]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [0]),
- .Q(\SR_shiftRegister_reg[2]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [1]),
- .Q(\SR_shiftRegister_reg[2]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [2]),
- .Q(\SR_shiftRegister_reg[2]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [3]),
- .Q(\SR_shiftRegister_reg[2]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [4]),
- .Q(\SR_shiftRegister_reg[2]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [5]),
- .Q(\SR_shiftRegister_reg[2]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [6]),
- .Q(\SR_shiftRegister_reg[2]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [7]),
- .Q(\SR_shiftRegister_reg[2]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [0]),
- .Q(\SR_shiftRegister_reg[3]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [1]),
- .Q(\SR_shiftRegister_reg[3]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [2]),
- .Q(\SR_shiftRegister_reg[3]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [3]),
- .Q(\SR_shiftRegister_reg[3]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [4]),
- .Q(\SR_shiftRegister_reg[3]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [5]),
- .Q(\SR_shiftRegister_reg[3]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [6]),
- .Q(\SR_shiftRegister_reg[3]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [7]),
- .Q(\SR_shiftRegister_reg[3]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [0]),
- .Q(\SR_shiftRegister_reg[4]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [1]),
- .Q(\SR_shiftRegister_reg[4]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [2]),
- .Q(\SR_shiftRegister_reg[4]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [3]),
- .Q(\SR_shiftRegister_reg[4]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [4]),
- .Q(\SR_shiftRegister_reg[4]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [5]),
- .Q(\SR_shiftRegister_reg[4]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [6]),
- .Q(\SR_shiftRegister_reg[4]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [7]),
- .Q(\SR_shiftRegister_reg[4]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [0]),
- .Q(\SR_shiftRegister_reg[5]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [1]),
- .Q(\SR_shiftRegister_reg[5]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [2]),
- .Q(\SR_shiftRegister_reg[5]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [3]),
- .Q(\SR_shiftRegister_reg[5]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [4]),
- .Q(\SR_shiftRegister_reg[5]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [5]),
- .Q(\SR_shiftRegister_reg[5]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [6]),
- .Q(\SR_shiftRegister_reg[5]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [7]),
- .Q(\SR_shiftRegister_reg[5]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [0]),
- .Q(\SR_shiftRegister_reg[6]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [1]),
- .Q(\SR_shiftRegister_reg[6]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [2]),
- .Q(\SR_shiftRegister_reg[6]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [3]),
- .Q(\SR_shiftRegister_reg[6]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [4]),
- .Q(\SR_shiftRegister_reg[6]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [5]),
- .Q(\SR_shiftRegister_reg[6]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [6]),
- .Q(\SR_shiftRegister_reg[6]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [7]),
- .Q(\SR_shiftRegister_reg[6]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [0]),
- .Q(\SR_shiftRegister_reg[7]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [1]),
- .Q(\SR_shiftRegister_reg[7]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [2]),
- .Q(\SR_shiftRegister_reg[7]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [3]),
- .Q(\SR_shiftRegister_reg[7]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [4]),
- .Q(\SR_shiftRegister_reg[7]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [5]),
- .Q(\SR_shiftRegister_reg[7]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [6]),
- .Q(\SR_shiftRegister_reg[7]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [7]),
- .Q(\SR_shiftRegister_reg[7]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [0]),
- .Q(\SR_shiftRegister_reg[8]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [1]),
- .Q(\SR_shiftRegister_reg[8]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [2]),
- .Q(\SR_shiftRegister_reg[8]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [3]),
- .Q(\SR_shiftRegister_reg[8]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [4]),
- .Q(\SR_shiftRegister_reg[8]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [5]),
- .Q(\SR_shiftRegister_reg[8]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [6]),
- .Q(\SR_shiftRegister_reg[8]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [7]),
- .Q(\SR_shiftRegister_reg[8]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [0]),
- .Q(\SR_shiftRegister_reg[9]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [1]),
- .Q(\SR_shiftRegister_reg[9]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [2]),
- .Q(\SR_shiftRegister_reg[9]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [3]),
- .Q(\SR_shiftRegister_reg[9]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [4]),
- .Q(\SR_shiftRegister_reg[9]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [5]),
- .Q(\SR_shiftRegister_reg[9]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [6]),
- .Q(\SR_shiftRegister_reg[9]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [7]),
- .Q(\SR_shiftRegister_reg[9]__0 [7]));
- LUT2 #(
- .INIT(4'hE))
- \SR_sum[0]_i_1
- (.I0(I_loadSum_IBUF),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[0]_i_10
- (.I0(SC_MultResult[0]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[0]),
- .O(\SR_sum[0]_i_10_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \SR_sum[0]_i_13
- (.I0(\SR_sum[0]_i_27_n_0 ),
- .O(\SR_sum[0]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hFDDD777F))
- \SR_sum[0]_i_14
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_sum[0]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h724E0000))
- \SR_sum[0]_i_15
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(\SR_shiftRegister[0] [1]),
- .O(\SR_sum[0]_i_15_n_0 ));
- LUT6 #(
- .INIT(64'h02228880FDDD777F))
- \SR_sum[0]_i_16
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_sum[0]_i_27_n_0 ),
- .O(\SR_sum[0]_i_16_n_0 ));
- LUT6 #(
- .INIT(64'hCED287B3FDDD777F))
- \SR_sum[0]_i_17
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_sum[0]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'h113AAC44220AA088))
- \SR_sum[0]_i_18
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [0]),
- .O(\SR_sum[0]_i_18_n_0 ));
- LUT5 #(
- .INIT(32'h028AA280))
- \SR_sum[0]_i_19
- (.I0(\SR_shiftRegister[0] [0]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_sum[0]_i_19_n_0 ));
- LUT3 #(
- .INIT(8'h69))
- \SR_sum[0]_i_20
- (.I0(\SR_sum[0]_i_31_n_0 ),
- .I1(\SR_sum[0]_i_32_n_0 ),
- .I2(\SR_sum[0]_i_33_n_0 ),
- .O(\SR_sum[0]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'h9B4AA1E6A88AA22A))
- \SR_sum[0]_i_21
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [0]),
- .O(\SR_sum[0]_i_21_n_0 ));
- LUT5 #(
- .INIT(32'h60060000))
- \SR_sum[0]_i_22
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(\SR_shiftRegister[0] [1]),
- .O(\SR_sum[0]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'h6696969666666666))
- \SR_sum[0]_i_23
- (.I0(\SR_sum[0]_i_31_n_0 ),
- .I1(\SR_sum[0]_i_33_n_0 ),
- .I2(\SR_shiftRegister[0] [1]),
- .I3(SC_multOperand2[1]),
- .I4(\SR_shiftRegister[0] [0]),
- .I5(SC_multOperand2[2]),
- .O(\SR_sum[0]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'h96AAAA96AAAAAAAA))
- \SR_sum[0]_i_24
- (.I0(\SR_sum[0]_i_21_n_0 ),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[3]),
- .I4(SR_readAddress_reg__0[1]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_sum[0]_i_24_n_0 ));
- LUT6 #(
- .INIT(64'hF7C143DF08028020))
- \SR_sum[0]_i_25
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[2]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister[0] [0]),
- .O(\SR_sum[0]_i_25_n_0 ));
- LUT5 #(
- .INIT(32'h00828200))
- \SR_sum[0]_i_26
- (.I0(\SR_shiftRegister[0] [0]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_sum[0]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'h113AAC44220AA088))
- \SR_sum[0]_i_27
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_sum[0]_i_27_n_0 ));
- LUT3 #(
- .INIT(8'h06))
- \SR_sum[0]_i_3
- (.I0(\SR_sum_reg[0]_i_11_n_7 ),
- .I1(\SR_sum_reg[0]_i_12_n_4 ),
- .I2(I_initSum_IBUF),
- .O(\SR_sum[0]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_sum[0]_i_31
- (.I0(\SR_shiftRegister[0] [2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_sum[0]_i_31_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_sum[0]_i_32
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_sum[0]_i_32_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_sum[0]_i_33
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_sum[0]_i_33_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT4 #(
- .INIT(16'hF99F))
- \SR_sum[0]_i_34
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .O(SC_multOperand2[1]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h581A))
- \SR_sum[0]_i_35
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[3]),
- .O(SC_multOperand2[2]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_4
- (.I0(SC_MultResult[2]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_45
- (.I0(\SR_shiftRegister_reg[3]__0 [1]),
- .I1(\SR_shiftRegister_reg[2]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [1]),
- .O(\SR_sum[0]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_46
- (.I0(\SR_shiftRegister_reg[7]__0 [1]),
- .I1(\SR_shiftRegister_reg[6]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [1]),
- .O(\SR_sum[0]_i_46_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_47
- (.I0(\SR_shiftRegister_reg[11]__0 [1]),
- .I1(\SR_shiftRegister_reg[10]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [1]),
- .O(\SR_sum[0]_i_47_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_48
- (.I0(\SR_shiftRegister_reg[15]__0 [1]),
- .I1(\SR_shiftRegister_reg[14]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [1]),
- .O(\SR_sum[0]_i_48_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_49
- (.I0(\SR_shiftRegister_reg[3]__0 [2]),
- .I1(\SR_shiftRegister_reg[2]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [2]),
- .O(\SR_sum[0]_i_49_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_5
- (.I0(SC_MultResult[1]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_50
- (.I0(\SR_shiftRegister_reg[7]__0 [2]),
- .I1(\SR_shiftRegister_reg[6]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [2]),
- .O(\SR_sum[0]_i_50_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_51
- (.I0(\SR_shiftRegister_reg[11]__0 [2]),
- .I1(\SR_shiftRegister_reg[10]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [2]),
- .O(\SR_sum[0]_i_51_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_52
- (.I0(\SR_shiftRegister_reg[15]__0 [2]),
- .I1(\SR_shiftRegister_reg[14]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [2]),
- .O(\SR_sum[0]_i_52_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_53
- (.I0(\SR_shiftRegister_reg[3]__0 [0]),
- .I1(\SR_shiftRegister_reg[2]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [0]),
- .O(\SR_sum[0]_i_53_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_54
- (.I0(\SR_shiftRegister_reg[7]__0 [0]),
- .I1(\SR_shiftRegister_reg[6]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [0]),
- .O(\SR_sum[0]_i_54_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_55
- (.I0(\SR_shiftRegister_reg[11]__0 [0]),
- .I1(\SR_shiftRegister_reg[10]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [0]),
- .O(\SR_sum[0]_i_55_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_56
- (.I0(\SR_shiftRegister_reg[15]__0 [0]),
- .I1(\SR_shiftRegister_reg[14]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [0]),
- .O(\SR_sum[0]_i_56_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_57
- (.I0(\SR_shiftRegister_reg[3]__0 [3]),
- .I1(\SR_shiftRegister_reg[2]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [3]),
- .O(\SR_sum[0]_i_57_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_58
- (.I0(\SR_shiftRegister_reg[7]__0 [3]),
- .I1(\SR_shiftRegister_reg[6]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [3]),
- .O(\SR_sum[0]_i_58_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_59
- (.I0(\SR_shiftRegister_reg[11]__0 [3]),
- .I1(\SR_shiftRegister_reg[10]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [3]),
- .O(\SR_sum[0]_i_59_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_6
- (.I0(SC_MultResult[0]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_60
- (.I0(\SR_shiftRegister_reg[15]__0 [3]),
- .I1(\SR_shiftRegister_reg[14]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [3]),
- .O(\SR_sum[0]_i_60_n_0 ));
- LUT4 #(
- .INIT(16'h0906))
- \SR_sum[0]_i_7
- (.I0(\SR_sum_reg[0]_i_12_n_4 ),
- .I1(\SR_sum_reg[0]_i_11_n_7 ),
- .I2(I_initSum_IBUF),
- .I3(SR_sum_reg[3]),
- .O(\SR_sum[0]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[0]_i_8
- (.I0(SC_MultResult[2]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[2]),
- .O(\SR_sum[0]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[0]_i_9
- (.I0(SC_MultResult[1]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[1]),
- .O(\SR_sum[0]_i_9_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[12]_i_2
- (.I0(SC_MultResult[13]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[12]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[12]_i_3
- (.I0(SC_MultResult[12]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[12]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[12]_i_4
- (.I0(SC_MultResult[14]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[14]),
- .O(\SR_sum[12]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[12]_i_5
- (.I0(SC_MultResult[13]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[13]),
- .O(\SR_sum[12]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[12]_i_6
- (.I0(SC_MultResult[12]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[12]),
- .O(\SR_sum[12]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_2
- (.I0(SC_MultResult[7]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_3
- (.I0(SC_MultResult[6]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_4
- (.I0(SC_MultResult[5]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_5
- (.I0(SC_MultResult[4]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_6
- (.I0(SC_MultResult[7]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[7]),
- .O(\SR_sum[4]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_7
- (.I0(SC_MultResult[6]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[6]),
- .O(\SR_sum[4]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_8
- (.I0(SC_MultResult[5]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[5]),
- .O(\SR_sum[4]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_9
- (.I0(SC_MultResult[4]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[4]),
- .O(\SR_sum[4]_i_9_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_2
- (.I0(SC_MultResult[11]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_3
- (.I0(SC_MultResult[10]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_4
- (.I0(SC_MultResult[9]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_5
- (.I0(SC_MultResult[8]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_6
- (.I0(SC_MultResult[11]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[11]),
- .O(\SR_sum[8]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_7
- (.I0(SC_MultResult[10]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[10]),
- .O(\SR_sum[8]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_8
- (.I0(SC_MultResult[9]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[9]),
- .O(\SR_sum[8]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_9
- (.I0(SC_MultResult[8]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[8]),
- .O(\SR_sum[8]_i_9_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_7 ),
- .Q(SR_sum_reg[0]));
- CARRY4 \SR_sum_reg[0]_i_11
- (.CI(\<const0> ),
- .CO({\SR_sum_reg[0]_i_11_n_0 ,\SR_sum_reg[0]_i_11_n_1 ,\SR_sum_reg[0]_i_11_n_2 ,\SR_sum_reg[0]_i_11_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[0]_i_13_n_0 ,\SR_sum[0]_i_14_n_0 ,\SR_sum[0]_i_15_n_0 ,\<const0> }),
- .O({\SR_sum_reg[0]_i_11_n_4 ,\SR_sum_reg[0]_i_11_n_5 ,\SR_sum_reg[0]_i_11_n_6 ,\SR_sum_reg[0]_i_11_n_7 }),
- .S({\SR_sum[0]_i_16_n_0 ,\SR_sum[0]_i_17_n_0 ,\SR_sum[0]_i_18_n_0 ,\SR_sum[0]_i_19_n_0 }));
- CARRY4 \SR_sum_reg[0]_i_12
- (.CI(\<const0> ),
- .CO({\SR_sum_reg[0]_i_12_n_0 ,\SR_sum_reg[0]_i_12_n_1 ,\SR_sum_reg[0]_i_12_n_2 ,\SR_sum_reg[0]_i_12_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[0]_i_20_n_0 ,\SR_sum[0]_i_21_n_0 ,\SR_sum[0]_i_22_n_0 ,\<const0> }),
- .O({\SR_sum_reg[0]_i_12_n_4 ,SC_MultResult[2:0]}),
- .S({\SR_sum[0]_i_23_n_0 ,\SR_sum[0]_i_24_n_0 ,\SR_sum[0]_i_25_n_0 ,\SR_sum[0]_i_26_n_0 }));
- CARRY4 \SR_sum_reg[0]_i_2
- (.CI(\<const0> ),
- .CO({\SR_sum_reg[0]_i_2_n_0 ,\SR_sum_reg[0]_i_2_n_1 ,\SR_sum_reg[0]_i_2_n_2 ,\SR_sum_reg[0]_i_2_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[0]_i_3_n_0 ,\SR_sum[0]_i_4_n_0 ,\SR_sum[0]_i_5_n_0 ,\SR_sum[0]_i_6_n_0 }),
- .O({\SR_sum_reg[0]_i_2_n_4 ,\SR_sum_reg[0]_i_2_n_5 ,\SR_sum_reg[0]_i_2_n_6 ,\SR_sum_reg[0]_i_2_n_7 }),
- .S({\SR_sum[0]_i_7_n_0 ,\SR_sum[0]_i_8_n_0 ,\SR_sum[0]_i_9_n_0 ,\SR_sum[0]_i_10_n_0 }));
- MUXF8 \SR_sum_reg[0]_i_28
- (.I0(\SR_sum_reg[0]_i_37_n_0 ),
- .I1(\SR_sum_reg[0]_i_38_n_0 ),
- .O(\SR_shiftRegister[0] [1]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_sum_reg[0]_i_29
- (.I0(\SR_sum_reg[0]_i_39_n_0 ),
- .I1(\SR_sum_reg[0]_i_40_n_0 ),
- .O(\SR_shiftRegister[0] [2]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_sum_reg[0]_i_30
- (.I0(\SR_sum_reg[0]_i_41_n_0 ),
- .I1(\SR_sum_reg[0]_i_42_n_0 ),
- .O(\SR_shiftRegister[0] [0]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_sum_reg[0]_i_36
- (.I0(\SR_sum_reg[0]_i_43_n_0 ),
- .I1(\SR_sum_reg[0]_i_44_n_0 ),
- .O(\SR_shiftRegister[0] [3]),
- .S(SR_readAddress_reg__0[3]));
- MUXF7 \SR_sum_reg[0]_i_37
- (.I0(\SR_sum[0]_i_45_n_0 ),
- .I1(\SR_sum[0]_i_46_n_0 ),
- .O(\SR_sum_reg[0]_i_37_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_38
- (.I0(\SR_sum[0]_i_47_n_0 ),
- .I1(\SR_sum[0]_i_48_n_0 ),
- .O(\SR_sum_reg[0]_i_38_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_39
- (.I0(\SR_sum[0]_i_49_n_0 ),
- .I1(\SR_sum[0]_i_50_n_0 ),
- .O(\SR_sum_reg[0]_i_39_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_40
- (.I0(\SR_sum[0]_i_51_n_0 ),
- .I1(\SR_sum[0]_i_52_n_0 ),
- .O(\SR_sum_reg[0]_i_40_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_41
- (.I0(\SR_sum[0]_i_53_n_0 ),
- .I1(\SR_sum[0]_i_54_n_0 ),
- .O(\SR_sum_reg[0]_i_41_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_42
- (.I0(\SR_sum[0]_i_55_n_0 ),
- .I1(\SR_sum[0]_i_56_n_0 ),
- .O(\SR_sum_reg[0]_i_42_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_43
- (.I0(\SR_sum[0]_i_57_n_0 ),
- .I1(\SR_sum[0]_i_58_n_0 ),
- .O(\SR_sum_reg[0]_i_43_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_44
- (.I0(\SR_sum[0]_i_59_n_0 ),
- .I1(\SR_sum[0]_i_60_n_0 ),
- .O(\SR_sum_reg[0]_i_44_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[10]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_5 ),
- .Q(SR_sum_reg[10]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[11]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_4 ),
- .Q(SR_sum_reg[11]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[12]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[12]_i_1_n_7 ),
- .Q(SR_sum_reg[12]));
- CARRY4 \SR_sum_reg[12]_i_1
- (.CI(\SR_sum_reg[8]_i_1_n_0 ),
- .CO({\SR_sum_reg[12]_i_1_n_2 ,\SR_sum_reg[12]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\SR_sum[12]_i_2_n_0 ,\SR_sum[12]_i_3_n_0 }),
- .O({\SR_sum_reg[12]_i_1_n_5 ,\SR_sum_reg[12]_i_1_n_6 ,\SR_sum_reg[12]_i_1_n_7 }),
- .S({\<const0> ,\SR_sum[12]_i_4_n_0 ,\SR_sum[12]_i_5_n_0 ,\SR_sum[12]_i_6_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[13]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[12]_i_1_n_6 ),
- .Q(SR_sum_reg[13]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[14]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[12]_i_1_n_5 ),
- .Q(SR_sum_reg[14]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_6 ),
- .Q(SR_sum_reg[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_5 ),
- .Q(SR_sum_reg[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_4 ),
- .Q(SR_sum_reg[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[4]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_7 ),
- .Q(SR_sum_reg[4]));
- CARRY4 \SR_sum_reg[4]_i_1
- (.CI(\SR_sum_reg[0]_i_2_n_0 ),
- .CO({\SR_sum_reg[4]_i_1_n_0 ,\SR_sum_reg[4]_i_1_n_1 ,\SR_sum_reg[4]_i_1_n_2 ,\SR_sum_reg[4]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[4]_i_2_n_0 ,\SR_sum[4]_i_3_n_0 ,\SR_sum[4]_i_4_n_0 ,\SR_sum[4]_i_5_n_0 }),
- .O({\SR_sum_reg[4]_i_1_n_4 ,\SR_sum_reg[4]_i_1_n_5 ,\SR_sum_reg[4]_i_1_n_6 ,\SR_sum_reg[4]_i_1_n_7 }),
- .S({\SR_sum[4]_i_6_n_0 ,\SR_sum[4]_i_7_n_0 ,\SR_sum[4]_i_8_n_0 ,\SR_sum[4]_i_9_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[5]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_6 ),
- .Q(SR_sum_reg[5]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[6]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_5 ),
- .Q(SR_sum_reg[6]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[7]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_4 ),
- .Q(SR_sum_reg[7]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[8]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_7 ),
- .Q(SR_sum_reg[8]));
- CARRY4 \SR_sum_reg[8]_i_1
- (.CI(\SR_sum_reg[4]_i_1_n_0 ),
- .CO({\SR_sum_reg[8]_i_1_n_0 ,\SR_sum_reg[8]_i_1_n_1 ,\SR_sum_reg[8]_i_1_n_2 ,\SR_sum_reg[8]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[8]_i_2_n_0 ,\SR_sum[8]_i_3_n_0 ,\SR_sum[8]_i_4_n_0 ,\SR_sum[8]_i_5_n_0 }),
- .O({\SR_sum_reg[8]_i_1_n_4 ,\SR_sum_reg[8]_i_1_n_5 ,\SR_sum_reg[8]_i_1_n_6 ,\SR_sum_reg[8]_i_1_n_7 }),
- .S({\SR_sum[8]_i_6_n_0 ,\SR_sum[8]_i_7_n_0 ,\SR_sum[8]_i_8_n_0 ,\SR_sum[8]_i_9_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[9]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_6 ),
- .Q(SR_sum_reg[9]));
- VCC VCC
- (.P(\<const1> ));
-endmodule
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index b33e962b4631a3043f2383bdd97b591c60d1f52c..8704de1722845fcb090a984556b0774e006d5ce1 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -10,7 +10,7 @@
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--- Description: 8 bit FIR
+-- Description: 16-bit FIR
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
@@ -19,6 +19,11 @@
-- 2018-04-11 1.0 jnbazin Created
-- 2018-04-18 1.1 marzel Modified to add more test inputs
-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
+-- 2025-04-09 1.2 marzel Renamed some signals and port names to match
+-- the description of lab activity
+-- Modified the sample width to 16 bits
+-- Changed the filter coefficients to have abetter
+-- low-pass filter
-------------------------------------------------------------------------------
library ieee;
@@ -33,17 +38,17 @@ architecture archi_tb_firUnit of tb_firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSample : in std_logic_vector(15 downto 0);
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0);
+ O_filteredSample : out std_logic_vector(15 downto 0);
O_filteredSampleValid : out std_logic);
end component firUnit;
signal SC_clock : std_logic := '0';
signal SC_reset : std_logic;
- signal SC_inputSample : std_logic_vector(7 downto 0);
+ signal SC_inputSample : std_logic_vector(15 downto 0);
signal SC_inputSampleValid : std_logic := '0';
- signal SC_filteredSample : std_logic_vector(7 downto 0);
+ signal SC_filteredSample : std_logic_vector(15 downto 0);
signal SC_filteredSampleValid : std_logic;
begin
@@ -55,24 +60,25 @@ begin
SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
-- Null signal followed by a Dirac and then an arbitrary sequence
- SC_inputSample <= "00000000",
- "01111111" after 401 ns,
- "00000000" after 601 ns,
- "00100100" after 4201 ns,
- "01100100" after 4401 ns,
- "10100010" after 4601 ns,
- "11011011" after 4801 ns,
- "00001011" after 5001 ns,
- "10000000" after 5201 ns,
- "01111111" after 5401 ns,
- "10111010" after 5601 ns;
+ SC_inputSample <= "0000000000000000",
+ "0111111111111111" after 401 ns,
+ "0000000000000000" after 601 ns,
+ "0000000000100100" after 4201 ns,
+ "0000000001100100" after 4401 ns,
+ "1111111110100010" after 4601 ns,
+ "1111111111011011" after 4801 ns,
+ "0000000000001011" after 5001 ns,
+ "1111111110000000" after 5201 ns,
+ "0000000001111111" after 5401 ns,
+ "1111111110111010" after 5601 ns;
- -- the filter output on 8 bits is a sequence of signed numbers (with the assumption
+ -- the filter output on 16 bits is a sequence of signed numbers (with the assumption
-- of rounding the output, so the accuracy can be slightly different depending
-- on your final stage):
- -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
- -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
+ -- 317,476,925,1589,2354,3087,3661,3975,3975,3661,3087,2354,1589,925,476,317,
+ -- 0,0,0,0,1,2,3,4,4,5,2,-1,-5,-10,-16,-23,-30,-37,-43,-49,-56,-61,-64,-68,
+ -- -68, -70, ...
firUnit_1 : entity work.firUnit