diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index cd056f619d4a6c4caddd9df5b41f43ed435892f3..e177340b286c9b23b3b77a3b93ebdfbd9dba66bd 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -8,10 +8,10 @@
## Questions
### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
-
+### Deux processus sont utilisés, un séquentiel et un combinatoire, on les différencie grâce à leurs entrées : celles du processus séquentiel comprend une horloge et un reset.
### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
-
+### La séquence renvoyé par la simulation est bien celle attendue, ce n'est pas une condition suffisante pour être sûr que la description VHDL est adapté mais donne tout de même pseudo validation.
### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index bd839a9b01be6c20eb7b6840fcbab9fd73e2336d..17b44c98de64bc01cdf8beb8959d721ef1de0ff3 100644
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diff --git a/docs/img/FSM.png b/docs/img/FSM.png
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..9c67a3678cec86d0e8f8b4638737bc6746715923 100644
Binary files a/docs/img/FSM.png and b/docs/img/FSM.png differ
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 21da15f3e1bdfbfa00939c8508c01ee8a1caca2f..9079cd1782e9122d5ee10d697542e61851b43660 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -54,37 +54,68 @@ begin
-- Process to describe the state register
-- Current state is provide at the output of the register
-- and is updated with the next state at each rising edge of clock
- process (_BLANK_) is
+ process (I_clock,I_reset) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
- SR_currentState <= _BLANK_
+ SR_currentState <= WAIT_SAMPLE;
elsif rising_edge(I_clock) then -- rising clock edge
- _BLANK_
+ SR_currentState <= SR_nextState;
end if;
end process;
-- Combinatorial process computing the next state which depends on
-- the current state and on the inputs
- process (_BLANK_) is
+ process (SR_currentState,I_processingDone, I_inputSampleValid ) is
begin
case SR_currentState is
when WAIT_SAMPLE =>
- _BLANK_
-
- when others => null;
+ if I_inputSampleValid = '1' then
+ SR_nextState <= STORE;
+ else
+ SR_nextState <= WAIT_SAMPLE;
+ end if;
+
+
+ when STORE =>
+ SR_nextState <= PROCESSING_LOOP;
+
+
+ when PROCESSING_LOOP =>
+ if I_processingDone = '1' then
+ SR_nextState <= OUTPUT;
+ else
+ SR_nextState <= PROCESSING_LOOP;
+ end if;
+
+
+ when OUTPUT =>
+ SR_nextState <= WAIT_END_SAMPLE;
+
+
+ when WAIT_END_SAMPLE =>
+ if I_inputSampleValid = '0' then
+ SR_nextState <= WAIT_SAMPLE;
+ else
+ SR_nextState <= WAIT_END_SAMPLE;
+ end if;
+
+
+ when others =>
+ SR_nextState <= WAIT_SAMPLE;
+
end case;
end process;
-- Rules to compute the outputs depending on the current state
-- (and on the inputs, if you want a Mealy machine).
- O_loadShift <= '1' when _BLANK_ else '0';
- O_initAddress <= '1' when _BLANK_ else '0';
- O_incrAddress <= '1' when _BLANK_ else '0';
- O_initSum <= '1' when _BLANK_ else '0';
- O_loadSum <= '1' when _BLANK_ else '0';
- O_loadOutput <= '1' when _BLANK_ else '0';
- O_FilteredSampleValid <= '1' when _BLANK_ else '0';
+ O_loadShift <= '1' when SR_currentState = STORE else '0';
+ O_initAddress <= '1' when SR_currentState = STORE else '0';
+ O_incrAddress <= '1' when SR_currentState = PROCESSING_LOOP else '0';
+ O_initSum <= '1' when SR_currentState = STORE else '0';
+ O_loadSum <= '1' when SR_currentState = PROCESSING_LOOP else '0';
+ O_loadOutput <= '1' when SR_currentState = OUTPUT else '0';
+ O_FilteredSampleValid <= '1' when SR_currentState = WAIT_END_SAMPLE else '0';
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index fe12a2e40d899e53218df9bccbf9aab36f8170bd..2e89ab5958e86891eeb3ac3585ee13b907b997c1 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -114,7 +114,7 @@ begin
);
-- Process to describe the shift register storing the input samples
- shift : process (_BLANK_) is
+ shift : process (I_reset, I_clock, ) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));