diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index fe12a2e40d899e53218df9bccbf9aab36f8170bd..4ea1b9493be25ad89fed58b7f7bcc65b78193b77 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -114,37 +114,44 @@ begin
                         );
     
     -- Process to describe the shift register storing the input samples
-    shift : process (_BLANK_) is
+    shift : process (I_clock,I_reset) is
     begin  -- process shift
         if I_reset = '1' then           -- asynchronous reset (active high)
             SR_shiftRegister <= (others => (others => '0'));
-        elsif _BLANK_
-
+        elsif rising_edge(I_clock) then
+            if I_loadShift = '1' then
+                for i in 15 downto 1 loop
+                    SR_shiftRegister(i) <= SR_shiftRegister(i-1);
+                end loop;
+                SR_shiftRegister(0) <= signed(I_inputSample);
+            end if;
         end if;
     end process shift;
 
-    -- Process to describe the counter providing the selection adresses
-    -- of the multiplexers
-    incr_address : process (_BLANK_) is
+    -- Process for incrementing and initializing the read address
+    incr_address : process (I_clock, I_reset) is
     begin
-        if I_reset = '1' then               -- asynchronous reset (active high)
+        if I_reset = '1' then
             SR_readAddress <= 0;
-        elsif _BLANK_
-
+        elsif rising_edge(I_clock) then
+            if I_initAddress = '1' then
+                SR_readAddress <= 0;
+            elsif I_incrAddress = '1' then
+                SR_readAddress <= SR_readAddress + 1;
+            end if;
         end if;
     end process incr_address;
 
     -- Signal detecting that the next cycle will be the one
     -- providing the last product used to compute the convolution
-    O_processingDone <= '1' when _BLANK_;
-
-    -- Signals connected with multiplexers (SIMPLY inferred with table indices)
-    SC_multOperand1 <= _BLANK_;             -- 16 bits
-    SC_multOperand2 <= _BLANK_;             -- 16 bits
+    O_processingDone <= '1' when SR_readAddress = 15 else '0';
 
-    -- Multiplication of the operands
-    SC_MultResult   <= _BLANK_;             -- 32 bits
+   -- Multiplication operands
+    SC_multOperand1 <= SR_shiftRegister(SR_readAddress);
+    SC_multOperand2 <= SR_coefRegister(SR_readAddress);
 
+    -- Multiplication
+    SC_MultResult   <= resize(SC_multOperand1, 32) * resize(SC_multOperand2, 32);
     -- Sum of the multiplication result and the accumulated value
     SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum;