From 71e06d5bb08ebed1915088f06954e95d40c23afe Mon Sep 17 00:00:00 2001
From: Emilien WOLFF <e24wolff@fl-tp-br-512.imta.fr>
Date: Mon, 12 May 2025 15:59:12 +0200
Subject: [PATCH] emilien2
---
src/hdl/operativeUnit.vhd | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 4eb6316..8aad07a 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -45,7 +45,7 @@ entity operativeUnit is
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register;
- I_loadY : in std_logic; -- Control signal to load Y register
+ I_loadOutput : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done
O_filteredSample : out std_logic_vector(15 downto 0) -- filtered sample
);
@@ -143,7 +143,7 @@ begin
-- Signal detecting that the next cycle will be the one
-- providing the last product used to compute the convolution
- O_processingDone <= '1' when SR_readAddress = 15 else '0';
+ O_processingDone <= '1' when SR_readAddress = 14 else '0';
-- Signals connected with multiplexers (SIMPLY inferred with table indices)
SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 16 bits
@@ -177,7 +177,7 @@ begin
if I_reset='1' then
SR_filteredSample <= (others => '0');
elsif rising_edge (I_clock) then
- if I_loadY = '1' then
+ if I_loadOutput = '1' then
if SC_addResult(14) = '1' then
SR_filteredSample <= SC_addResult(30 downto 15) + 1;
else
--
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