diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd index 21da15f3e1bdfbfa00939c8508c01ee8a1caca2f..e040e8bf3b0ffbff688afb8c289246cbbc6cf373 100644 --- a/src/hdl/controlUnit.vhd +++ b/src/hdl/controlUnit.vhd @@ -54,39 +54,57 @@ begin -- Process to describe the state register -- Current state is provide at the output of the register -- and is updated with the next state at each rising edge of clock - process (_BLANK_) is + process (I_clock,I_reset) is begin if I_reset = '1' then -- asynchronous reset (active high) - SR_currentState <= _BLANK_ + SR_currentState <= WAIT_SAMPLE ; elsif rising_edge(I_clock) then -- rising clock edge - _BLANK_ + SR_currentState <= SR_nextState ;-- état futur dans été présent end if; end process; -- Combinatorial process computing the next state which depends on -- the current state and on the inputs - process (_BLANK_) is + process (SR_currentState,I_processingDone,I_inputSampleValid) is begin case SR_currentState is when WAIT_SAMPLE => - _BLANK_ - - when others => null; + if I_inputSampleValid = '1' then + SR_nextState <= STORE; + + else + SR_nextState <= WAIT_SAMPLE; + end if; + + when STORE => + SR_nextState <= PROCESSING_LOOP; + + when OUTPUT => + SR_nextState <= WAIT_END_SAMPLE; + + when WAIT_END_SAMPLE => + if I_inputSampleValid = '0' then + SR_nextState <= WAIT_SAMPLE; + else + SR_nextState <= WAIT_END_SAMPLE; + end if; + + when others => + SR_nextState <= WAIT_SAMPLE; + end case; end process; -- Rules to compute the outputs depending on the current state -- (and on the inputs, if you want a Mealy machine). - O_loadShift <= '1' when _BLANK_ else '0'; - O_initAddress <= '1' when _BLANK_ else '0'; - O_incrAddress <= '1' when _BLANK_ else '0'; - O_initSum <= '1' when _BLANK_ else '0'; - O_loadSum <= '1' when _BLANK_ else '0'; - O_loadOutput <= '1' when _BLANK_ else '0'; - O_FilteredSampleValid <= '1' when _BLANK_ else '0'; - - + O_loadShift <= '1' when SR_currentState = STORE else '0'; + O_initAddress <= '1' when SR_currentState = STORE else '0'; + O_incrAddress <= '1' when SR_currentState = PROCESSING_LOOP else '0'; + O_initSum <= '1' when SR_currentState = STORE else '0'; + O_loadSum <= '1' when SR_currentState = PROCESSING_LOOP else '0'; + O_loadOutput <= '1' when SR_currentState = OUTPUT else '0'; + O_FilteredSampleValid <= '1' when SR_currentState = OUTPUT else '0';