From 70c7ddd95a11b74b5a7bcf70c456fdfd95332f3e Mon Sep 17 00:00:00 2001
From: Kani FOMBA <k24fomba@fl-tp-br-518.imta.fr>
Date: Mon, 5 May 2025 10:49:58 +0200
Subject: [PATCH] ajout de wave gen
---
docs/module E.png | Bin 0 -> 24044 bytes
docs/moduleD.png | Bin 0 -> 24089 bytes
docs/wave_generator_completed.drawio | 100 ++
proj/tb_module_C_behav.wcfg | 61 ++
proj/tb_module_D_behav.wcfg | 61 ++
proj/tb_module_E_behav.wcfg | 61 ++
proj/tb_module_G_behav.wcfg | 32 +
src/hdl/wave_generator.vhd | 60 +-
vivado.jou | 187 ++++
vivado.log | 1265 ++++++++++++++++++++++++++
10 files changed, 1797 insertions(+), 30 deletions(-)
create mode 100644 docs/module E.png
create mode 100644 docs/moduleD.png
create mode 100644 docs/wave_generator_completed.drawio
create mode 100644 proj/tb_module_C_behav.wcfg
create mode 100644 proj/tb_module_D_behav.wcfg
create mode 100644 proj/tb_module_E_behav.wcfg
create mode 100644 proj/tb_module_G_behav.wcfg
create mode 100644 vivado.jou
create mode 100644 vivado.log
diff --git a/docs/module E.png b/docs/module E.png
new file mode 100644
index 0000000000000000000000000000000000000000..8e1659d20b3f21bcb66dd7f037f1fbae5d3c90f6
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diff --git a/proj/tb_module_C_behav.wcfg b/proj/tb_module_C_behav.wcfg
new file mode 100644
index 0000000..a2e22fd
--- /dev/null
+++ b/proj/tb_module_C_behav.wcfg
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+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
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+ <top_modules>
+ <top_module name="tb_module_C" />
+ <top_module name="wave_package" />
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+ <obj_property name="ObjectShortName">SR_clk</obj_property>
+ </wvobject>
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+ </wvobject>
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+ </wvobject>
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+ <obj_property name="ObjectShortName">SC_sine_out[15:0]</obj_property>
+ <obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
+ <obj_property name="CellHeight">100</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_C/SR_addrNatural">
+ <obj_property name="ElementShortName">SR_addrNatural</obj_property>
+ <obj_property name="ObjectShortName">SR_addrNatural</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_C/C_N">
+ <obj_property name="ElementShortName">C_N</obj_property>
+ <obj_property name="ObjectShortName">C_N</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_C/C_f0">
+ <obj_property name="ElementShortName">C_f0</obj_property>
+ <obj_property name="ObjectShortName">C_f0</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_C/C_fs">
+ <obj_property name="ElementShortName">C_fs</obj_property>
+ <obj_property name="ObjectShortName">C_fs</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_C/C_clk_period">
+ <obj_property name="ElementShortName">C_clk_period</obj_property>
+ <obj_property name="ObjectShortName">C_clk_period</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/proj/tb_module_D_behav.wcfg b/proj/tb_module_D_behav.wcfg
new file mode 100644
index 0000000..88d33b1
--- /dev/null
+++ b/proj/tb_module_D_behav.wcfg
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="tb_module_D_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="tb_module_D" />
+ <top_module name="wave_package" />
+ </top_modules>
+ </db_ref>
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+ </zoom_setting>
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+ <NameColumnWidth column_width="276"></NameColumnWidth>
+ <ValueColumnWidth column_width="120"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="9" />
+ <wvobject type="logic" fp_name="/tb_module_D/SR_clk">
+ <obj_property name="ElementShortName">SR_clk</obj_property>
+ <obj_property name="ObjectShortName">SR_clk</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_module_D/SR_rst">
+ <obj_property name="ElementShortName">SR_rst</obj_property>
+ <obj_property name="ObjectShortName">SR_rst</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_module_D/SR_addr">
+ <obj_property name="ElementShortName">SR_addr[4:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_addr[4:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_module_D/SC_triangle_out">
+ <obj_property name="ElementShortName">SC_triangle_out[15:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_triangle_out[15:0]</obj_property>
+ <obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
+ <obj_property name="CellHeight">100</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_D/SR_addrNatural">
+ <obj_property name="ElementShortName">SR_addrNatural</obj_property>
+ <obj_property name="ObjectShortName">SR_addrNatural</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_D/C_clk_period">
+ <obj_property name="ElementShortName">C_clk_period</obj_property>
+ <obj_property name="ObjectShortName">C_clk_period</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_D/C_N">
+ <obj_property name="ElementShortName">C_N</obj_property>
+ <obj_property name="ObjectShortName">C_N</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_D/C_f0">
+ <obj_property name="ElementShortName">C_f0</obj_property>
+ <obj_property name="ObjectShortName">C_f0</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_D/C_fs">
+ <obj_property name="ElementShortName">C_fs</obj_property>
+ <obj_property name="ObjectShortName">C_fs</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/proj/tb_module_E_behav.wcfg b/proj/tb_module_E_behav.wcfg
new file mode 100644
index 0000000..9d79bb6
--- /dev/null
+++ b/proj/tb_module_E_behav.wcfg
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="tb_module_E_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="tb_module_E" />
+ <top_module name="wave_package" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+ <ZoomEndTime time="563.001 ns"></ZoomEndTime>
+ <Cursor1Time time="550.000 ns"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="276"></NameColumnWidth>
+ <ValueColumnWidth column_width="120"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="9" />
+ <wvobject type="logic" fp_name="/tb_module_E/SR_clk">
+ <obj_property name="ElementShortName">SR_clk</obj_property>
+ <obj_property name="ObjectShortName">SR_clk</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_module_E/SR_rst">
+ <obj_property name="ElementShortName">SR_rst</obj_property>
+ <obj_property name="ObjectShortName">SR_rst</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_module_E/SR_addr">
+ <obj_property name="ElementShortName">SR_addr[5:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_addr[5:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_module_E/SC_saw_tooth_out">
+ <obj_property name="ElementShortName">SC_saw_tooth_out[15:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_saw_tooth_out[15:0]</obj_property>
+ <obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
+ <obj_property name="CellHeight">100</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_E/SR_addrNatural">
+ <obj_property name="ElementShortName">SR_addrNatural</obj_property>
+ <obj_property name="ObjectShortName">SR_addrNatural</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_E/C_clk_period">
+ <obj_property name="ElementShortName">C_clk_period</obj_property>
+ <obj_property name="ObjectShortName">C_clk_period</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_E/C_N">
+ <obj_property name="ElementShortName">C_N</obj_property>
+ <obj_property name="ObjectShortName">C_N</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_E/C_f0">
+ <obj_property name="ElementShortName">C_f0</obj_property>
+ <obj_property name="ObjectShortName">C_f0</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_module_E/C_fs">
+ <obj_property name="ElementShortName">C_fs</obj_property>
+ <obj_property name="ObjectShortName">C_fs</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/proj/tb_module_G_behav.wcfg b/proj/tb_module_G_behav.wcfg
new file mode 100644
index 0000000..dd477ff
--- /dev/null
+++ b/proj/tb_module_G_behav.wcfg
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="tb_module_G_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="tb_module_G" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+ <ZoomEndTime time="112.601 ns"></ZoomEndTime>
+ <Cursor1Time time="72.200 ns"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="276"></NameColumnWidth>
+ <ValueColumnWidth column_width="120"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="2" />
+ <wvobject type="array" fp_name="/tb_module_G/SR_din">
+ <obj_property name="ElementShortName">SR_din[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_din[7:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_module_G/SC_dout">
+ <obj_property name="ElementShortName">SC_dout[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_dout[7:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/src/hdl/wave_generator.vhd b/src/hdl/wave_generator.vhd
index 310c78f..16250f9 100644
--- a/src/hdl/wave_generator.vhd
+++ b/src/hdl/wave_generator.vhd
@@ -64,12 +64,12 @@ begin
G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
)
port map (
- I_clk => ,
- I_rst => ,
- I_u_d => ,
- O_val => ,
- O_last => ,
- O_middle =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_u_d => S_u_d,
+ O_val => S_addr,
+ O_last => S_last,
+ O_middle => S_middle
);
-- Module C
@@ -94,10 +94,10 @@ begin
G_fs => G_fs
)
port map (
- I_clk => ,
- I_rst => ,
- I_addr => ,
- O_triangle =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_addr => S_addr(C_addr_half_w-1 downto 0),
+ O_triangle => S_triangle_out_lut
);
-- Module E
@@ -108,10 +108,10 @@ begin
G_fs => G_fs
)
port map (
- I_clk => ,
- I_rst => ,
- I_addr => ,
- O_saw_tooth =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_addr => S_addr,
+ O_saw_tooth => S_saw_tooth_out_lut
);
S_square <= ((G_N-1) => '0', others => '1');
@@ -119,12 +119,12 @@ begin
-- Module F
F_inst : entity work.module_F
port map (
- I_sel => ,
- I_din0 => ,
- I_din1 => ,
- I_din2 => ,
- I_din3 => ,
- O_dout =>
+ I_sel => I_wave_sel,
+ I_din0 => S_sine_out_lut,
+ I_din1 => S_square,
+ I_din2 => S_saw_tooth_out_lut,
+ I_din3 => S_triangle_out_lut,
+ O_dout => S_wave_sample
);
-- Module G
@@ -133,17 +133,17 @@ begin
G_N => G_N
)
port map (
- I_din => ,
- O_dout =>
+ I_din => S_wave_sample,
+ O_dout => S_opposite_wave_sample
);
-- Module H
H_inst : entity work.module_H
port map (
- I_sel => ,
- I_din0 => ,
- I_din1 => ,
- O_dout =>
+ I_sel => S_sign_sel,
+ I_din0 => S_wave_sample,
+ I_din1 => S_opposite_wave_sample,
+ O_dout =>S_wave_value
);
-- Module I
@@ -152,10 +152,10 @@ begin
G_N => G_N
)
port map (
- I_clk => ,
- I_rst => ,
- I_din => ,
- O_dout =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_din => S_wave_value,
+ O_dout =>O_wav
);
end arch;
diff --git a/vivado.jou b/vivado.jou
new file mode 100644
index 0000000..20d0fe9
--- /dev/null
+++ b/vivado.jou
@@ -0,0 +1,187 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 5 08:23:34 2025
+# Process ID: 5153
+# Current directory: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba
+# Command line: vivado
+# Log file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/vivado.log
+# Journal file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/vivado.jou
+# Running On :fl-tp-br-518
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4194.132 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :18954 MB
+#-----------------------------------------------------------
+start_gui
+cd tp-synthe-etudiant-k24fomba/proj
+cd
+dir
+cd ~/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj
+source ./create_project.tcl
+update_compile_order -fileset sources_1
+launch_simulation
+source tb_module_B.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_C [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_C.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_D [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_D.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_C [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+current_sim simulation_2
+close_sim
+launch_simulation
+source tb_module_C.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_B [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+current_sim simulation_1
+close_sim
+launch_simulation
+source tb_module_B.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_E.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_D [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+current_sim simulation_3
+close_sim
+launch_simulation
+source tb_module_D.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+current_sim simulation_6
+close_sim
+launch_simulation
+source tb_module_E.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_F [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_F.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_H [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_H.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_G [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_G.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_I [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_I.tcl
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+open_run synth_1 -name synth_1
+open_run synth_1 -name synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 12
+wait_on_run impl_1
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+current_hw_device [get_hw_devices xc7a200t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+close_sim
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg
+set_property xsim.view /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg [get_filesets sim_1]
+current_sim simulation_11
+close_sim
+current_sim simulation_10
+close_sim
+current_sim simulation_9
+close_sim
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg
+set_property xsim.view {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg} [get_filesets sim_1]
+current_sim simulation_8
+close_sim
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg
+set_property xsim.view {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg} [get_filesets sim_1]
+current_sim simulation_7
+close_sim
+current_sim simulation_5
+close_sim
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_C_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_C_behav.wcfg
+set_property xsim.view {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_C_behav.wcfg} [get_filesets sim_1]
+close_sim
diff --git a/vivado.log b/vivado.log
new file mode 100644
index 0000000..47bfff1
--- /dev/null
+++ b/vivado.log
@@ -0,0 +1,1265 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 5 08:23:34 2025
+# Process ID: 5153
+# Current directory: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba
+# Command line: vivado
+# Log file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/vivado.log
+# Journal file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/vivado.jou
+# Running On :fl-tp-br-518
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4194.132 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :18954 MB
+#-----------------------------------------------------------
+start_gui
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+cd tp-synthe-etudiant-k24fomba/proj
+couldn't change working directory to "tp-synthe-etudiant-k24fomba/proj": no such file or directory
+cd
+dir
+WARNING: [Common 17-259] Unknown Tcl command 'dir' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
+Bureau Images Musique Public Vidéos
+Documents Modèles path Téléchargements
+cd ~/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj
+source ./create_project.tcl
+# if {[info exists ::create_path]} {
+# set dest_dir $::create_path
+# } else {
+# set dest_dir [pwd]
+# }
+# puts "INFO: Creating new project in $dest_dir"
+INFO: Creating new project in /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj
+# set proj_name "Synthe"
+# set origin_dir ".."
+# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+# set src_dir $origin_dir/src
+# set repo_dir $origin_dir/repo
+# set part_num "xc7a200tsbg484-1"
+# create_project $proj_name $dest_dir
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+create_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 8169.461 ; gain = 227.711 ; free physical = 9463 ; free virtual = 16887
+# set proj_dir [get_property directory [current_project]]
+# set obj [get_projects $proj_name]
+# set_property "default_lib" "xil_defaultlib" $obj
+# set_property "part" "$part_num" $obj
+# set_property "simulator_language" "Mixed" $obj
+# set_property "target_language" "VHDL" $obj
+# if {[string equal [get_filesets -quiet sources_1] ""]} {
+# create_fileset -srcset sources_1
+# }
+# if {[string equal [get_filesets -quiet constrs_1] ""]} {
+# create_fileset -constrset constrs_1
+# }
+# set obj [get_filesets sources_1]
+# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
+# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
+# add_files -fileset constrs_1 -quiet $src_dir/constraints
+# add_files -quiet $src_dir/hdl
+# set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
+CRITICAL WARNING: [filemgmt 20-1702] Unable to set property on the file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+File is managed as part of sub-design (IP, Block Design, DSP Design, etc.) file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci
+CRITICAL WARNING: [filemgmt 20-1702] Unable to set property on the file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+File is managed as part of sub-design (IP, Block Design, DSP Design, etc.) file: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_wave_generator.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_ADSR_module.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_B.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_C.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_D.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_E.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_F.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_G.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_H.vhd]
+# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_I.vhd]
+# set_property used_in_simulation false [get_files $src_dir/hdl/audioProc.v]
+# if {[string equal [get_runs -quiet synth_1] ""]} {
+# create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
+# } else {
+# set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
+# set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
+# }
+# set obj [get_runs synth_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.synth_design.args.fanout_limit" "400" $obj
+# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
+# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
+# set_property "steps.synth_design.args.resource_sharing" "off" $obj
+# set_property "steps.synth_design.args.no_lc" "1" $obj
+# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
+# current_run -synthesis [get_runs synth_1]
+# if {[string equal [get_runs -quiet impl_1] ""]} {
+# create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+# } else {
+# set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+# set_property flow "Vivado Implementation 2014" [get_runs impl_1]
+# }
+# set obj [get_runs impl_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.write_bitstream.args.bin_file" "1" $obj
+# current_run -implementation [get_runs impl_1]
+# set_property top tb_module_B [get_filesets sim_1]
+# set_property top_lib xil_defaultlib [get_filesets sim_1]
+# update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_B'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_B' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_B_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_B'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_B.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_B'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+execute_script: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 8332.176 ; gain = 0.000 ; free physical = 9250 ; free virtual = 16694
+INFO: [USF-XSim-69] 'compile' step finished in '6' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_B_behav xil_defaultlib.tb_module_B -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_B_behav xil_defaultlib.tb_module_B -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.math_real
+Compiling architecture behavioral of entity xil_defaultlib.module_B [module_b_default]
+Compiling architecture behavior of entity xil_defaultlib.tb_module_b
+Built simulation snapshot tb_module_B_behav
+execute_script: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 8332.176 ; gain = 0.000 ; free physical = 9235 ; free virtual = 16745
+INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_B_behav -key {Behavioral:sim_1:Functional:tb_module_B} -tclbatch {tb_module_B.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_B.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_B_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 8346.480 ; gain = 87.203 ; free physical = 9162 ; free virtual = 16718
+set_property top tb_module_C [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_C'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_C' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_C_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_package.vhd" into library xil_defaultlib
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_C'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_C.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_C'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_C_behav xil_defaultlib.tb_module_C -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_C_behav xil_defaultlib.tb_module_C -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.math_real
+Compiling package xil_defaultlib.wave_package
+Compiling architecture behavioral of entity xil_defaultlib.module_C [\module_C(g_n=16)\]
+Compiling architecture behavior of entity xil_defaultlib.tb_module_c
+Built simulation snapshot tb_module_C_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_C_behav -key {Behavioral:sim_1:Functional:tb_module_C} -tclbatch {tb_module_C.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_C.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_C_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8465.004 ; gain = 50.816 ; free physical = 9057 ; free virtual = 16625
+set_property top tb_module_D [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_D'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_D' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_D_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_D.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_D'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_D'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_D_behav xil_defaultlib.tb_module_D -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_D_behav xil_defaultlib.tb_module_D -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.math_real
+Compiling package xil_defaultlib.wave_package
+Compiling architecture behavioral of entity xil_defaultlib.module_D [\module_D(g_n=16)\]
+Compiling architecture behavior of entity xil_defaultlib.tb_module_d
+Built simulation snapshot tb_module_D_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_D_behav -key {Behavioral:sim_1:Functional:tb_module_D} -tclbatch {tb_module_D.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_D.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_D_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 8568.832 ; gain = 47.816 ; free physical = 9024 ; free virtual = 16594
+set_property top tb_module_C [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+current_sim simulation_2
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_C'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_C' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_C_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_C_behav xil_defaultlib.tb_module_C -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_C_behav xil_defaultlib.tb_module_C -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_C_behav -key {Behavioral:sim_1:Functional:tb_module_C} -tclbatch {tb_module_C.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_C.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_C_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 8625.840 ; gain = 0.918 ; free physical = 8938 ; free virtual = 16619
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+set_property top tb_module_B [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+current_sim simulation_1
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_B'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_B' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_B_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_B_behav xil_defaultlib.tb_module_B -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_B_behav xil_defaultlib.tb_module_B -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_B_behav -key {Behavioral:sim_1:Functional:tb_module_B} -tclbatch {tb_module_B.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_B.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_B_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 8641.852 ; gain = 0.000 ; free physical = 8663 ; free virtual = 16339
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_E'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_E' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_E_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_E.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_E'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_E.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_E'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_E_behav xil_defaultlib.tb_module_E -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_E_behav xil_defaultlib.tb_module_E -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package ieee.math_real
+Compiling package xil_defaultlib.wave_package
+Compiling architecture behavioral of entity xil_defaultlib.module_E [\module_E(g_n=16)\]
+Compiling architecture behavior of entity xil_defaultlib.tb_module_e
+Built simulation snapshot tb_module_E_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_E_behav -key {Behavioral:sim_1:Functional:tb_module_E} -tclbatch {tb_module_E.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_E.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_E_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8708.676 ; gain = 60.820 ; free physical = 8574 ; free virtual = 16285
+set_property top tb_module_D [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+current_sim simulation_3
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_D'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_D' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_D_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_D_behav xil_defaultlib.tb_module_D -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_D_behav xil_defaultlib.tb_module_D -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_D_behav -key {Behavioral:sim_1:Functional:tb_module_D} -tclbatch {tb_module_D.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_D.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_D_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 8746.422 ; gain = 0.000 ; free physical = 8613 ; free virtual = 16303
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+current_sim simulation_6
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_E'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_E' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_E_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_E_behav xil_defaultlib.tb_module_E -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_E_behav xil_defaultlib.tb_module_E -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_E_behav -key {Behavioral:sim_1:Functional:tb_module_E} -tclbatch {tb_module_E.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_E.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_E_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 8746.422 ; gain = 0.000 ; free physical = 8467 ; free virtual = 16188
+set_property top tb_module_F [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_F'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_F' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_F_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_F.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_F'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_F.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_F'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_F_behav xil_defaultlib.tb_module_F -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_F_behav xil_defaultlib.tb_module_F -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture behavioral of entity xil_defaultlib.module_F [\module_F(15,0)(15,0)(15,0)(15,0...]
+Compiling architecture behavioral of entity xil_defaultlib.tb_module_f
+Built simulation snapshot tb_module_F_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_F_behav -key {Behavioral:sim_1:Functional:tb_module_F} -tclbatch {tb_module_F.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_F.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_F_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8799.242 ; gain = 37.812 ; free physical = 8396 ; free virtual = 16143
+set_property top tb_module_H [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_H'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_H' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_H_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_H.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_H'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_H.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_H'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_H_behav xil_defaultlib.tb_module_H -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_H_behav xil_defaultlib.tb_module_H -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture behavioral of entity xil_defaultlib.module_H [\module_H(15,0)(15,0)(15,0)\]
+Compiling architecture behavioral of entity xil_defaultlib.tb_module_h
+Built simulation snapshot tb_module_H_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_H_behav -key {Behavioral:sim_1:Functional:tb_module_H} -tclbatch {tb_module_H.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_H.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_H_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 8872.070 ; gain = 47.812 ; free physical = 8342 ; free virtual = 16114
+set_property top tb_module_G [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_G'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_G' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_G_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_G.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_G'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_G.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_G'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_G_behav xil_defaultlib.tb_module_G -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_G_behav xil_defaultlib.tb_module_G -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture behavioral of entity xil_defaultlib.module_G [\module_G(g_n=8)\]
+Compiling architecture testbench of entity xil_defaultlib.tb_module_g
+Built simulation snapshot tb_module_G_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_G_behav -key {Behavioral:sim_1:Functional:tb_module_G} -tclbatch {tb_module_G.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_G.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_G_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 8945.895 ; gain = 39.812 ; free physical = 8307 ; free virtual = 16092
+set_property top tb_module_I [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/wave_generator.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_C.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_B.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_D.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_module_I'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_I' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj tb_module_I_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/module_I.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'module_I'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/hdl/tb_module_I.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_module_I'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_I_behav xil_defaultlib.tb_module_I -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_I_behav xil_defaultlib.tb_module_I -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture behavioral of entity xil_defaultlib.module_I [\module_I(g_n=16)\]
+Compiling architecture behavioral of entity xil_defaultlib.tb_module_i
+Built simulation snapshot tb_module_I_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_module_I_behav -key {Behavioral:sim_1:Functional:tb_module_I} -tclbatch {tb_module_I.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_module_I.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_I_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9012.719 ; gain = 50.812 ; free physical = 8238 ; free virtual = 16030
+launch_runs synth_1 -jobs 6
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+WARNING: [Vivado 12-4801] The synthesis checkpoint for IP '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci' is available but stale and the IP is locked. An out-of-context (OOC) run will be created and/or launched, but synthesis may not be able to complete or could result in incorrect behavior.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
+WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Synthesis target. Since these IPs are locked, no update to the output products can be done.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+[Mon May 5 10:23:46 2025] Launched synth_1...
+Run output will be captured here: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/synth_1/runme.log
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+WARNING: [Vivado 12-4801] The synthesis checkpoint for IP '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci' is available but stale and the IP is locked. An out-of-context (OOC) run will be created and/or launched, but synthesis may not be able to complete or could result in incorrect behavior.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
+WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Synthesis target. Since these IPs are locked, no update to the output products can be done.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+[Mon May 5 10:30:30 2025] Launched synth_1...
+Run output will be captured here: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/synth_1/runme.log
+launch_runs impl_1 -jobs 6
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+WARNING: [Vivado 12-4801] The synthesis checkpoint for IP '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci' is available but stale and the IP is locked. An out-of-context (OOC) run will be created and/or launched, but synthesis may not be able to complete or could result in incorrect behavior.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+[Mon May 5 10:33:37 2025] Launched impl_1...
+Run output will be captured here: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/runme.log
+open_run synth_1 -name synth_1
+Design is defaulting to impl run constrset: constrs_1
+Design is defaulting to synth run part: xc7a200tsbg484-1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 9350.176 ; gain = 0.000 ; free physical = 7512 ; free virtual = 15332
+INFO: [Netlist 29-17] Analyzing 668 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Common 17-41] Interrupt caught. Command should exit soon. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Common 17-344] 'get_clocks' was cancelled [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+Finished Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+open_run: Time (s): cpu = 00:00:14 ; elapsed = 00:00:25 . Memory (MB): peak = 10135.625 ; gain = 1098.855 ; free physical = 6754 ; free virtual = 14602
+INFO: [Common 17-344] 'open_run' was cancelled
+open_run synth_1 -name synth_1
+Design is defaulting to impl run constrset: constrs_1
+Design is defaulting to synth run part: xc7a200tsbg484-1
+INFO: [Project 1-454] Reading design checkpoint '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 10135.625 ; gain = 0.000 ; free physical = 6650 ; free virtual = 14496
+INFO: [Netlist 29-17] Analyzing 668 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+Finished Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10135.625 ; gain = 0.000 ; free physical = 6328 ; free virtual = 14170
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+open_run: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 10249.512 ; gain = 113.887 ; free physical = 6221 ; free virtual = 14078
+launch_runs impl_1 -to_step write_bitstream -jobs 12
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+WARNING: [Vivado 12-4801] The synthesis checkpoint for IP '/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/src/ip/clk_wiz_0/clk_wiz_0.xci' is available but stale and the IP is locked. An out-of-context (OOC) run will be created and/or launched, but synthesis may not be able to complete or could result in incorrect behavior.
+Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
+[Mon May 5 10:36:20 2025] Launched impl_1...
+Run output will be captured here: /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/runme.log
+open_hw_manager
+connect_hw_server -allow_non_jtag
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-2222] Launching hw_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+****** Xilinx hw_server v2024.1
+ **** Build date : May 22 2024 at 19:19:01
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+
+INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
+INFO: [Labtools 27-3417] Launching cs_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+
+******** Xilinx cs_server v2024.1.0
+ ****** Build date : Apr 27 2024-03:40:49
+ **** Build number : 2024.1.1714182049
+ ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+
+connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 10249.512 ; gain = 0.000 ; free physical = 6913 ; free virtual = 14899
+open_hw_target
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210276A79435B
+set_property PROGRAM.FILE {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+current_hw_device [get_hw_devices xc7a200t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
+INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 10249.512 ; gain = 0.000 ; free physical = 6824 ; free virtual = 14811
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 10249.512 ; gain = 0.000 ; free physical = 6959 ; free virtual = 14946
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg
+set_property xsim.view /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg [get_filesets sim_1]
+current_sim simulation_11
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+current_sim simulation_10
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+current_sim simulation_9
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg
+set_property xsim.view {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg} [get_filesets sim_1]
+current_sim simulation_8
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg
+set_property xsim.view {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg} [get_filesets sim_1]
+current_sim simulation_7
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+current_sim simulation_5
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+save_wave_config {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_C_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_C_behav.wcfg
+set_property xsim.view {/homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_G_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_E_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_D_behav.wcfg /homes/k24fomba/path/wish/tp-vhdl-mee/UE-name/tp-synthe-etudiant-k24fomba/proj/tb_module_C_behav.wcfg} [get_filesets sim_1]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+exit
+INFO: [Common 17-206] Exiting Vivado at Mon May 5 10:45:05 2025...
--
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