diff --git a/docs/.~lock.Sans nom 1.odt# b/docs/.~lock.Sans nom 1.odt#
deleted file mode 100644
index e7e0dd4d0ffb553a259f67af8de5744a243e64db..0000000000000000000000000000000000000000
--- a/docs/.~lock.Sans nom 1.odt#
+++ /dev/null
@@ -1 +0,0 @@
-,l24nicot,fl-tp-br-515,12.05.2025 15:18,file:///homes/l24nicot/.config/libreoffice/4;
\ No newline at end of file
diff --git a/docs/Sans nom 1.odt b/docs/Sans nom 1.odt
index c39e09ec508480cc8ff9dad8856d41a7a6fff7f7..54d9daa829cb23fa67b00f6a8a23d37031cfdc9c 100644
Binary files a/docs/Sans nom 1.odt and b/docs/Sans nom 1.odt differ
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9331e9ff16862013196a9e3cd259df898a03bc8e 100644
--- a/proj/AudioProc.cache/wt/synthesis.wdf
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:74625f666972556e6974:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:343030:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:35:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:6f6e655f686f74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323273:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323734342e3434354d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313034342e3931344d42:00:00
+eof:1279915618
diff --git a/proj/AudioProc.cache/wt/webtalk_pa.xml b/proj/AudioProc.cache/wt/webtalk_pa.xml
index c7fb61500f16f332a68f6f59927df1245f2c933c..3860f06b4e6b88b1ea3036f4d1f25ac1207ce4e8 100644
--- a/proj/AudioProc.cache/wt/webtalk_pa.xml
+++ b/proj/AudioProc.cache/wt/webtalk_pa.xml
@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Mon May 12 16:07:25 2025">
+<application name="pa" timeStamp="Mon May 12 16:28:35 2025">
<section name="Project Information" visible="false">
<property name="ProjectID" value="a2a460662c534046acb4b1eb8742bffd" type="ProjectID"/>
-<property name="ProjectIteration" value="2" type="ProjectIteration"/>
+<property name="ProjectIteration" value="3" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_3.xml b/proj/AudioProc.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0f282cfca228696809b58cca857391edc9fa4ce3
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/impl_1/.init_design.begin.rst b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d26c0357bc800d4738c078b5b2a2a9c8ade95c78
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l24nicot" Host="" Pid="80350">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/__synthesis_is_running__ b/proj/AudioProc.runs/impl_1/.init_design.end.rst
similarity index 100%
rename from proj/AudioProc.runs/synth_1/__synthesis_is_running__
rename to proj/AudioProc.runs/impl_1/.init_design.end.rst
diff --git a/proj/AudioProc.runs/impl_1/.nfs0000000002539445000000a3 b/proj/AudioProc.runs/impl_1/.nfs0000000002539445000000a3
new file mode 100644
index 0000000000000000000000000000000000000000..593c74796cf5911a902b1602c3bf42b97a38fe6c
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs0000000002539445000000a3 differ
diff --git a/proj/AudioProc.runs/impl_1/.nfs0000000002539eb5000000a2 b/proj/AudioProc.runs/impl_1/.nfs0000000002539eb5000000a2
new file mode 100644
index 0000000000000000000000000000000000000000..9d5cd070b50c6a153722a5ca2c8f06d4ef71cb55
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs0000000002539eb5000000a2 differ
diff --git a/proj/AudioProc.runs/impl_1/.nfs0000000002539ec4000000a1 b/proj/AudioProc.runs/impl_1/.nfs0000000002539ec4000000a1
new file mode 100644
index 0000000000000000000000000000000000000000..824fe1e27442e25bb4f9997119e2a58749ea0c90
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs0000000002539ec4000000a1 differ
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d26c0357bc800d4738c078b5b2a2a9c8ade95c78
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l24nicot" Host="" Pid="80350">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.end.rst b/proj/AudioProc.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.place_design.begin.rst b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d26c0357bc800d4738c078b5b2a2a9c8ade95c78
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l24nicot" Host="" Pid="80350">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.place_design.error.rst b/proj/AudioProc.runs/impl_1/.place_design.error.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.vivado.begin.rst b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d015549ef1329c70fd5119b8a919d36c07942346
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,10 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="l24nicot" Host="fl-tp-br-515" Pid="74165" HostCore="12" HostMemory="16146432">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="l24nicot" Host="fl-tp-br-515" Pid="80279" HostCore="12" HostMemory="16146432">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.vivado.error.rst b/proj/AudioProc.runs/impl_1/.vivado.error.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/gen_run.xml b/proj/AudioProc.runs/impl_1/gen_run.xml
index 373879b2cdf3e982002841421ed2d667d4647b60..e6dd045b34d8a45b5af143618eb97bc89afe34cc 100644
--- a/proj/AudioProc.runs/impl_1/gen_run.xml
+++ b/proj/AudioProc.runs/impl_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747058845">
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747060115">
<File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
<File Type="POSTROUTE-PHYSOPT-RQS" Name="tb_firUnit_postroute_physopted.rqs"/>
<File Type="ROUTE-RQS" Name="tb_firUnit_routed.rqs"/>
diff --git a/proj/AudioProc.runs/impl_1/init_design.pb b/proj/AudioProc.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..7c143029c7ade2e1d170ede1233d0b13efeb774f
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/init_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/opt_design.pb b/proj/AudioProc.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..10c15df6a66008b9297ae77b7186315d79ac8de6
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/opt_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/place_design.pb b/proj/AudioProc.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..02ee2c6f4df1f00c102fc2fb76da75142690bca1
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/place_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/project.wdf b/proj/AudioProc.runs/impl_1/project.wdf
index 1a09bd1a6e8c5048c552c36092027065c62c99d2..d135852a5d56c8e81b25d9714eeb5ca1229e6c76 100644
--- a/proj/AudioProc.runs/impl_1/project.wdf
+++ b/proj/AudioProc.runs/impl_1/project.wdf
@@ -13,7 +13,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3331:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3431:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
@@ -28,4 +28,4 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346466313732396165393434316161366364373034663438313832636337:506172656e742050412070726f6a656374204944:00
-eof:4252997287
+eof:1088738618
diff --git a/proj/AudioProc.runs/impl_1/runme.log b/proj/AudioProc.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..ba540f79d97f517fbed32e0cbbc83b74825aeb1c
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.log
@@ -0,0 +1,315 @@
+
+*** Running vivado
+ with args -log tb_firUnit.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source tb_firUnit.tcl -notrace
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Mon May 12 16:30:09 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source tb_firUnit.tcl -notrace
+create_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:27 . Memory (MB): peak = 1680.551 ; gain = 325.840 ; free physical = 4426 ; free virtual = 14540
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top tb_firUnit -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.262 ; gain = 0.000 ; free physical = 3975 ; free virtual = 14086
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNC'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTND'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNL'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNR'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNU'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'rstn'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_adc_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_bclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_dac_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_lrclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_mclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'scl'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sda'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2183.512 ; gain = 0.000 ; free physical = 3875 ; free virtual = 13980
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+8 Infos, 28 Warnings, 27 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 2183.512 ; gain = 497.023 ; free physical = 3875 ; free virtual = 13980
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2253.480 ; gain = 69.969 ; free physical = 3851 ; free virtual = 13960
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2709.441 ; gain = 455.961 ; free physical = 3443 ; free virtual = 13546
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Phase 1 Initialization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Phase 2 Timer Update And Timing Data Collection | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Retarget | Checksum: 144339148
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Constant propagation | Checksum: 144339148
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Sweep | Checksum: 144339148
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+BUFG optimization | Checksum: 144339148
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Shift Register Optimization | Checksum: 144339148
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Post Processing Netlist | Checksum: 144339148
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Phase 9 Finalization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 0 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Ending Netlist Obfuscation Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+INFO: [Common 17-83] Releasing license: Implementation
+26 Infos, 28 Warnings, 27 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3053.293 ; gain = 869.781 ; free physical = 3127 ; free virtual = 13231
+INFO: [Vivado 12-24828] Executing command : report_drc -file tb_firUnit_drc_opted.rpt -pb tb_firUnit_drc_opted.pb -rpx tb_firUnit_drc_opted.rpx
+Command: report_drc -file tb_firUnit_drc_opted.rpt -pb tb_firUnit_drc_opted.pb -rpx tb_firUnit_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+INFO: [Common 17-1381] The checkpoint '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/tb_firUnit_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 981aeb64
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+Phase 1 Placer Initialization | Checksum: 981aeb64
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+ERROR: [Place 30-494] The design is empty
+Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
+Ending Placer Task | Checksum: 981aeb64
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+41 Infos, 28 Warnings, 27 Critical Warnings and 2 Errors encountered.
+place_design failed
+ERROR: [Common 17-69] Command failed: Placer could not place all instances
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:31:24 2025...
diff --git a/proj/AudioProc.runs/impl_1/tb_firUnit.vdi b/proj/AudioProc.runs/impl_1/tb_firUnit.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..b66f07bb589b7ea7d52655e7510529227963ecaa
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/tb_firUnit.vdi
@@ -0,0 +1,325 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 16:30:09 2025
+# Process ID: 80350
+# Current directory: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1
+# Command line: vivado -log tb_firUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source tb_firUnit.tcl -notrace
+# Log file: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/tb_firUnit.vdi
+# Journal file: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-515
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4324.503 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :15845 MB
+#-----------------------------------------------------------
+source tb_firUnit.tcl -notrace
+create_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:27 . Memory (MB): peak = 1680.551 ; gain = 325.840 ; free physical = 4426 ; free virtual = 14540
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top tb_firUnit -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.262 ; gain = 0.000 ; free physical = 3975 ; free virtual = 14086
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNC'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTND'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNL'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNR'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNU'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'rstn'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_adc_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_bclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_dac_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_lrclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_mclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'scl'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sda'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2183.512 ; gain = 0.000 ; free physical = 3875 ; free virtual = 13980
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+8 Infos, 28 Warnings, 27 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 2183.512 ; gain = 497.023 ; free physical = 3875 ; free virtual = 13980
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2253.480 ; gain = 69.969 ; free physical = 3851 ; free virtual = 13960
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2709.441 ; gain = 455.961 ; free physical = 3443 ; free virtual = 13546
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Phase 1 Initialization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Phase 2 Timer Update And Timing Data Collection | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Retarget | Checksum: 144339148
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Constant propagation | Checksum: 144339148
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3021.277 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Sweep | Checksum: 144339148
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+BUFG optimization | Checksum: 144339148
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Shift Register Optimization | Checksum: 144339148
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Post Processing Netlist | Checksum: 144339148
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Phase 9 Finalization | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 0 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3053.293 ; gain = 32.016 ; free physical = 3127 ; free virtual = 13231
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+Ending Netlist Obfuscation Task | Checksum: 144339148
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3053.293 ; gain = 0.000 ; free physical = 3127 ; free virtual = 13231
+INFO: [Common 17-83] Releasing license: Implementation
+26 Infos, 28 Warnings, 27 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3053.293 ; gain = 869.781 ; free physical = 3127 ; free virtual = 13231
+INFO: [Vivado 12-24828] Executing command : report_drc -file tb_firUnit_drc_opted.rpt -pb tb_firUnit_drc_opted.pb -rpx tb_firUnit_drc_opted.rpx
+Command: report_drc -file tb_firUnit_drc_opted.rpt -pb tb_firUnit_drc_opted.pb -rpx tb_firUnit_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+INFO: [Common 17-1381] The checkpoint '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/tb_firUnit_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 981aeb64
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+Phase 1 Placer Initialization | Checksum: 981aeb64
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+ERROR: [Place 30-494] The design is empty
+Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
+Ending Placer Task | Checksum: 981aeb64
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3168.086 ; gain = 0.000 ; free physical = 3114 ; free virtual = 13222
+41 Infos, 28 Warnings, 27 Critical Warnings and 2 Errors encountered.
+place_design failed
+ERROR: [Common 17-69] Command failed: Placer could not place all instances
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:31:24 2025...
diff --git a/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.pb b/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.pb differ
diff --git a/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpt b/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a58ff13d3037e6f7f7716d97cf87ab41d8e833fb
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Mon May 12 16:31:23 2025
+| Host : fl-tp-br-515 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_drc -file tb_firUnit_drc_opted.rpt -pb tb_firUnit_drc_opted.pb -rpx tb_firUnit_drc_opted.rpx
+| Design : tb_firUnit
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpx b/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..18db1c8b86ff645e9e8d8ac51ecab5deffcb2a5c
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/tb_firUnit_drc_opted.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/tb_firUnit_opt.dcp b/proj/AudioProc.runs/impl_1/tb_firUnit_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..4ea83c70eed7e7db39eef87aadd2dad3623cf678
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/tb_firUnit_opt.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/vivado.jou b/proj/AudioProc.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..d2d99cf10b5090fc234a1a3f06887bf317cc154f
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 16:30:09 2025
+# Process ID: 80350
+# Current directory: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1
+# Command line: vivado -log tb_firUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source tb_firUnit.tcl -notrace
+# Log file: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/tb_firUnit.vdi
+# Journal file: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-515
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4324.503 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :15845 MB
+#-----------------------------------------------------------
+source tb_firUnit.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado.pb b/proj/AudioProc.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b155e40f06a230303a04d2a77f07560e35c5dc93
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/.lpr b/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/.lpr
deleted file mode 100644
index afc0a86cf8f820e635f040c3869b4b647d11ec04..0000000000000000000000000000000000000000
--- a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/.lpr
+++ /dev/null
@@ -1,7 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2024.1 (64-bit) -->
-<!-- -->
-<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
-<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
-
-<labtools version="1" minor="0"/>
diff --git a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/dcp.xml b/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/dcp.xml
deleted file mode 100755
index 5534b8a08499b3b5f142133dd39029173395d6f9..0000000000000000000000000000000000000000
--- a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/dcp.xml
+++ /dev/null
@@ -1,27 +0,0 @@
-<?xml version="1.0"?>
-<Checkpoint Version="22" Minor="0">
- <BUILD_NUMBER Name="5076996"/>
- <FULL_BUILD Name="SW Build 5076996 on Wed May 22 18:36:09 MDT 2024"/>
- <PRODUCT Name="Vivado v2024.1 (64-bit)"/>
- <Part Name="xc7a200tsbg484-1"/>
- <FeatureSet Name="FeatureSet_Classic"/>
- <NEXTGEN_VERSAL Name="0"/>
- <Top Name="tb_firUnit"/>
- <DisableAutoIOBuffers Name="0"/>
- <OutOfContext Name="0"/>
- <MacroLevel Name="1"/>
- <RunGenerated Name="1"/>
- <HDPlatform Name="0"/>
- <File Type="VERILOG_STUB" Name="tb_firUnit_stub.v" ModTime="1746799479"/>
- <File Type="VHDL_STUB" Name="tb_firUnit_stub.vhdl" ModTime="1746799479"/>
- <File Type="PARAMXML" Name="tb_firUnit_param.xml" ModTime="1746799479"/>
- <File Type="PARAMXML" Name="tb_firUnit_param.xml" ModTime="1746799479"/>
- <File Type="XN" Name="tb_firUnit.xn" ModTime="1746799479"/>
- <File Type="EDIF" Name="tb_firUnit.edf" ModTime="1746799479"/>
- <File Type="INCR" Name="tb_firUnit.incr" ModTime="1746799479"/>
- <File Type="RDA" Name="tb_firUnit.rda" ModTime="1746799479"/>
- <File Type="JSON_RDA" Name="tb_firUnit_rda.json" ModTime="1746799479"/>
- <File Type="WDF" Name="tb_firUnit.wdf" ModTime="1746799479"/>
- <File Type="SYNTH" Name="tb_firUnit.synth" ModTime="1746799479"/>
-</Checkpoint>
-
diff --git a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/incrSyn/tb_firUnit.gnd b/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/incrSyn/tb_firUnit.gnd
deleted file mode 100644
index 30f6370ebe3d71c5fcbe7f9a870d510d6dd170e5..0000000000000000000000000000000000000000
--- a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/incrSyn/tb_firUnit.gnd
+++ /dev/null
@@ -1 +0,0 @@
-the design is too small
diff --git a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/top.rda b/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/top.rda
deleted file mode 100755
index f239324ac210dbff00fa8cacf684a29879d9ade5..0000000000000000000000000000000000000000
Binary files a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/refSynth/top.rda and /dev/null differ
diff --git a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/wt/project.wpc b/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/wt/project.wpc
deleted file mode 100644
index 834da226cf3908e30536d5ca3070213c82a2f18b..0000000000000000000000000000000000000000
--- a/proj/AudioProc.runs/synth_1/.Xil/Vivado-73726-fl-tp-br-515/wt/project.wpc
+++ /dev/null
@@ -1,3 +0,0 @@
-version:1
-6d6f64655f636f756e7465727c42617463684d6f6465:1
-eof:
diff --git a/proj/AudioProc.runs/synth_1/.nfs000000000253a07e000000a4 b/proj/AudioProc.runs/synth_1/.nfs000000000253a07e000000a4
new file mode 100644
index 0000000000000000000000000000000000000000..253f553921a73c22221cff3474eb8bab332f3cb6
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/.nfs000000000253a07e000000a4 differ
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
index 323afd7be99cabda4150f7646b76c6ad9d8967b4..69d75660f2fd0cd9cc4bf3ab5070aea7b126e357 100644
--- a/proj/AudioProc.runs/synth_1/.vivado.begin.rst
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="l24nicot" Host="fl-tp-br-515" Pid="73655" HostCore="12" HostMemory="16146432">
+ <Process Command="vivado" Owner="l24nicot" Host="fl-tp-br-515" Pid="79766" HostCore="12" HostMemory="16146432">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/.vivado.end.rst b/proj/AudioProc.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/__synthesis_is_complete__ b/proj/AudioProc.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
index cae9c9e244e1200fafd8b1be9d09a4297a240933..631f689d66694212d273f6d0b6c097bb8eef6861 100644
--- a/proj/AudioProc.runs/synth_1/gen_run.xml
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747058844" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/tb_firUnit.dcp">
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747060115" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/tb_firUnit.dcp">
<File Type="VDS-TIMINGSUMMARY" Name="tb_firUnit_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="tb_firUnit.dcp"/>
<File Type="RDS-UTIL-PB" Name="tb_firUnit_utilization_synth.pb"/>
diff --git a/proj/AudioProc.runs/synth_1/incr_synth_reason.pb b/proj/AudioProc.runs/synth_1/incr_synth_reason.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4cb4ed43e865edf4e8dcb3c9857bfe8acfc68b23
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/incr_synth_reason.pb
@@ -0,0 +1 @@
+� 6No compile time benefit to using incremental synthesis
\ No newline at end of file
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
index 85b500631d2d902de9466a3d2faac7a5751ee4ec..43f1cb4f1bfede921908aa47319b532d4f1b01d6 100644
--- a/proj/AudioProc.runs/synth_1/runme.log
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -7,12 +7,12 @@
**** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
**** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
**** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
- **** Start of session at: Mon May 12 16:07:28 2025
+ **** Start of session at: Mon May 12 16:28:37 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
source tb_firUnit.tcl -notrace
-create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1680.613 ; gain = 325.840 ; free physical = 5055 ; free virtual = 14804
+create_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:29 . Memory (MB): peak = 1680.688 ; gain = 327.840 ; free physical = 4412 ; free virtual = 14526
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -26,3 +26,320 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Device 21-403] Loading part xc7a200tsbg484-1
INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 80067
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2500.902 ; gain = 421.527 ; free physical = 3303 ; free virtual = 13415
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'tb_firUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:36]
+WARNING: [Synth 8-312] ignoring unsynthesizable construct: extra waveform elements [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:57]
+WARNING: [Synth 8-312] ignoring unsynthesizable construct: extra waveform elements [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd:42]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/controlUnit.vhd:45]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/controlUnit.vhd:45]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd:42]
+INFO: [Synth 8-256] done synthesizing module 'tb_firUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:36]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2577.840 ; gain = 498.465 ; free physical = 3214 ; free virtual = 13327
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2592.684 ; gain = 513.309 ; free physical = 3212 ; free virtual = 13326
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2592.684 ; gain = 513.309 ; free physical = 3212 ; free virtual = 13326
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2592.684 ; gain = 0.000 ; free physical = 3212 ; free virtual = 13326
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNC'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTND'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNL'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNR'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNU'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'rstn'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_adc_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_bclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_dac_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_lrclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_mclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'scl'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sda'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2736.434 ; gain = 0.000 ; free physical = 3194 ; free virtual = 13307
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2736.434 ; gain = 0.000 ; free physical = 3194 ; free virtual = 13307
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2736.434 ; gain = 657.059 ; free physical = 3213 ; free virtual = 13327
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3213 ; free virtual = 13327
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3213 ; free virtual = 13326
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_currentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 000001 | 000
+ store | 000010 | 001
+ processing_loop | 000100 | 010
+ output | 001000 | 011
+ wait_end_sample | 010000 | 100
+ iSTATE | 100000 | 111
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_currentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_nextState_reg' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/controlUnit.vhd:62]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3209 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 16 Bit Adders := 1
+ 2 Input 4 Bit Adders := 1
++---Registers :
+ 36 Bit Registers := 1
+ 16 Bit Registers := 17
+ 4 Bit Registers := 1
++---Muxes :
+ 2 Input 36 Bit Muxes := 1
+ 16 Input 12 Bit Muxes := 1
+ 5 Input 6 Bit Muxes := 1
+ 2 Input 6 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 1
+ 6 Input 3 Bit Muxes := 1
+ 6 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 9
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[5]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[4]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[3]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[2]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[1]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[0]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[5]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[3]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[2]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[1]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[0]) is unused and will be removed from module tb_firUnit.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3201 ; free virtual = 13318
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3206 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3206 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3206 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++-+-----+------+
+| |Cell |Count |
++-+-----+------+
++-+-----+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 14 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2744.438 ; gain = 521.312 ; free physical = 3191 ; free virtual = 13308
+Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.445 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.445 ; gain = 0.000 ; free physical = 3191 ; free virtual = 13308
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.445 ; gain = 0.000 ; free physical = 3412 ; free virtual = 13529
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: ac18a5e4
+INFO: [Common 17-83] Releasing license: Synthesis
+31 Infos, 44 Warnings, 27 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2744.445 ; gain = 1052.852 ; free physical = 3420 ; free virtual = 13537
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2263.667; main = 1891.119; forked = 422.524
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3849.148; main = 2744.441; forked = 1104.707
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+INFO: [Common 17-1381] The checkpoint '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1/tb_firUnit.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file tb_firUnit_utilization_synth.rpt -pb tb_firUnit_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:30:05 2025...
diff --git a/proj/AudioProc.runs/synth_1/tb_firUnit.dcp b/proj/AudioProc.runs/synth_1/tb_firUnit.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..7d370c1d3d6f21ab131f0d56a75ab90ffa84f38f
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/tb_firUnit.dcp differ
diff --git a/proj/AudioProc.runs/synth_1/tb_firUnit.tcl b/proj/AudioProc.runs/synth_1/tb_firUnit.tcl
index f36f080506a029b2c03ab0bcf4819bd3387a93ef..af85f06a3d9ace72267da459db848c1902b7648d 100644
--- a/proj/AudioProc.runs/synth_1/tb_firUnit.tcl
+++ b/proj/AudioProc.runs/synth_1/tb_firUnit.tcl
@@ -56,6 +56,7 @@ if {$::dispatch::connected} {
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param chipscope.maxJobs 3
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a200tsbg484-1
diff --git a/proj/AudioProc.runs/synth_1/tb_firUnit.vds b/proj/AudioProc.runs/synth_1/tb_firUnit.vds
index 6e6f44c6f76ef4077d893a38193f1a4137131f37..6927d2916497db5e3a1c6e956ac8246d4cb725b6 100644
--- a/proj/AudioProc.runs/synth_1/tb_firUnit.vds
+++ b/proj/AudioProc.runs/synth_1/tb_firUnit.vds
@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Mon May 12 16:07:28 2025
-# Process ID: 73726
+# Start of session at: Mon May 12 16:28:37 2025
+# Process ID: 79837
# Current directory: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1
# Command line: vivado -log tb_firUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source tb_firUnit.tcl
# Log file: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1/tb_firUnit.vds
@@ -13,16 +13,16 @@
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4392.944 MHz
+# CPU Frequency :4396.217 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
-# Available Virtual :16177 MB
+# Available Virtual :15713 MB
#-----------------------------------------------------------
source tb_firUnit.tcl -notrace
-create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1680.613 ; gain = 325.840 ; free physical = 5055 ; free virtual = 14804
+create_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:29 . Memory (MB): peak = 1680.688 ; gain = 327.840 ; free physical = 4412 ; free virtual = 14526
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -36,3 +36,320 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Device 21-403] Loading part xc7a200tsbg484-1
INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 80067
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2500.902 ; gain = 421.527 ; free physical = 3303 ; free virtual = 13415
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'tb_firUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:36]
+WARNING: [Synth 8-312] ignoring unsynthesizable construct: extra waveform elements [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:57]
+WARNING: [Synth 8-312] ignoring unsynthesizable construct: extra waveform elements [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd:42]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/controlUnit.vhd:45]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/controlUnit.vhd:45]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd:42]
+INFO: [Synth 8-256] done synthesizing module 'tb_firUnit' (0#1) [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd:36]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2577.840 ; gain = 498.465 ; free physical = 3214 ; free virtual = 13327
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2592.684 ; gain = 513.309 ; free physical = 3212 ; free virtual = 13326
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2592.684 ; gain = 513.309 ; free physical = 3212 ; free virtual = 13326
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2592.684 ; gain = 0.000 ; free physical = 3212 ; free virtual = 13326
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:8]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:14]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:18]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:19]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNC'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:23]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTND'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:24]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNL'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:25]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNR'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:26]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNU'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'rstn'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:28]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:32]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw2'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:34]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw3'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:35]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw4'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:36]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw5'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:37]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw6'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:38]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw7'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:39]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_adc_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:91]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_bclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:92]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_dac_sdata'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:93]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_lrclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:94]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_mclk'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:95]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'scl'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:202]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sda'. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc:203]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/constraints/NexysVideo_Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2736.434 ; gain = 0.000 ; free physical = 3194 ; free virtual = 13307
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2736.434 ; gain = 0.000 ; free physical = 3194 ; free virtual = 13307
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2736.434 ; gain = 657.059 ; free physical = 3213 ; free virtual = 13327
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3213 ; free virtual = 13327
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3213 ; free virtual = 13326
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_currentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 000001 | 000
+ store | 000010 | 001
+ processing_loop | 000100 | 010
+ output | 001000 | 011
+ wait_end_sample | 010000 | 100
+ iSTATE | 100000 | 111
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_currentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_nextState_reg' [/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/controlUnit.vhd:62]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3209 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 16 Bit Adders := 1
+ 2 Input 4 Bit Adders := 1
++---Registers :
+ 36 Bit Registers := 1
+ 16 Bit Registers := 17
+ 4 Bit Registers := 1
++---Muxes :
+ 2 Input 36 Bit Muxes := 1
+ 16 Input 12 Bit Muxes := 1
+ 5 Input 6 Bit Muxes := 1
+ 2 Input 6 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 1
+ 6 Input 3 Bit Muxes := 1
+ 6 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 9
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[5]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[4]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[3]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[2]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[1]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_currentState_reg[0]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[5]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[3]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[2]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[1]) is unused and will be removed from module tb_firUnit.
+WARNING: [Synth 8-3332] Sequential element (firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[0]) is unused and will be removed from module tb_firUnit.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3201 ; free virtual = 13318
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3206 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3206 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3206 ; free virtual = 13323
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++-+-----+------+
+| |Cell |Count |
++-+-----+------+
++-+-----+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.438 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 14 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2744.438 ; gain = 521.312 ; free physical = 3191 ; free virtual = 13308
+Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2744.445 ; gain = 665.062 ; free physical = 3191 ; free virtual = 13308
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.445 ; gain = 0.000 ; free physical = 3191 ; free virtual = 13308
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.445 ; gain = 0.000 ; free physical = 3412 ; free virtual = 13529
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: ac18a5e4
+INFO: [Common 17-83] Releasing license: Synthesis
+31 Infos, 44 Warnings, 27 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2744.445 ; gain = 1052.852 ; free physical = 3420 ; free virtual = 13537
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2263.667; main = 1891.119; forked = 422.524
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3849.148; main = 2744.441; forked = 1104.707
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+INFO: [Common 17-1381] The checkpoint '/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1/tb_firUnit.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file tb_firUnit_utilization_synth.rpt -pb tb_firUnit_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:30:05 2025...
diff --git a/proj/AudioProc.runs/synth_1/tb_firUnit_utilization_synth.pb b/proj/AudioProc.runs/synth_1/tb_firUnit_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..d1022321314445d2f662e974279993af9d9b5cb7
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/tb_firUnit_utilization_synth.pb differ
diff --git a/proj/AudioProc.runs/synth_1/tb_firUnit_utilization_synth.rpt b/proj/AudioProc.runs/synth_1/tb_firUnit_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..fc26b4de37b08bf888b5399183960f8c44459b01
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/tb_firUnit_utilization_synth.rpt
@@ -0,0 +1,172 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Mon May 12 16:30:05 2025
+| Host : fl-tp-br-515 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_utilization -file tb_firUnit_utilization_synth.rpt -pb tb_firUnit_utilization_synth.pb
+| Design : tb_firUnit
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Logic | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Flip Flop | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 0 | Yes | - | Set |
+| 0 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 0 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 0 | 0 | 0 | 285 | 0.00 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
index 3b0739689f57fee20991fbc719220c64732a547a..9b4418168cee3bc0ebf62e99ad707c005f2fb095 100644
--- a/proj/AudioProc.runs/synth_1/vivado.jou
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Mon May 12 16:07:28 2025
-# Process ID: 73726
+# Start of session at: Mon May 12 16:28:37 2025
+# Process ID: 79837
# Current directory: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1
# Command line: vivado -log tb_firUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source tb_firUnit.tcl
# Log file: /homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/proj/AudioProc.runs/synth_1/tb_firUnit.vds
@@ -13,12 +13,12 @@
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4392.944 MHz
+# CPU Frequency :4396.217 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
-# Available Virtual :16177 MB
+# Available Virtual :15713 MB
#-----------------------------------------------------------
source tb_firUnit.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
index 9c590e3d969321290bf425379c8a127a5f72019c..583f8ec186ccc5dd9e7558e9cd9c5762209df8d9 100644
Binary files a/proj/AudioProc.runs/synth_1/vivado.pb and b/proj/AudioProc.runs/synth_1/vivado.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
index 3c7ba34ed004d72fcfabfb8aa20a61e9bc7ef49b..a1594af4d4a96b9d652cfc0a39abf48262acc2d3 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
-# Generated by Vivado on Mon May 12 16:03:52 CEST 2025
+# Generated by Vivado on Mon May 12 16:26:44 CEST 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
index c5493a92bc3878bb552aa7cef0623eff6553f076..620eb2716742e428c1c6bad2e695a805a1905a41 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
-# Generated by Vivado on Mon May 12 16:03:54 CEST 2025
+# Generated by Vivado on Mon May 12 16:26:46 CEST 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
index 0ce3bab20fd26e42dc28e30e4b307a370d2a8447..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
@@ -1,21 +0,0 @@
-Time resolution is 1 ps
-Stopped at time : 0 fs : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 19 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 125 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 135 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 145 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 155 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 165 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 175 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 185 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 195 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 205 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 215 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 225 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 235 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 245 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 255 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 265 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 315 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 325 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
-Stopped at time : 335 ns : File "/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd" Line 151
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
index c17c31bfcd5fe130bec18f9972a5743051f6b035..b968e880816766b408af429d30cee37f9fd04d51 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
-# Generated by Vivado on Mon May 12 16:02:26 CEST 2025
+# Generated by Vivado on Mon May 12 16:18:14 CEST 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index f8d76e2b03fa99df299f7f0d4710f19479cc3761..763161a4e671470567328ab2ba58b2a39adeb1a9 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb and b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
index f3273028f603e4810a84b110bd88c43a047ebf92..fdbc612e3497473d6b58c7f0c1432b55416f6136 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
@@ -1,2 +1 @@
Breakpoint File Version 1.0
-151,true,"/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd"
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
index 37f104a61d48f09312550ed9b3ce64d79b7c0aa3..a5153658c9c0efd5474484edd76520803eeb02a2 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
index b8dec24608bc5eadd699a0113423ae35a4827848..72315f73c672930dbdbceaa2c808fb21427f9f98 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
index e406e470775a77dfece7c32f0bae1014f700966c..8719994eb7907635616023aabf9c51f01bc7df82 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
index 1593e3a91d942a03c28b222ccca493804212d414..7a46b7dd39cdb4896eb8aabeb7087f6d18fe7df5 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -1,6 +1,6 @@
{
- crc : 1143525208533358939 ,
+ crc : 17597839079798958422 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
buildDate : "May 22 2024" ,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
index 88786c17baca8370ce20465c4bb205e41a8b7615..b5a7a737163d950baa163b4dc5f85e8711469a08 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
index c28c84d68e27da5f1de4e8577d991ed1a8af5b02..ca532f12be797e0e462d148c68ad7fa2f3d9c1be 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
index d9dfb41e729f1be9d061a05d63e2d5b0276a9eb1..99c0c774f83770455aedd875993e271be99ce512 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
index 5b3ad0b68b3b70e4a990b5ae78cb919e4e6cac6e..7fd9eb173f1befd6f1b6f635c7ba1d84bcf39111 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -28,8 +28,8 @@ VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=193
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=209
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
-OBJECT_NAME_COLUMN_WIDTH=207
-OBJECT_VALUE_COLUMN_WIDTH=640
+OBJECT_NAME_COLUMN_WIDTH=188
+OBJECT_VALUE_COLUMN_WIDTH=49
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
index 1d21f3b9a648c61953d3b82e0b2ad96b73a5576d..265984a53e0b224f0b93e030a78eae79223d6ad9 100755
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
index 76d4694c39c0c1036ea800e603037a85d0e5a225..87f100322402f70354b9e176d686ae070ca783ec 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -1,7 +1,4 @@
-Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 39085
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 46891
Design successfully loaded
Design Loading Memory Usage: 20176 KB (Peak: 20752 KB)
Design Loading CPU Usage: 10 ms
-Simulation completed
-Simulation Memory Usage: 110112 KB (Peak: 159444 KB)
-Simulation CPU Usage: 70 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
index 05e0ab7281ae3cfe00b0e1966fb470aea8bbb9ae..aebf5f886dabe12b39cd29839ad4a4fa0bb00b88 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
index cab88913091cf55618a3e92e942754b91fde32bc..6058b4cb0c5160bb656330d06ecdaa7bf88c0435 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
index 9d7b37da0e7d042258150b04e4d745e44f4e261f..a53b915fa7963bd4c96f94cf16a56850851e7a7d 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index c692e4e4f5a7728e606d0ac1cb4bc204f6e730e7..06b999af6ee16a4703c01dd200aacd859f55b1eb 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -12,7 +12,7 @@ May 22 2024
/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd,1746792867,vhdl,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/i2s_ctl.vhd,1746792867,vhdl,,,,i2s_ctl,,,,,,,,
/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.v,1746792867,verilog,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/audioProc.v,,\operativeUnit\,,,,,,,,
-/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd,1747058630,vhdl,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/operativeUnit.vhd,1747060002,vhdl,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/tb_firUnit.vhd,1746792867,vhdl,,,,tb_firunit,,,,,,,,
/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/ip/clk_wiz_0/clk_wiz_0.v,1746792867,verilog,,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/hdl/audio_init.v,,clk_wiz_0,,,,,,,,
/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,1746792867,verilog,,/homes/l24nicot/path/wish/tp-vhdl-mee/UE-name/tp-filtre-etudiant/src/ip/clk_wiz_0/clk_wiz_0.v,,clk_wiz_0_clk_wiz,,,,,,,,
diff --git a/proj/AudioProc.srcs/utils_1/imports/synth_1/tb_firUnit.dcp b/proj/AudioProc.srcs/utils_1/imports/synth_1/tb_firUnit.dcp
index f0096280a919e3d4c9b7665975d057766fac19b6..97d1db7731ffb47fbb9d64bab0450cce457d3861 100755
Binary files a/proj/AudioProc.srcs/utils_1/imports/synth_1/tb_firUnit.dcp and b/proj/AudioProc.srcs/utils_1/imports/synth_1/tb_firUnit.dcp differ
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
index 16d3300d2ada9265d63747eaaf96c33fcb69611f..ecde4fef41a3339705d21c96bc4665b2c385b461 100644
--- a/proj/AudioProc.xpr
+++ b/proj/AudioProc.xpr
@@ -60,7 +60,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="31"/>
+ <Option Name="WTXSimLaunchSim" Val="41"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index f2d7f8b4edc1a9ae4a3328d12cc511ec6f4dd835..388329b6ac71182be931f3db6b6487a0fb330cfa 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -180,9 +180,10 @@ begin
SR_filteredSample <= (others => '0');
elsif rising_edge(I_clock) then
if I_loadOutput = '1' then
- SR_filteredSample <= SC_addResult(30 downto 15);
if SC_addResult(14) = '1' then
- SR_filteredSample <= SR_filteredSample + 1;
+ SR_filteredSample <= SC_addResult(30 downto 15) + 1;
+ else
+ SR_filteredSample <= SC_addResult(30 downto 15);
end if;
end if;
end if;