diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd index 3997149f5e14834cb7b8b646d1d181513aacccf7..c5e11b46f0a65ce1b820e68fcdd411390eab5354 100644 --- a/src/hdl/operativeUnit.vhd +++ b/src/hdl/operativeUnit.vhd @@ -25,7 +25,7 @@ entity operativeUnit is end entity operativeUnit; architecture arch_operativeUnit of operativeUnit is - type registerFile is array(0 to 15) of signed(15 downto 0); + type registerFile is array(0 to 31) of signed(15 downto 0); signal SR_coefRegister : registerFile; signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples @@ -33,29 +33,72 @@ architecture arch_operativeUnit of operativeUnit is signal SC_multOperand2 : signed(15 downto 0); signal SC_MultResult : signed(31 downto 0); -- Result of the multiplication Xi*Hi signal SC_addResult : signed(35 downto 0); -- result of the accumulation addition - signal SR_sum : signed(35 downto 0); -- Accumulation register + signal SR_sum : signed(35 downto 0); -- Accumulation re gister signal SR_filteredSample: signed(15 downto 0); -- filtered sample storage register signal SR_readAddress : integer range 0 to 15; -- register files read address begin + + -- Low-pass filter provided with octave (or Matlab ;)) script : + -- pkg load signal + -- + -- fs=44100 + -- fn=fs/2 + -- n=32 + -- fc=1000 + -- fHP=fir1(n-1,fc/fn,"high"); + -- + -- function quantized_signal = quantize(signal, q) + -- % Quantize the signal to q bits + -- max_val = 2^(q-1) - 1; + -- min_val = -2^(q-1); + -- quantized_signal = round(min(max(signal * 2^(q-1), min_val), max_val)) / 2^(q-1); + -- end + -- + -- q=16 + -- + -- fHPq= quantize(fHP,q); + -- + -- for i=1:n + -- printf("to_signed(%d,%d),\n", fHPq(i)*2^(q-1),q); + -- endfor + -- Table to store the filter coefficients obtained with the previous script - SR_coefRegister <= (to_signed(317,16), - to_signed(476,16), - to_signed(925,16), - to_signed(1589,16), - to_signed(2354,16), - to_signed(3087,16), - to_signed(3661,16), - to_signed(3975,16), - to_signed(3975,16), - to_signed(3661,16), - to_signed(3087,16), - to_signed(2354,16), - to_signed(1589,16), - to_signed(925,16), - to_signed(476,16), - to_signed(317,16) + + + SR_coefRegister <= (to_signed(-40,16), + to_signed(-52,16), + to_signed(-78,16), + to_signed(-122,16), + to_signed(-185,16), + to_signed(-270,16), + to_signed(-376,16), + to_signed(-501,16), + to_signed(-640,16), + to_signed(-789,16), + to_signed(-940,16), + to_signed(-1086,16), + to_signed(-1219,16), + to_signed(-1331,16), + to_signed(-1416,16), + to_signed(-1470,16), + to_signed(31316,16), + to_signed(-1470,16), + to_signed(-1416,16), + to_signed(-1331,16), + to_signed(-1219,16), + to_signed(-1086,16), + to_signed(-940,16), + to_signed(-789,16), + to_signed(-640,16), + to_signed(-501,16), + to_signed(-376,16), + to_signed(-270,16), + to_signed(-185,16), + to_signed(-122,16), + to_signed(-78,16), + to_signed(-52,16) ); -- Process to describe the shift register storing the input samples @@ -105,7 +148,7 @@ begin -- Register to store the accumulated value if the loadSum is active -- It also reduces the width of the sum to fit to the input and output -- signal widths (be careful with truncating/rounding) - sum_acc : process (I_clock, I_reset) is + sum_acc : process (I_clock, I_reset) is begin if I_reset = '1' then -- asynchronous reset (active high) SR_sum <= (others => '0');