diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index ddeb02c0fbfd073b938f76707271f52cfa985cbd..00a9c7fcea121edaf85a0aa02b8be5de4a347ba7 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -15,16 +15,23 @@ Il y a deux processus dans le code : le premier est un processus synchrone qui c
Après simulation, on obtient exactement la séquence attendue en sortie du filtre. Ainsi, on peut valider notre description VHDL.
-
### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
Oui
### Question filtre 4 : Combien de processus sont utilisés et de quelles natures sont-ils ?
-Il y a 4 processus
+Il y a 4 processus séquentiels :
+- Le processus ***shift*** est de nature séquentiel. Il s'agit d'un processus de registre à décalage. Il stocke les échantillons d'entrées dans un registre à décalage quand I_loadShift='1'
+- Le processus ***incr_adress*** est aussi séquentiel. Il permet l'incrémentation de l'adresse des multiplexeurs.
+- Le processus ***sum_acc*** est séquentiel. Il accumule la somme (convolution)
+- Le processus ***store_result*** est également séquentiel. Il stocke le résultat final.
### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
-
+Après simulation, nous remarquons que la séquence de sortie correspond à celle attendue à une unité près. Par exemple, au lieu d'avoir la suite 317, 476, 925, 1589, ... nous avons la suite 316, 475, 924, 1588, ...
+La simulation ne nous permet donc pas de valider notre description VHDL. Le problème est due au fait qu'on n'arrondis pas lorsqu'on passe de 36 bits à 16 bits. En effet, dans notre description VHDL, on tronque toujours le résultat ce qui entraine un décalage vers le bas. Pour corriger ce problème, on pourrait regarder le bit 14 pour arrondir le résultat au supérieur si besoin. On obtient alors la séquence attendue.
+
### Question filtre 6 : Validez-vous la conception de l’unité opérative ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ?
+
+Oui, nous validons la conception de l'unité opérative.
diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
index 9b342093142bd1b298b4af63bdebdead3a3ef56e..6888edec1ac73923cacb7d6dea38f6663dae769b 100644
--- a/proj/AudioProc.cache/wt/project.wpc
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
index b8773761758f34d8b5dd61a2401844ea43ca2b20..1a42a2d89e01e2084d8a991ec77d5841795fb88a 100644
--- a/proj/AudioProc.cache/wt/synthesis.wdf
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -46,7 +46,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323673:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323638382e3433304d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3938372e3033314d42:00:00
-eof:3242433620
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323773:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323735392e3336334d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313035382e3030304d42:00:00
+eof:2638794961
diff --git a/proj/AudioProc.cache/wt/webtalk_pa.xml b/proj/AudioProc.cache/wt/webtalk_pa.xml
index 7d4cc59770e339b3f9ed7fcdeb596a2aa1f2d1fc..2e42abfcf7237c6e09b30a96037f6d58bd698f8d 100644
--- a/proj/AudioProc.cache/wt/webtalk_pa.xml
+++ b/proj/AudioProc.cache/wt/webtalk_pa.xml
@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri May 9 16:19:02 2025">
+<application name="pa" timeStamp="Mon May 12 16:25:30 2025">
<section name="Project Information" visible="false">
<property name="ProjectID" value="9ccedbccb28842ac935db24e4b881869" type="ProjectID"/>
-<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+<property name="ProjectIteration" value="5" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
index 50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af..51d5206f7011f2f0764fb661278617e58456141a 100644
--- a/proj/AudioProc.cache/wt/xsim.wdf
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -1,4 +1,4 @@
version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:241934075
+eof:2427094519
diff --git a/proj/AudioProc.hw/AudioProc.lpr b/proj/AudioProc.hw/AudioProc.lpr
index afc0a86cf8f820e635f040c3869b4b647d11ec04..aa18adc095c6432a86aa8a7a331502559213b706 100644
--- a/proj/AudioProc.hw/AudioProc.lpr
+++ b/proj/AudioProc.hw/AudioProc.lpr
@@ -4,4 +4,6 @@
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
-<labtools version="1" minor="0"/>
+<labtools version="1" minor="0">
+ <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/proj/AudioProc.hw/hw_1/hw.xml b/proj/AudioProc.hw/hw_1/hw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2cc8b5c9dbf896cee7f203c4cfa2a0fccaedffa0
--- /dev/null
+++ b/proj/AudioProc.hw/hw_1/hw.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<hwsession version="1" minor="2">
+ <device name="xc7a200t_0" gui_info=""/>
+ <ObjectList object_type="hw_device" gui_info="">
+ <Object name="xc7a200t_0" gui_info="">
+ <Properties Property="FULL_PROBES.FILE" value=""/>
+ <Properties Property="PROBES.FILE" value=""/>
+ <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/audioProc.bit"/>
+ <Properties Property="SLR.COUNT" value="1"/>
+ </Object>
+ </ObjectList>
+ <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_2.xml b/proj/AudioProc.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a96c7f415fe045d0b6df23ac51a71d39e478a061
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_3.xml b/proj/AudioProc.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000000000000000000000000000000000000..47a9d4129204dfe276a270df467ed25525192465
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_4.xml b/proj/AudioProc.runs/.jobs/vrs_config_4.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0f551a66f592888afbe338d5dd69f7f74dfd189c
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_5.xml b/proj/AudioProc.runs/.jobs/vrs_config_5.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0f551a66f592888afbe338d5dd69f7f74dfd189c
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_5.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_6.xml b/proj/AudioProc.runs/.jobs/vrs_config_6.xml
new file mode 100644
index 0000000000000000000000000000000000000000..1ce2ce116e1d4a3eb27776487395cb9134c56ff8
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_6.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/impl_1/.init_design.begin.rst b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
index 19be83bfd3b0d239fb70f4175632687390a22faf..5ae90ae5882c26173a6659f41054886959bf89f6 100644
--- a/proj/AudioProc.runs/impl_1/.init_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="m24wang" Host="" Pid="115256">
+ <Process Command=".planAhead." Owner="m24wang" Host="" Pid="128779">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.nfs000000000260aad200000132 b/proj/AudioProc.runs/impl_1/.nfs000000000260aad200000132
new file mode 100644
index 0000000000000000000000000000000000000000..269383e5b60f532df635a536e347160052ddda6e
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs000000000260aad200000132 differ
diff --git a/proj/AudioProc.runs/impl_1/.nfs000000000260ba8900000131 b/proj/AudioProc.runs/impl_1/.nfs000000000260ba8900000131
new file mode 100644
index 0000000000000000000000000000000000000000..9d216b93f6b032f0ee197f9e813c4d4ffed0612c
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs000000000260ba8900000131 differ
diff --git a/proj/AudioProc.runs/impl_1/.nfs000000000260bae100000130 b/proj/AudioProc.runs/impl_1/.nfs000000000260bae100000130
new file mode 100644
index 0000000000000000000000000000000000000000..24d41c558bc16a7d0871a9d0cea264c41d187191
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs000000000260bae100000130 differ
diff --git a/proj/AudioProc.runs/impl_1/.nfs000000000260ef2000000133 b/proj/AudioProc.runs/impl_1/.nfs000000000260ef2000000133
new file mode 100644
index 0000000000000000000000000000000000000000..4883ea72b8d54ef508a91619c0b7cf1e457e8a56
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs000000000260ef2000000133 differ
diff --git a/proj/AudioProc.runs/impl_1/.nfs0000000002616e870000012f b/proj/AudioProc.runs/impl_1/.nfs0000000002616e870000012f
new file mode 100644
index 0000000000000000000000000000000000000000..3fe09b5047018b1c099de143d83fddeda7702cca
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/.nfs0000000002616e870000012f differ
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
index 19be83bfd3b0d239fb70f4175632687390a22faf..5ae90ae5882c26173a6659f41054886959bf89f6 100644
--- a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="m24wang" Host="" Pid="115256">
+ <Process Command=".planAhead." Owner="m24wang" Host="" Pid="128779">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.place_design.begin.rst b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
index 19be83bfd3b0d239fb70f4175632687390a22faf..5ae90ae5882c26173a6659f41054886959bf89f6 100644
--- a/proj/AudioProc.runs/impl_1/.place_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="m24wang" Host="" Pid="115256">
+ <Process Command=".planAhead." Owner="m24wang" Host="" Pid="128779">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.route_design.begin.rst b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
index 19be83bfd3b0d239fb70f4175632687390a22faf..5ae90ae5882c26173a6659f41054886959bf89f6 100644
--- a/proj/AudioProc.runs/impl_1/.route_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="m24wang" Host="" Pid="115256">
+ <Process Command=".planAhead." Owner="m24wang" Host="" Pid="128779">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.vivado.begin.rst b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
index d625b84d08d9193bfc568406cd5ec0245819772b..6909c32ba30093a615ea069d1aebce8dace12a98 100644
--- a/proj/AudioProc.runs/impl_1/.vivado.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
@@ -1,5 +1,20 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="115185" HostCore="12" HostMemory="16146428">
+ <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="95480" HostCore="12" HostMemory="16146432">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="125718" HostCore="12" HostMemory="16146432">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="126614" HostCore="12" HostMemory="16146432">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="128708" HostCore="12" HostMemory="16146432">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
index 19be83bfd3b0d239fb70f4175632687390a22faf..5ae90ae5882c26173a6659f41054886959bf89f6 100644
--- a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="m24wang" Host="" Pid="115256">
+ <Process Command=".planAhead." Owner="m24wang" Host="" Pid="128779">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bin b/proj/AudioProc.runs/impl_1/audioProc.bin
index c82b3e4348f6991d14acfba79b9a58b1355d38ea..bbac862cfb67ca8e735942c402f5d381112dcac5 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc.bin and b/proj/AudioProc.runs/impl_1/audioProc.bin differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bit b/proj/AudioProc.runs/impl_1/audioProc.bit
index 2963bb05c36236fd55fb6d7cdf8cc93046f4c969..ef8bad0243d6c2a2392d0451858ac72fcb600880 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc.bit and b/proj/AudioProc.runs/impl_1/audioProc.bit differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.tcl b/proj/AudioProc.runs/impl_1/audioProc.tcl
index c9c8c78d22e76722d5e2b673e4f32c3c7698fafe..6715c31bc67067c6ee1556282687672a567ac3f5 100644
--- a/proj/AudioProc.runs/impl_1/audioProc.tcl
+++ b/proj/AudioProc.runs/impl_1/audioProc.tcl
@@ -105,7 +105,7 @@ set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param chipscope.maxJobs 3
- set_param runs.launchOptions { -jobs 6 }
+ set_param runs.launchOptions { -jobs 12 }
OPTRACE "create in-memory project" START { }
create_project -in_memory -part xc7a200tsbg484-1
set_property design_mode GateLvl [current_fileset]
diff --git a/proj/AudioProc.runs/impl_1/audioProc.vdi b/proj/AudioProc.runs/impl_1/audioProc.vdi
index 45d31387e112ec3bf0a856ca1f1feebd9147e6c5..b6a68d646f44bf3d8ea8533e503161c921bd5f4a 100644
--- a/proj/AudioProc.runs/impl_1/audioProc.vdi
+++ b/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May 9 16:20:38 2025
-# Process ID: 115256
+# Start of session at: Mon May 12 16:27:04 2025
+# Process ID: 128779
# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1
# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -13,16 +13,16 @@
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4199.706 MHz
+# CPU Frequency :4267.765 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
-# Available Virtual :16974 MB
+# Available Virtual :15208 MB
#-----------------------------------------------------------
source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1680.582 ; gain = 326.840 ; free physical = 6369 ; free virtual = 15615
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.582 ; gain = 326.840 ; free physical = 3938 ; free virtual = 13924
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -33,7 +33,7 @@ Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a200tsbg484-1
INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
INFO: [Project 1-454] Reading design checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2098.465 ; gain = 0.000 ; free physical = 5935 ; free virtual = 15181
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2097.465 ; gain = 0.000 ; free physical = 3534 ; free virtual = 13487
INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.3
@@ -43,20 +43,20 @@ Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etu
Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
INFO: [Timing 38-2] Deriving generated clocks [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
-get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2743.926 ; gain = 548.961 ; free physical = 5350 ; free virtual = 14616
+get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2743.957 ; gain = 551.961 ; free physical = 2976 ; free virtual = 12929
Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/constraints/NexysVideo_Master.xdc]
Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/constraints/NexysVideo_Master.xdc]
INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.dcp'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.926 ; gain = 0.000 ; free physical = 5349 ; free virtual = 14615
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.957 ; gain = 0.000 ; free physical = 2976 ; free virtual = 12929
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 2743.926 ; gain = 1048.500 ; free physical = 5349 ; free virtual = 14615
+link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2743.957 ; gain = 1048.531 ; free physical = 2976 ; free virtual = 12929
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
@@ -67,113 +67,112 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:01 . Memory (MB): peak = 2819.832 ; gain = 75.906 ; free physical = 5327 ; free virtual = 14593
+Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2817.895 ; gain = 73.938 ; free physical = 2949 ; free virtual = 12902
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 3002b507b
+Ending Cache Timing Information Task | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2819.832 ; gain = 0.000 ; free physical = 5327 ; free virtual = 14593
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2817.895 ; gain = 0.000 ; free physical = 2949 ; free virtual = 12902
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 3002b507b
+Phase 1.1 Core Generation And Design Setup | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 3002b507b
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Phase 1 Initialization | Checksum: 3002b507b
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 1 Initialization | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
-Phase 2.1 Timer Update | Checksum: 3002b507b
+Phase 2.1 Timer Update | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 2.2 Timing Data Collection
-Phase 2.2 Timing Data Collection | Checksum: 3002b507b
+Phase 2.2 Timing Data Collection | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Phase 2 Timer Update And Timing Data Collection | Checksum: 3002b507b
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 3 Retarget
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 3002b507b
+Phase 3 Retarget | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Retarget | Checksum: 3002b507b
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Retarget | Checksum: 2e2fef6cb
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 3002b507b
+Phase 4 Constant propagation | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Constant propagation | Checksum: 3002b507b
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Constant propagation | Checksum: 2e2fef6cb
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
-Phase 5 Sweep | Checksum: 26ac40cc4
+Phase 5 Sweep | Checksum: 278026854
-Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Sweep | Checksum: 26ac40cc4
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Sweep | Checksum: 278026854
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 6 BUFG optimization
-INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells
-Phase 6 BUFG optimization | Checksum: 2ceae85f4
+Phase 6 BUFG optimization | Checksum: 278026854
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-BUFG optimization | Checksum: 2ceae85f4
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells.
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+BUFG optimization | Checksum: 278026854
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 2ceae85f4
+Phase 7 Shift Register Optimization | Checksum: 278026854
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Shift Register Optimization | Checksum: 2ceae85f4
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Shift Register Optimization | Checksum: 278026854
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 300494802
+Phase 8 Post Processing Netlist | Checksum: 278026854
-Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Post Processing Netlist | Checksum: 300494802
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Post Processing Netlist | Checksum: 278026854
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 28a25b064
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 28a25b064
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Phase 9 Finalization | Checksum: 28a25b064
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 9 Finalization | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Opt_design Change Summary
=========================
@@ -184,34 +183,34 @@ Opt_design Change Summary
| Retarget | 0 | 0 | 1 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 1 | 0 |
-| BUFG optimization | 0 | 2 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
-Ending Logic Optimization Task | Checksum: 28a25b064
+Ending Logic Optimization Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 28a25b064
+Ending Power Optimization Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 28a25b064
+Ending Final Cleanup Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Ending Netlist Obfuscation Task | Checksum: 28a25b064
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Ending Netlist Obfuscation Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
INFO: [Common 17-83] Releasing license: Implementation
-34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
@@ -220,16 +219,16 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5011 ; free virtual = 14280
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5011 ; free virtual = 14280
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5011 ; free virtual = 14280
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5010 ; free virtual = 14279
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5007 ; free virtual = 14276
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5007 ; free virtual = 14276
-Write Physdb Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5007 ; free virtual = 14276
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2632 ; free virtual = 12585
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2632 ; free virtual = 12585
+Write Physdb Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2632 ; free virtual = 12585
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -249,59 +248,59 @@ Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4971 ; free virtual = 14250
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1971e65b5
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2505 ; free virtual = 12458
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 27ecc6cee
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4971 ; free virtual = 14250
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4971 ; free virtual = 14250
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2505 ; free virtual = 12458
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2505 ; free virtual = 12458
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d834e537
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 167eef5db
-Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.49 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4964 ; free virtual = 14246
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2497 ; free virtual = 12450
Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 24479b66e
+Phase 1.3 Build Placer Netlist Model | Checksum: 22978800d
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4962 ; free virtual = 14245
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2487 ; free virtual = 12440
Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 24479b66e
+Phase 1.4 Constrain Clocks/Macros | Checksum: 22978800d
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4962 ; free virtual = 14245
-Phase 1 Placer Initialization | Checksum: 24479b66e
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2487 ; free virtual = 12440
+Phase 1 Placer Initialization | Checksum: 22978800d
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.84 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4961 ; free virtual = 14245
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2487 ; free virtual = 12440
Phase 2 Global Placement
Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1f0769a16
+Phase 2.1 Floorplanning | Checksum: 224a3efaa
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.95 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4988 ; free virtual = 14272
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2486 ; free virtual = 12439
Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2d5cde647
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 16f59aef9
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 5009 ; free virtual = 14292
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2538 ; free virtual = 12491
Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2d5cde647
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 16f59aef9
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 5009 ; free virtual = 14292
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2538 ; free virtual = 12491
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
-Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 24e71af8c
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e559c04f
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3234.477 ; gain = 20.031 ; free physical = 5007 ; free virtual = 14283
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3233.539 ; gain = 21.031 ; free physical = 2522 ; free virtual = 12475
Phase 2.4.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 96 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 90 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 44 nets or LUTs. Breaked 0 LUT, combined 44 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 43 nets or LUTs. Breaked 0 LUT, combined 43 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
@@ -312,7 +311,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3234.477 ; gain = 0.000 ; free physical = 4980 ; free virtual = 14279
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3233.539 ; gain = 0.000 ; free physical = 2535 ; free virtual = 12488
Summary of Physical Synthesis Optimizations
============================================
@@ -321,7 +320,7 @@ Summary of Physical Synthesis Optimizations
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 44 | 44 | 0 | 1 | 00:00:00 |
+| LUT Combining | 0 | 43 | 43 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
@@ -330,59 +329,59 @@ Summary of Physical Synthesis Optimizations
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 44 | 44 | 0 | 4 | 00:00:00 |
+| Total | 0 | 43 | 43 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2d955f418
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 26385cb9f
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4980 ; free virtual = 14279
-Phase 2.4 Global Placement Core | Checksum: 24d73e065
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
+Phase 2.4 Global Placement Core | Checksum: 264b89dc8
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4971 ; free virtual = 14265
-Phase 2 Global Placement | Checksum: 24d73e065
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
+Phase 2 Global Placement | Checksum: 264b89dc8
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4971 ; free virtual = 14265
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 23d657603
+Phase 3.1 Commit Multi Column Macros | Checksum: 23022f2f1
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4963 ; free virtual = 14264
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22513e1c8
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c797472b
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4962 ; free virtual = 14264
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2534 ; free virtual = 12487
Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 1ea1af04a
+Phase 3.3 Area Swap Optimization | Checksum: 26d02ebbb
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4962 ; free virtual = 14264
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2534 ; free virtual = 12487
Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 178715a17
+Phase 3.4 Pipeline Register Optimization | Checksum: 1f51d677c
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4962 ; free virtual = 14264
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2534 ; free virtual = 12487
Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 2d4f2065c
+Phase 3.5 Small Shape Detail Placement | Checksum: 2a343d387
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4913 ; free virtual = 14235
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2490 ; free virtual = 12443
Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1f22d608d
+Phase 3.6 Re-assign LUT pins | Checksum: 26349eaea
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4905 ; free virtual = 14228
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2490 ; free virtual = 12443
Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 146f8e4d1
+Phase 3.7 Pipeline Register Optimization | Checksum: 214e05132
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4905 ; free virtual = 14228
-Phase 3 Detail Placement | Checksum: 146f8e4d1
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2490 ; free virtual = 12443
+Phase 3 Detail Placement | Checksum: 214e05132
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4905 ; free virtual = 14228
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2482 ; free virtual = 12435
Phase 4 Post Placement Optimization and Clean-Up
@@ -390,7 +389,7 @@ Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 236af2095
+Post Placement Optimization Initialization | Checksum: 1f3d6a612
Phase 4.1.1.1 BUFG Insertion
@@ -398,33 +397,33 @@ Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.794 | TNS=0.000 |
-Phase 1 Physical Synthesis Initialization | Checksum: 27a123550
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.890 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 200ae2f51
-Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4897 ; free virtual = 14215
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2474 ; free virtual = 12427
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 239910472
+Ending Physical Synthesis Task | Checksum: 2858bbf4e
-Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4897 ; free virtual = 14215
-Phase 4.1.1.1 BUFG Insertion | Checksum: 236af2095
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2474 ; free virtual = 12427
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1f3d6a612
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4896 ; free virtual = 14214
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2474 ; free virtual = 12427
Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.794. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 242e1e100
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.890. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2728a29e4
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2474 ; free virtual = 12427
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Phase 4.1 Post Commit Optimization | Checksum: 242e1e100
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2474 ; free virtual = 12427
+Phase 4.1 Post Commit Optimization | Checksum: 2728a29e4
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 242e1e100
+Phase 4.2 Post Placement Cleanup | Checksum: 2728a29e4
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
Phase 4.3 Placer Reporting
@@ -443,44 +442,43 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
| West| 1x1| 1x1|
|___________|___________________|___________________|
-Phase 4.3.1 Print Estimated Congestion | Checksum: 242e1e100
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2728a29e4
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Phase 4.3 Placer Reporting | Checksum: 242e1e100
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+Phase 4.3 Placer Reporting | Checksum: 2728a29e4
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4891 ; free virtual = 14209
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2466 ; free virtual = 12419
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c155315a
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 285157fe1
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Ending Placer Task | Checksum: c4fd0a1d
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+Ending Placer Task | Checksum: 1c42333b7
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-69 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
-place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3244.285 ; gain = 63.625 ; free physical = 4891 ; free virtual = 14209
INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
Running report generation with 3 threads.
INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4872 ; free virtual = 14193
+report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2452 ; free virtual = 12405
INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4848 ; free virtual = 14173
+report_io: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2443 ; free virtual = 12396
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4840 ; free virtual = 14169
-Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4834 ; free virtual = 14164
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14165
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2434 ; free virtual = 12387
+Wrote PlaceDB: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2434 ; free virtual = 12388
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12388
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
-Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12388
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12388
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12389
+Write Physdb Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12389
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -495,122 +493,116 @@ Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
-Checksum: PlaceDB: 17894a90 ConstDB: 0 ShapeSum: 1558d429 RouteDB: 981aeb64
-Post Restoration Checksum: NetGraph: a8773583 | NumContArr: fe331ce0 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 32bfc479d
+Checksum: PlaceDB: 2f016cf1 ConstDB: 0 ShapeSum: fd06db62 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 6f0615b9 | NumContArr: 99ab826b | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 28e038d5e
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 3434.043 ; gain = 168.945 ; free physical = 4726 ; free virtual = 14008
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 3432.137 ; gain = 166.945 ; free physical = 2328 ; free virtual = 12283
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 32bfc479d
+Phase 2.1 Fix Topology Constraints | Checksum: 28e038d5e
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 3434.043 ; gain = 168.945 ; free physical = 4718 ; free virtual = 14002
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 3432.137 ; gain = 166.945 ; free physical = 2328 ; free virtual = 12283
Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 32bfc479d
+Phase 2.2 Pre Route Cleanup | Checksum: 28e038d5e
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 3434.043 ; gain = 168.945 ; free physical = 4718 ; free virtual = 14002
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 3432.137 ; gain = 166.945 ; free physical = 2328 ; free virtual = 12283
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 2d1d4910a
+Phase 2.3 Update Timing | Checksum: 19e4dbff3
-Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 3501.801 ; gain = 236.703 ; free physical = 4649 ; free virtual = 13934
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.803 | TNS=0.000 | WHS=-0.144 | THS=-22.944|
+Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 3499.895 ; gain = 234.703 ; free physical = 2259 ; free virtual = 12213
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.910 | TNS=0.000 | WHS=-0.148 | THS=-25.785|
Router Utilization Summary
- Global Vertical Routing Utilization = 0.000182205 %
+ Global Vertical Routing Utilization = 0.00020245 %
Global Horizontal Routing Utilization = 0.000165235 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
- Number of Failed Nets = 1211
+ Number of Failed Nets = 1206
(Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 1201
+ Number of Unrouted Nets = 1196
Number of Partially Routed Nets = 10
Number of Node Overlaps = 11
-Phase 2 Router Initialization | Checksum: 269f51fe2
+Phase 2 Router Initialization | Checksum: 22e8cf3f2
-Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 269f51fe2
+Phase 3 Global Routing | Checksum: 22e8cf3f2
-Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
Phase 4 Initial Routing
Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 2c245566f
+Phase 4.1 Initial Net Routing Pass | Checksum: 2b7538a3c
-Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
-Phase 4 Initial Routing | Checksum: 2c245566f
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
+Phase 4 Initial Routing | Checksum: 2b7538a3c
-Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
Phase 5 Rip-up And Reroute
Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 238
- Number of Nodes with overlaps = 126
- Number of Nodes with overlaps = 68
+ Number of Nodes with overlaps = 217
+ Number of Nodes with overlaps = 106
+ Number of Nodes with overlaps = 62
Number of Nodes with overlaps = 32
- Number of Nodes with overlaps = 10
- Number of Nodes with overlaps = 6
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 19
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.534 | TNS=0.000 | WHS=N/A | THS=N/A |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.650 | TNS=0.000 | WHS=N/A | THS=N/A |
-Phase 5.1 Global Iteration 0 | Checksum: 2abe36016
+Phase 5.1 Global Iteration 0 | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-Phase 5 Rip-up And Reroute | Checksum: 2abe36016
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Phase 5 Rip-up And Reroute | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 6 Delay and Skew Optimization
Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 35ff68537
-Phase 6.1.1 Update Timing
-Phase 6.1.1 Update Timing | Checksum: 2efa28e2c
-
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613 | TNS=0.000 | WHS=N/A | THS=N/A |
-
-Phase 6.1 Delay CleanUp | Checksum: 2efa28e2c
-
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 2efa28e2c
+Phase 6.2 Clock Skew Optimization | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-Phase 6 Delay and Skew Optimization | Checksum: 2efa28e2c
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Phase 6 Delay and Skew Optimization | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 7 Post Hold Fix
Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613 | TNS=0.000 | WHS=0.107 | THS=0.000 |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.729 | TNS=0.000 | WHS=0.049 | THS=0.000 |
-Phase 7.1 Hold Fix Iter | Checksum: 2486ccefa
+Phase 7.1 Hold Fix Iter | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-Phase 7 Post Hold Fix | Checksum: 2486ccefa
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Phase 7 Post Hold Fix | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 8 Route finalize
Router Utilization Summary
- Global Vertical Routing Utilization = 0.0942403 %
- Global Horizontal Routing Utilization = 0.118209 %
+ Global Vertical Routing Utilization = 0.0982691 %
+ Global Horizontal Routing Utilization = 0.114871 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -620,50 +612,50 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
-Phase 8 Route finalize | Checksum: 2486ccefa
+Phase 8 Route finalize | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 9 Verifying routed nets
Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2486ccefa
+Phase 9 Verifying routed nets | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 16786fc76
+Phase 10 Depositing Routes | Checksum: 3780a9066
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 16786fc76
+Phase 11 Post Process Routing | Checksum: 3780a9066
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.613 | TNS=0.000 | WHS=0.107 | THS=0.000 |
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.729 | TNS=0.000 | WHS=0.049 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 16786fc76
+Phase 12 Post Router Timing | Checksum: 3780a9066
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
-Total Elapsed time in route_design: 35.78 secs
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Total Elapsed time in route_design: 33.94 secs
Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: d2e3295b
+Phase 13 Post-Route Event Processing | Checksum: 23c536cd6
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: d2e3295b
+Ending Routing Task | Checksum: 23c536cd6
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
-88 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+86 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:37 . Memory (MB): peak = 3509.191 ; gain = 252.098 ; free physical = 4646 ; free virtual = 13929
+route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3507.285 ; gain = 250.098 ; free physical = 2257 ; free virtual = 12212
INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -693,22 +685,22 @@ Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summa
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
-108 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+106 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
WARNING: [Device 21-2174] Failed to initialize Virtual grid.
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4604 ; free virtual = 13917
-Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4603 ; free virtual = 13917
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12211
+Wrote PlaceDB: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12212
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12212
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
-Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4600 ; free virtual = 13919
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12212
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12213
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12213
+Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.3 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12213
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
Command: write_bitstream -force audioProc.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -735,8 +727,8 @@ WARNING: [DRC DPOP-1] PREG Output pipelining: DSP leftFir/firUnit_1/operativeUni
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult output rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP leftFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
-WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
@@ -750,7 +742,7 @@ Writing bitstream ./audioProc.bit...
Writing bitstream ./audioProc.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
-119 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
+117 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3851.027 ; gain = 253.793 ; free physical = 4280 ; free virtual = 13588
-INFO: [Common 17-206] Exiting Vivado at Fri May 9 16:22:48 2025...
+write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3851.090 ; gain = 255.762 ; free physical = 1873 ; free virtual = 11848
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:29:09 2025...
diff --git a/proj/AudioProc.runs/impl_1/audioProc_95553.backup.vdi b/proj/AudioProc.runs/impl_1/audioProc_95553.backup.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..0a2aa02698f64458b511430e680074c17fcb3b40
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_95553.backup.vdi
@@ -0,0 +1,709 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 16:07:38 2025
+# Process ID: 95553
+# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-520
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4197.958 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :16521 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1680.582 ; gain = 325.840 ; free physical = 5244 ; free virtual = 15146
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2097.465 ; gain = 0.000 ; free physical = 4829 ; free virtual = 14731
+INFO: [Netlist 29-17] Analyzing 113 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2743.926 ; gain = 540.961 ; free physical = 4246 ; free virtual = 14167
+Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.926 ; gain = 0.000 ; free physical = 4246 ; free virtual = 14167
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2743.926 ; gain = 1048.500 ; free physical = 4246 ; free virtual = 14167
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2819.832 ; gain = 75.906 ; free physical = 4209 ; free virtual = 14130
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2819.832 ; gain = 0.000 ; free physical = 4209 ; free virtual = 14130
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Phase 1 Initialization | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Retarget | Checksum: 2426d7b49
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 2426d7b49
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Constant propagation | Checksum: 2426d7b49
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 23d390c90
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Sweep | Checksum: 23d390c90
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 23d390c90
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+BUFG optimization | Checksum: 23d390c90
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 23d390c90
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Shift Register Optimization | Checksum: 23d390c90
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 23d390c90
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Post Processing Netlist | Checksum: 23d390c90
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Phase 9 Finalization | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+Ending Netlist Obfuscation Task | Checksum: 285eca0a6
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.590 ; gain = 0.000 ; free physical = 3906 ; free virtual = 13828
+INFO: [Common 17-83] Releasing license: Implementation
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3896 ; free virtual = 13820
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3896 ; free virtual = 13820
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3896 ; free virtual = 13820
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3890 ; free virtual = 13814
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3890 ; free virtual = 13814
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3890 ; free virtual = 13814
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3187.402 ; gain = 0.000 ; free physical = 3887 ; free virtual = 13812
+INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.383 ; gain = 0.000 ; free physical = 3883 ; free virtual = 13808
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 21cd87339
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3214.383 ; gain = 0.000 ; free physical = 3883 ; free virtual = 13808
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.383 ; gain = 0.000 ; free physical = 3883 ; free virtual = 13808
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1f8f14d7d
+
+Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3214.383 ; gain = 0.000 ; free physical = 3880 ; free virtual = 13808
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 299a6df38
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3221.410 ; gain = 7.027 ; free physical = 3880 ; free virtual = 13809
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 299a6df38
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3221.410 ; gain = 7.027 ; free physical = 3880 ; free virtual = 13809
+Phase 1 Placer Initialization | Checksum: 299a6df38
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3221.410 ; gain = 7.027 ; free physical = 3879 ; free virtual = 13808
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 22e45fa48
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3221.410 ; gain = 7.027 ; free physical = 3871 ; free virtual = 13801
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 25a979b84
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3221.410 ; gain = 7.027 ; free physical = 3906 ; free virtual = 13836
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 25a979b84
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3221.410 ; gain = 7.027 ; free physical = 3906 ; free virtual = 13836
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1f1e4ad48
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3230.414 ; gain = 16.031 ; free physical = 3886 ; free virtual = 13816
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 90 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 43 nets or LUTs. Breaked 0 LUT, combined 43 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3230.414 ; gain = 0.000 ; free physical = 3882 ; free virtual = 13814
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 43 | 43 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 43 | 43 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2ad4418b4
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3882 ; free virtual = 13814
+Phase 2.4 Global Placement Core | Checksum: 2c292c0ff
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3881 ; free virtual = 13814
+Phase 2 Global Placement | Checksum: 2c292c0ff
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3881 ; free virtual = 13814
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 268373d6a
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3880 ; free virtual = 13813
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 351694d6e
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3879 ; free virtual = 13812
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 358b46be5
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3879 ; free virtual = 13812
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2882c1e10
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3879 ; free virtual = 13812
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 29f91ad23
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3869 ; free virtual = 13803
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 27e5afb78
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3869 ; free virtual = 13803
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 3006b824b
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3869 ; free virtual = 13803
+Phase 3 Detail Placement | Checksum: 3006b824b
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3869 ; free virtual = 13803
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 22e7573a8
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.534 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 1613a6306
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3869 ; free virtual = 13803
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 281f8560c
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3869 ; free virtual = 13803
+Phase 4.1.1.1 BUFG Insertion | Checksum: 22e7573a8
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3869 ; free virtual = 13803
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=1.534. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 26a682312
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+Phase 4.1 Post Commit Optimization | Checksum: 26a682312
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 26a682312
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 26a682312
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+Phase 4.3 Placer Reporting | Checksum: 26a682312
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3868 ; free virtual = 13802
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 222e61a2f
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+Ending Placer Task | Checksum: 1d1621fbc
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3242.254 ; gain = 27.871 ; free physical = 3868 ; free virtual = 13802
+68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 3242.254 ; gain = 54.852 ; free physical = 3868 ; free virtual = 13802
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3857 ; free virtual = 13790
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3856 ; free virtual = 13789
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3856 ; free virtual = 13789
+Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3855 ; free virtual = 13789
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3853 ; free virtual = 13788
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3853 ; free virtual = 13788
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3853 ; free virtual = 13789
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3853 ; free virtual = 13789
+Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3242.254 ; gain = 0.000 ; free physical = 3853 ; free virtual = 13788
+INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 9e3452ab ConstDB: 0 ShapeSum: 9b12e1ad RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 56e097cb | NumContArr: 5e2f90ef | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 23a621df4
+
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 3431.012 ; gain = 165.945 ; free physical = 3610 ; free virtual = 13547
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 23a621df4
+
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 3431.012 ; gain = 165.945 ; free physical = 3603 ; free virtual = 13540
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 23a621df4
+
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 3431.012 ; gain = 165.945 ; free physical = 3603 ; free virtual = 13540
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 2a5ed5860
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3499.770 ; gain = 234.703 ; free physical = 3540 ; free virtual = 13478
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.611 | TNS=0.000 | WHS=-0.148 | THS=-24.878|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.000263185 %
+ Global Horizontal Routing Utilization = 0.000660939 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 1198
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 1188
+ Number of Partially Routed Nets = 10
+ Number of Node Overlaps = 9
+
+Phase 2 Router Initialization | Checksum: 2820d5cfb
+
+Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3533 ; free virtual = 13471
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 2820d5cfb
+
+Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3533 ; free virtual = 13471
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 2316cad4c
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3533 ; free virtual = 13471
+Phase 4 Initial Routing | Checksum: 2316cad4c
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3533 ; free virtual = 13471
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 139
+ Number of Nodes with overlaps = 32
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.216 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 264e8fad6
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+Phase 5 Rip-up And Reroute | Checksum: 264e8fad6
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 34063f566
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.295 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 6.1 Delay CleanUp | Checksum: 34063f566
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 34063f566
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+Phase 6 Delay and Skew Optimization | Checksum: 34063f566
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.295 | TNS=0.000 | WHS=0.102 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 2b9192298
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+Phase 7 Post Hold Fix | Checksum: 2b9192298
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0887944 %
+ Global Horizontal Routing Utilization = 0.113087 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 2b9192298
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 2b9192298
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 2ea9cee13
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 2ea9cee13
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=1.295 | TNS=0.000 | WHS=0.102 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 2ea9cee13
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+Total Elapsed time in route_design: 33.46 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 1e4f0bce2
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 1e4f0bce2
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3507.160 ; gain = 242.094 ; free physical = 3534 ; free virtual = 13472
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+87 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.160 ; gain = 250.098 ; free physical = 3534 ; free virtual = 13472
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+107 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3538 ; free virtual = 13478
+Wrote PlaceDB: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3536 ; free virtual = 13477
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3536 ; free virtual = 13477
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3536 ; free virtual = 13477
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3536 ; free virtual = 13478
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3536 ; free virtual = 13478
+Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3595.203 ; gain = 0.000 ; free physical = 3536 ; free virtual = 13478
+INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:09:38 2025...
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
index 3d55071ee158637be68e51b314213049ae407cab..792be74d58ee6f21a2b0102232be207bb2e8e2db 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:22:31 2025
+| Date : Mon May 12 16:28:53 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
| Design : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx
index ef4cb0820cb99d6d5dd7158dfadccb6ca28d396f..a4c721c77122664a969d447fb318b992ed8bdf76 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
index 1209fd13d944e9e1c94776f4750e2ec8f0c2a0c4..d4d7daec63ceba6d6d1ad262a6dd68d3a299e59c 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:22:32 2025
+| Date : Mon May 12 16:28:54 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
| Design : audioProc
@@ -23,7 +23,8 @@ Table of Contents
7. Device Cell Placement Summary for Global Clock g1
8. Device Cell Placement Summary for Global Clock g2
9. Device Cell Placement Summary for Global Clock g3
-10. Clock Region Cell Placement per Global Clock: Region X1Y2
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+11. Clock Region Cell Placement per Global Clock: Region X1Y2
1. Clock Primitive Utilization
------------------------------
@@ -47,7 +48,7 @@ Table of Contents
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
-| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 773 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1 |
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 2 | 773 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1 |
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 1 | 120 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/clkout4_buf/O | clk_1/inst/clk_out4 |
| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/clkf_buf/O | clk_1/inst/clkfbout_buf_clk_wiz_0 |
| g3 | src3 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 0 | 1 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/clkout3_buf/O | clk_1/inst/clk_out3 |
@@ -82,9 +83,9 @@ Table of Contents
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
-| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 239 | 4000 | 101 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
-| X1Y2 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 893 | 4000 | 343 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X1Y2 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 654 | 4000 | 259 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
@@ -127,8 +128,8 @@ All Modules
+----+----+------+-----------------------+
| Y4 | 0 | 0 | - |
| Y3 | 0 | 0 | - |
-| Y2 | 0 | 773 | 0 |
-| Y1 | 0 | 0 | - |
+| Y2 | 0 | 534 | 0 |
+| Y1 | 0 | 239 | 0 |
| Y0 | 0 | 0 | - |
+----+----+------+-----------------------+
@@ -208,13 +209,26 @@ All Modules
+----+----+----+-----------------------+
-10. Clock Region Cell Placement per Global Clock: Region X1Y2
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------------+
+| g0 | n/a | BUFG/O | None | 239 | 0 | 239 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+---------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+11. Clock Region Cell Placement per Global Clock: Region X1Y2
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
-| g0 | n/a | BUFG/O | None | 773 | 0 | 773 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
+| g0 | n/a | BUFG/O | None | 534 | 0 | 534 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
| g1 | n/a | BUFG/O | None | 120 | 0 | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
| g3 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out3 |
@@ -248,5 +262,5 @@ resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] -add {CLOCKREGION_X1Y2:C
#startgroup
create_pblock {CLKAG_clk_1/inst/clk_out1}
add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out1"}]]]
-resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup
diff --git a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
index 74000412fdf476aa51d159de6b3d7a179178aeea..9084591a7d544891396427394a5efdcd65c3fe54 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:21:52 2025
+| Date : Mon May 12 16:28:15 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
| Design : audioProc
@@ -23,11 +23,11 @@ Table of Contents
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
-| Total control sets | 32 |
-| Minimum number of control sets | 32 |
+| Total control sets | 30 |
+| Minimum number of control sets | 30 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
-| Unused register locations in slices containing registers | 81 |
+| Unused register locations in slices containing registers | 65 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
@@ -39,9 +39,9 @@ Table of Contents
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
-| Total control sets | 32 |
+| Total control sets | 30 |
| >= 0 to < 4 | 1 |
-| >= 4 to < 6 | 10 |
+| >= 4 to < 6 | 8 |
| >= 6 to < 8 | 5 |
| >= 8 to < 10 | 1 |
| >= 10 to < 12 | 1 |
@@ -58,11 +58,11 @@ Table of Contents
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
-| No | No | No | 34 | 19 |
-| No | No | Yes | 10 | 2 |
+| No | No | No | 34 | 17 |
+| No | No | Yes | 10 | 3 |
| No | Yes | No | 44 | 14 |
-| Yes | No | No | 67 | 23 |
-| Yes | No | Yes | 624 | 156 |
+| Yes | No | No | 67 | 27 |
+| Yes | No | Yes | 624 | 164 |
| Yes | Yes | No | 124 | 36 |
+--------------+-----------------------+------------------------+-----------------+--------------+
@@ -70,41 +70,39 @@ Table of Contents
4. Detailed Control Set Information
-----------------------------------
-+------------------------------------------------+--------------------------------------------------------------+---------------------------------------------------+------------------+----------------+--------------+
-| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
-+------------------------------------------------+--------------------------------------------------------------+---------------------------------------------------+------------------+----------------+--------------+
-| clk_1/inst/clk_out1 | dbuttons/IV[2]_i_1_n_0 | | 1 | 1 | 1.00 |
-| clk_1/inst/clk_out1 | leftFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0 | audio_inout/SR[0] | 1 | 4 | 4.00 |
-| clk_1/inst/clk_out4 | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0 | | 2 | 4 | 2.00 |
-| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[5]_i_1_n_0 | 2 | 4 | 2.00 |
-| clk_1/inst/clk_out1 | rightFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0 | audio_inout/SR[0] | 1 | 4 | 4.00 |
-| clk_1/inst/clk_out4 | initialize_audio/twi_controller/E[0] | audio_inout/SR[0] | 2 | 4 | 2.00 |
-| clk_1/inst/clk_out1 | lrclkcnt[3]_i_2_n_0 | lrclkcnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
-| rightFir/firUnit_1/controlUnit_1/SR_nextState | | | 2 | 5 | 2.50 |
-| clk_1/inst/clk_out1 | | audio_inout/Cnt_Bclk[4]_i_1_n_0 | 2 | 5 | 2.50 |
-| leftFir/firUnit_1/controlUnit_1/SR_nextState | | | 2 | 5 | 2.50 |
-| clk_1/inst/clk_out1 | audio_inout/BCLK_Fall_int | audio_inout/SR[0] | 2 | 5 | 2.50 |
-| clk_1/inst/clk_out1 | | | 3 | 6 | 2.00 |
-| clk_1/inst/clk_out4 | rstn_IBUF | | 2 | 6 | 3.00 |
-| clk_1/inst/clk_out4 | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0 | initialize_audio/twi_controller/sclCnt[6]_i_1_n_0 | 3 | 7 | 2.33 |
-| clk_1/inst/clk_out4 | initialize_audio/twi_controller/state_reg[3][0] | audio_inout/SR[0] | 3 | 7 | 2.33 |
-| clk_1/inst/clk_out4 | | initialize_audio/twi_controller/busFreeCnt0 | 3 | 7 | 2.33 |
-| clk_1/inst/clk_out4 | initialize_audio/twi_controller/dataByte[7]_i_1_n_0 | | 3 | 8 | 2.67 |
-| clk_1/inst/clk_out1 | | audio_inout/SR[0] | 2 | 10 | 5.00 |
-| clk_1/inst/clk_out1 | dbuttons/cnt2 | dbuttons/cnt2[12]_i_1_n_0 | 4 | 13 | 3.25 |
-| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[2] | audio_inout/SR[0] | 4 | 16 | 4.00 |
-| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[2] | audio_inout/SR[0] | 4 | 16 | 4.00 |
-| clk_1/inst/clk_out4 | | | 12 | 18 | 1.50 |
-| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | | 5 | 23 | 4.60 |
-| clk_1/inst/clk_out1 | audio_inout/D_R_O_int[23]_i_1_n_0 | audio_inout/SR[0] | 5 | 24 | 4.80 |
-| clk_1/inst/clk_out1 | audio_inout/D_L_O_int | audio_inout/SR[0] | 6 | 24 | 4.00 |
-| clk_1/inst/clk_out1 | audio_inout/Data_Out_int[31]_i_1_n_0 | | 10 | 25 | 2.50 |
-| clk_1/inst/clk_out1 | audio_inout/p_4_in | audio_inout/Data_In_int[31]_i_1_n_0 | 7 | 32 | 4.57 |
-| clk_1/inst/clk_out4 | | initialize_audio/delaycnt0 | 9 | 32 | 3.56 |
-| clk_1/inst/clk_out1 | rightFir/firUnit_1/operativeUnit_1/SR_sum[35]_i_1_n_0 | audio_inout/SR[0] | 9 | 36 | 4.00 |
-| clk_1/inst/clk_out1 | leftFir/firUnit_1/operativeUnit_1/SR_sum[35]_i_1_n_0 | audio_inout/SR[0] | 13 | 36 | 2.77 |
-| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[0] | audio_inout/SR[0] | 59 | 256 | 4.34 |
-| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[0] | audio_inout/SR[0] | 65 | 256 | 3.94 |
-+------------------------------------------------+--------------------------------------------------------------+---------------------------------------------------+------------------+----------------+--------------+
++------------------------------------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++------------------------------------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| clk_1/inst/clk_out1 | dbuttons/IV[2]_i_1_n_0 | | 1 | 1 | 1.00 |
+| clk_1/inst/clk_out1 | lrclkcnt[3]_i_2_n_0 | lrclkcnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0 | | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[5]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out1 | audio_inout/BCLK_Fall_int | rightFir/firUnit_1/operativeUnit_1/AR[0] | 2 | 5 | 2.50 |
+| rightFir/firUnit_1/controlUnit_1/SR_nextState | | | 2 | 5 | 2.50 |
+| leftFir/firUnit_1/controlUnit_1/SR_nextState | | | 3 | 5 | 1.67 |
+| clk_1/inst/clk_out1 | | audio_inout/Cnt_Bclk[4]_i_1_n_0 | 2 | 5 | 2.50 |
+| clk_1/inst/clk_out4 | rstn_IBUF | | 5 | 6 | 1.20 |
+| clk_1/inst/clk_out1 | | | 3 | 6 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0 | initialize_audio/twi_controller/sclCnt0 | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/state_reg[3][0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | | initialize_audio/twi_controller/busFreeCnt0 | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/dataByte[7]_i_1_n_0 | | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out1 | | rightFir/firUnit_1/operativeUnit_1/AR[0] | 3 | 10 | 3.33 |
+| clk_1/inst/clk_out1 | dbuttons/cnt2 | dbuttons/cnt2[12]_i_1_n_0 | 4 | 13 | 3.25 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[2] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 4 | 16 | 4.00 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[2] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 4 | 16 | 4.00 |
+| clk_1/inst/clk_out4 | | | 9 | 18 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | | 6 | 23 | 3.83 |
+| clk_1/inst/clk_out1 | audio_inout/D_L_O_int | rightFir/firUnit_1/operativeUnit_1/AR[0] | 5 | 24 | 4.80 |
+| clk_1/inst/clk_out1 | audio_inout/D_R_O_int[23]_i_1_n_0 | rightFir/firUnit_1/operativeUnit_1/AR[0] | 7 | 24 | 3.43 |
+| clk_1/inst/clk_out1 | audio_inout/Data_Out_int[31]_i_1_n_0 | | 10 | 25 | 2.50 |
+| clk_1/inst/clk_out4 | | initialize_audio/delaycnt0 | 9 | 32 | 3.56 |
+| clk_1/inst/clk_out1 | audio_inout/p_4_in | audio_inout/Data_In_int[31]_i_1_n_0 | 6 | 32 | 5.33 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 13 | 40 | 3.08 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 12 | 40 | 3.33 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 64 | 256 | 4.00 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 67 | 256 | 3.82 |
++------------------------------------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
index ac90dc6bc60eda35b9470849b78892e6701c1aad..0652c45d91b15cf79fce1deb500d071efbe7d50e 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:21:44 2025
+| Date : Mon May 12 16:28:10 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
| Design : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx
index 272d1197018cd04bb9ee4f3d35246d179bad3d3a..c2ca5990d943a075e51a8d1ed7354902f68076d4 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
index 95a53c882d314ed3e067cdfd0d44ce9f975400a2..b5e1d4fe8e113c10d75d3e893b290f8a600f211a 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:22:30 2025
+| Date : Mon May 12 16:28:52 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
| Design : audioProc
@@ -102,12 +102,12 @@ Related violations: <none>
PDRC-153#1 Warning
Gated clock check
-Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>
PDRC-153#2 Warning
Gated clock check
-Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx
index 08c9b5d27b624947b73cc95a477237ad4b99bf41..71517212ddbe3ed01c5599e8b59cd5968ee6fa4f 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
index b7b08c972688a6b6be34ddf650b6c6eb36a25f9c..d95ac970a472e433d24cd2006201ee07b0ce2f44 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:21:52 2025
+| Date : Mon May 12 16:28:15 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_io -file audioProc_io_placed.rpt
| Design : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
index 12335645c07c45ecccc063c343005099e1dc9dd2..b06cd0d8d179e73095d00884993c4dd06cfb6b7f 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:22:31 2025
+| Date : Mon May 12 16:28:53 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
| Design : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx
index b9b9451440f43d5ba7cd64f0662f9bef25c503f6..c1eb828cba5251676d748e73326178da7ce9aa83 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp
index c694a7d380c8b1ff6dfb3ce32800b37e4d58d9b6..bd745c76fc21e87057b03efcb3560f55be8deac5 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp and b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp
index 53079db41f35d9e49b332dcb2f6cfd98d6a6cea1..4614d1c94da3c653b434e54b3f5b6b794a09118f 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp and b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
index e343da479d46faaf2d24d08d4aab4743f01af9ea..7c32a0a4a40071864074fe2a84b493e1a079147e 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:22:32 2025
+| Date : Mon May 12 16:28:53 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
| Design : audioProc
@@ -30,10 +30,10 @@ Table of Contents
----------
+--------------------------+--------------+
-| Total On-Chip Power (W) | 0.251 |
+| Total On-Chip Power (W) | 0.252 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
-| Dynamic (W) | 0.099 |
+| Dynamic (W) | 0.100 |
| Device Static (W) | 0.151 |
| Effective TJA (C/W) | 3.3 |
| Max Ambient (C) | 84.2 |
@@ -52,19 +52,19 @@ Table of Contents
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
-| Clocks | 0.003 | 7 | --- | --- |
-| Slice Logic | 0.001 | 1617 | --- | --- |
-| LUT as Logic | <0.001 | 531 | 133800 | 0.40 |
+| Clocks | 0.004 | 7 | --- | --- |
+| Slice Logic | <0.001 | 1612 | --- | --- |
+| LUT as Logic | <0.001 | 525 | 133800 | 0.39 |
| CARRY4 | <0.001 | 20 | 33450 | 0.06 |
| Register | <0.001 | 903 | 267600 | 0.34 |
| F7/F8 Muxes | <0.001 | 96 | 133800 | 0.07 |
-| Others | 0.000 | 23 | --- | --- |
-| Signals | 0.001 | 1213 | --- | --- |
+| Others | 0.000 | 25 | --- | --- |
+| Signals | 0.001 | 1208 | --- | --- |
| MMCM | 0.085 | 1 | 10 | 10.00 |
| DSPs | 0.002 | 2 | 740 | 0.27 |
| I/O | 0.007 | 22 | 285 | 7.72 |
| Static Power | 0.151 | | | |
-| Total | 0.251 | | | |
+| Total | 0.252 | | | |
+----------------+-----------+----------+-----------+-----------------+
@@ -74,7 +74,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Vccint | 1.000 | 0.039 | 0.008 | 0.031 | NA | Unspecified | NA |
+| Vccint | 1.000 | 0.040 | 0.009 | 0.031 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.078 | 0.047 | 0.031 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
@@ -147,15 +147,15 @@ Table of Contents
+-----------------------+-----------+
| Name | Power (W) |
+-----------------------+-----------+
-| audioProc | 0.099 |
+| audioProc | 0.100 |
| clk_1 | 0.086 |
| inst | 0.086 |
-| leftFir | 0.002 |
-| firUnit_1 | 0.002 |
-| operativeUnit_1 | 0.002 |
-| rightFir | 0.002 |
-| firUnit_1 | 0.002 |
-| operativeUnit_1 | 0.002 |
+| leftFir | 0.003 |
+| firUnit_1 | 0.003 |
+| operativeUnit_1 | 0.003 |
+| rightFir | 0.003 |
+| firUnit_1 | 0.003 |
+| operativeUnit_1 | 0.003 |
+-----------------------+-----------+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx
index 4c3e3119c3dac1fd1f0cb4ffe5fc9299a3f1efd6..724f45bf16b90901ad58d60718c5af941cb8ddfb 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb
index 939f3d598693d12429ca71be3f1fd941c4405e62..adebbea98eaa3751fbbc33ee61bfe656248e8b79 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb and b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb
index 3ce7d52e579049b70af0eb58705abebcd5156caa..5c08bc0193e4e32908d3318ed902e11875ad31cb 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb and b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
index 4e101bf919a718d0984fa8a100b74b992b5590e1..a4f7e8b26328939e3ec0575c79eecd14a293f213 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
@@ -1,11 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
- # of logical nets.......................... : 1781 :
- # of nets not needing routing.......... : 557 :
- # of internally routed nets........ : 557 :
- # of routable nets..................... : 1224 :
- # of fully routed nets............. : 1224 :
+ # of logical nets.......................... : 1774 :
+ # of nets not needing routing.......... : 555 :
+ # of internally routed nets........ : 555 :
+ # of routable nets..................... : 1219 :
+ # of fully routed nets............. : 1219 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
diff --git a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp
index cebfa27759d36b09932a27d5e1ee2508fc196e49..8345eaef6697697ff20a484b2a0ee6dc4bafb9b8 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp and b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb
index 2575ef04138d5f83cf1bfb17c0fd7c1ec3a0cb7c..0d9ab5351d779b7f444f23c28795fbdc877072da 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
index 9242e618742cc2d84bcbd4983484343488045a91..1f172e26acfc2589de798fcbca1c5081cccc245d 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:22:31 2025
+| Date : Mon May 12 16:28:53 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
| Design : audioProc
@@ -163,7 +163,7 @@ Table of Contents
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
- 0.617 0.000 0 1788 0.109 0.000 0 1788 3.000 0.000 0 903
+ 0.732 0.000 0 1788 0.050 0.000 0 1788 3.000 0.000 0 903
All user specified timing constraints are met.
@@ -191,9 +191,9 @@ CLK100MHZ {0.000 5.000} 10.000 100.000
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
CLK100MHZ 3.000 0.000 0 1
- clk_out1_clk_wiz_0 0.617 0.000 0 1567 0.134 0.000 0 1567 4.500 0.000 0 775
+ clk_out1_clk_wiz_0 0.732 0.000 0 1567 0.050 0.000 0 1567 4.500 0.000 0 775
clk_out3_clk_wiz_0 81.178 0.000 0 2
- clk_out4_clk_wiz_0 14.589 0.000 0 221 0.109 0.000 0 221 9.500 0.000 0 122
+ clk_out4_clk_wiz_0 14.342 0.000 0 221 0.132 0.000 0 221 9.500 0.000 0 122
clkfbout_clk_wiz_0 7.845 0.000 0 3
@@ -252,27 +252,27 @@ High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000
From Clock: clk_out1_clk_wiz_0
To Clock: clk_out1_clk_wiz_0
-Setup : 0 Failing Endpoints, Worst Slack 0.617ns, Total Violation 0.000ns
-Hold : 0 Failing Endpoints, Worst Slack 0.134ns, Total Violation 0.000ns
+Setup : 0 Failing Endpoints, Worst Slack 0.732ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.050ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
-Slack (MET) : 0.617ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.732ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.295ns (logic 6.059ns (65.188%) route 3.236ns (34.812%))
- Logic Levels: 7 (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.114ns (DCD - SCD + CPR)
+ Data Path Delay: 9.253ns (logic 6.211ns (67.123%) route 3.042ns (32.877%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
+ Source Clock Delay (SCD): -1.064ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
@@ -291,30 +291,35 @@ Slack (MET) : 0.617ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X152Y106 CARRY4 (Prop_carry4_CI_CO[3])
- 0.117 7.982 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.982 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
- SLICE_X152Y107 CARRY4 (Prop_carry4_CI_O[1])
- 0.323 8.305 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[1]
- net (fo=1, routed) 0.000 8.305 rightFir/firUnit_1/operativeUnit_1/p_0_in[13]
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+ net (fo=773, routed) 1.755 -1.064 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X142Y102 FDCE (Prop_fdce_C_Q) 0.518 -0.546 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=80, routed) 1.414 0.868 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X142Y96 LUT6 (Prop_lut6_I2_O) 0.124 0.992 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117/O
+ net (fo=1, routed) 0.000 0.992 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117_n_0
+ SLICE_X142Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 1.233 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57/O
+ net (fo=1, routed) 0.000 1.233 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57_n_0
+ SLICE_X142Y96 MUXF8 (Prop_muxf8_I0_O) 0.098 1.331 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_27/O
+ net (fo=1, routed) 0.805 2.136 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X7Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.036 6.172 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.824 6.995 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X144Y103 LUT2 (Prop_lut2_I0_O) 0.124 7.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2/O
+ net (fo=1, routed) 0.000 7.119 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2_n_0
+ SLICE_X144Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.632 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.632 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
+ SLICE_X144Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.749 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.749 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ SLICE_X144Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.866 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.866 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
+ SLICE_X144Y106 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 8.189 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[1]
+ net (fo=1, routed) 0.000 8.189 leftFir/firUnit_1/operativeUnit_1/p_0_in[13]
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -327,30 +332,30 @@ Slack (MET) : 0.617ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.635 8.343 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/C
+ net (fo=773, routed) 1.635 8.343 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/C
clock pessimism 0.554 8.896
clock uncertainty -0.084 8.813
- SLICE_X152Y107 FDCE (Setup_fdce_C_D) 0.109 8.922 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]
+ SLICE_X144Y106 FDCE (Setup_fdce_C_D) 0.109 8.922 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]
-------------------------------------------------------------------
required time 8.922
- arrival time -8.305
+ arrival time -8.189
-------------------------------------------------------------------
- slack 0.617
+ slack 0.732
-Slack (MET) : 0.625ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.740ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.287ns (logic 6.051ns (65.158%) route 3.236ns (34.842%))
- Logic Levels: 7 (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.114ns (DCD - SCD + CPR)
+ Data Path Delay: 9.245ns (logic 6.203ns (67.095%) route 3.042ns (32.905%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
+ Source Clock Delay (SCD): -1.064ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
@@ -369,30 +374,35 @@ Slack (MET) : 0.625ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X152Y106 CARRY4 (Prop_carry4_CI_CO[3])
- 0.117 7.982 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.982 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
- SLICE_X152Y107 CARRY4 (Prop_carry4_CI_O[3])
- 0.315 8.297 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[3]
- net (fo=1, routed) 0.000 8.297 rightFir/firUnit_1/operativeUnit_1/p_0_in[15]
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+ net (fo=773, routed) 1.755 -1.064 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X142Y102 FDCE (Prop_fdce_C_Q) 0.518 -0.546 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=80, routed) 1.414 0.868 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X142Y96 LUT6 (Prop_lut6_I2_O) 0.124 0.992 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117/O
+ net (fo=1, routed) 0.000 0.992 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117_n_0
+ SLICE_X142Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 1.233 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57/O
+ net (fo=1, routed) 0.000 1.233 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57_n_0
+ SLICE_X142Y96 MUXF8 (Prop_muxf8_I0_O) 0.098 1.331 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_27/O
+ net (fo=1, routed) 0.805 2.136 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X7Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.036 6.172 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.824 6.995 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X144Y103 LUT2 (Prop_lut2_I0_O) 0.124 7.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2/O
+ net (fo=1, routed) 0.000 7.119 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2_n_0
+ SLICE_X144Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.632 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.632 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
+ SLICE_X144Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.749 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.749 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ SLICE_X144Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.866 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.866 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
+ SLICE_X144Y106 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 8.181 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[3]
+ net (fo=1, routed) 0.000 8.181 leftFir/firUnit_1/operativeUnit_1/p_0_in[15]
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -405,31 +415,31 @@ Slack (MET) : 0.625ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.635 8.343 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/C
+ net (fo=773, routed) 1.635 8.343 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/C
clock pessimism 0.554 8.896
clock uncertainty -0.084 8.813
- SLICE_X152Y107 FDCE (Setup_fdce_C_D) 0.109 8.922 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]
+ SLICE_X144Y106 FDCE (Setup_fdce_C_D) 0.109 8.922 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]
-------------------------------------------------------------------
required time 8.922
- arrival time -8.297
+ arrival time -8.181
-------------------------------------------------------------------
- slack 0.625
+ slack 0.740
-Slack (MET) : 0.701ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.812ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.211ns (logic 5.975ns (64.871%) route 3.236ns (35.129%))
- Logic Levels: 7 (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.114ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Data Path Delay: 8.927ns (logic 6.350ns (71.129%) route 2.577ns (28.871%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.286ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.656ns = ( 8.344 - 10.000 )
+ Source Clock Delay (SCD): -0.889ns
+ Clock Pessimism Removal (CPR): 0.482ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.151ns
@@ -447,30 +457,35 @@ Slack (MET) : 0.701ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X152Y106 CARRY4 (Prop_carry4_CI_CO[3])
- 0.117 7.982 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.982 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
- SLICE_X152Y107 CARRY4 (Prop_carry4_CI_O[2])
- 0.239 8.221 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[2]
- net (fo=1, routed) 0.000 8.221 rightFir/firUnit_1/operativeUnit_1/p_0_in[14]
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
+ net (fo=773, routed) 1.930 -0.889 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X148Y98 FDCE (Prop_fdce_C_Q) 0.478 -0.411 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/Q
+ net (fo=2, routed) 1.095 0.685 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_7[1]
+ SLICE_X149Y98 LUT6 (Prop_lut6_I1_O) 0.296 0.981 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0/O
+ net (fo=1, routed) 0.000 0.981 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0_n_0
+ SLICE_X149Y98 MUXF7 (Prop_muxf7_I1_O) 0.245 1.226 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0/O
+ net (fo=1, routed) 0.000 1.226 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0_n_0
+ SLICE_X149Y98 MUXF8 (Prop_muxf8_I0_O) 0.104 1.330 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_27__0/O
+ net (fo=1, routed) 0.682 2.011 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.033 6.044 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.801 6.845 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X152Y103 LUT2 (Prop_lut2_I0_O) 0.124 6.969 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0/O
+ net (fo=1, routed) 0.000 6.969 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0_n_0
+ SLICE_X152Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.482 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.482 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0_n_0
+ SLICE_X152Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.599 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.599 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0_n_0
+ SLICE_X152Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.716 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.716 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0_n_0
+ SLICE_X152Y106 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 8.039 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1__0/O[1]
+ net (fo=1, routed) 0.000 8.039 rightFir/firUnit_1/operativeUnit_1/p_0_in[13]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -483,30 +498,30 @@ Slack (MET) : 0.701ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.635 8.343 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/C
- clock pessimism 0.554 8.896
- clock uncertainty -0.084 8.813
- SLICE_X152Y107 FDCE (Setup_fdce_C_D) 0.109 8.922 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]
+ net (fo=773, routed) 1.636 8.344 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/C
+ clock pessimism 0.482 8.825
+ clock uncertainty -0.084 8.742
+ SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.851 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]
-------------------------------------------------------------------
- required time 8.922
- arrival time -8.221
+ required time 8.851
+ arrival time -8.039
-------------------------------------------------------------------
- slack 0.701
+ slack 0.812
-Slack (MET) : 0.721ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.816ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.191ns (logic 5.955ns (64.794%) route 3.236ns (35.206%))
- Logic Levels: 7 (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.114ns (DCD - SCD + CPR)
+ Data Path Delay: 9.169ns (logic 6.127ns (66.822%) route 3.042ns (33.178%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
+ Source Clock Delay (SCD): -1.064ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
@@ -525,30 +540,35 @@ Slack (MET) : 0.721ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X152Y106 CARRY4 (Prop_carry4_CI_CO[3])
- 0.117 7.982 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.982 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
- SLICE_X152Y107 CARRY4 (Prop_carry4_CI_O[0])
- 0.219 8.201 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[0]
- net (fo=1, routed) 0.000 8.201 rightFir/firUnit_1/operativeUnit_1/p_0_in[12]
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
+ net (fo=773, routed) 1.755 -1.064 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X142Y102 FDCE (Prop_fdce_C_Q) 0.518 -0.546 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=80, routed) 1.414 0.868 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X142Y96 LUT6 (Prop_lut6_I2_O) 0.124 0.992 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117/O
+ net (fo=1, routed) 0.000 0.992 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117_n_0
+ SLICE_X142Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 1.233 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57/O
+ net (fo=1, routed) 0.000 1.233 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57_n_0
+ SLICE_X142Y96 MUXF8 (Prop_muxf8_I0_O) 0.098 1.331 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_27/O
+ net (fo=1, routed) 0.805 2.136 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X7Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.036 6.172 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.824 6.995 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X144Y103 LUT2 (Prop_lut2_I0_O) 0.124 7.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2/O
+ net (fo=1, routed) 0.000 7.119 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2_n_0
+ SLICE_X144Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.632 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.632 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
+ SLICE_X144Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.749 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.749 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ SLICE_X144Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.866 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.866 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
+ SLICE_X144Y106 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 8.105 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[2]
+ net (fo=1, routed) 0.000 8.105 leftFir/firUnit_1/operativeUnit_1/p_0_in[14]
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -561,31 +581,31 @@ Slack (MET) : 0.721ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.635 8.343 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/C
+ net (fo=773, routed) 1.635 8.343 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/C
clock pessimism 0.554 8.896
clock uncertainty -0.084 8.813
- SLICE_X152Y107 FDCE (Setup_fdce_C_D) 0.109 8.922 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]
+ SLICE_X144Y106 FDCE (Setup_fdce_C_D) 0.109 8.922 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]
-------------------------------------------------------------------
required time 8.922
- arrival time -8.201
+ arrival time -8.105
-------------------------------------------------------------------
- slack 0.721
+ slack 0.816
-Slack (MET) : 0.735ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.820ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/D
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.178ns (logic 5.942ns (64.745%) route 3.236ns (35.255%))
- Logic Levels: 6 (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.113ns (DCD - SCD + CPR)
+ Data Path Delay: 8.919ns (logic 6.342ns (71.103%) route 2.577ns (28.897%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.286ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.656ns = ( 8.344 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Source Clock Delay (SCD): -0.889ns
+ Clock Pessimism Removal (CPR): 0.482ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.151ns
@@ -603,27 +623,35 @@ Slack (MET) : 0.735ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X152Y106 CARRY4 (Prop_carry4_CI_O[1])
- 0.323 8.188 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[1]
- net (fo=1, routed) 0.000 8.188 rightFir/firUnit_1/operativeUnit_1/p_0_in[9]
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/D
+ net (fo=773, routed) 1.930 -0.889 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X148Y98 FDCE (Prop_fdce_C_Q) 0.478 -0.411 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/Q
+ net (fo=2, routed) 1.095 0.685 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_7[1]
+ SLICE_X149Y98 LUT6 (Prop_lut6_I1_O) 0.296 0.981 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0/O
+ net (fo=1, routed) 0.000 0.981 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0_n_0
+ SLICE_X149Y98 MUXF7 (Prop_muxf7_I1_O) 0.245 1.226 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0/O
+ net (fo=1, routed) 0.000 1.226 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0_n_0
+ SLICE_X149Y98 MUXF8 (Prop_muxf8_I0_O) 0.104 1.330 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_27__0/O
+ net (fo=1, routed) 0.682 2.011 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.033 6.044 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.801 6.845 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X152Y103 LUT2 (Prop_lut2_I0_O) 0.124 6.969 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0/O
+ net (fo=1, routed) 0.000 6.969 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0_n_0
+ SLICE_X152Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.482 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.482 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0_n_0
+ SLICE_X152Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.599 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.599 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0_n_0
+ SLICE_X152Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.716 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.716 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0_n_0
+ SLICE_X152Y106 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 8.031 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1__0/O[3]
+ net (fo=1, routed) 0.000 8.031 rightFir/firUnit_1/operativeUnit_1/p_0_in[15]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -637,29 +665,29 @@ Slack (MET) : 0.735ns (required time - arrival time)
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
net (fo=773, routed) 1.636 8.344 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/C
- clock pessimism 0.554 8.897
- clock uncertainty -0.084 8.814
- SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.923 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/C
+ clock pessimism 0.482 8.825
+ clock uncertainty -0.084 8.742
+ SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.851 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]
-------------------------------------------------------------------
- required time 8.923
- arrival time -8.188
+ required time 8.851
+ arrival time -8.031
-------------------------------------------------------------------
- slack 0.735
+ slack 0.820
-Slack (MET) : 0.743ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.836ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.170ns (logic 5.934ns (64.714%) route 3.236ns (35.286%))
- Logic Levels: 6 (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.113ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.656ns = ( 8.344 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
+ Data Path Delay: 9.149ns (logic 6.107ns (66.750%) route 3.042ns (33.250%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.040ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
+ Source Clock Delay (SCD): -1.064ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
@@ -678,27 +706,35 @@ Slack (MET) : 0.743ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X152Y106 CARRY4 (Prop_carry4_CI_O[3])
- 0.315 8.180 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[3]
- net (fo=1, routed) 0.000 8.180 rightFir/firUnit_1/operativeUnit_1/p_0_in[11]
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/D
+ net (fo=773, routed) 1.755 -1.064 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X142Y102 FDCE (Prop_fdce_C_Q) 0.518 -0.546 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=80, routed) 1.414 0.868 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X142Y96 LUT6 (Prop_lut6_I2_O) 0.124 0.992 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117/O
+ net (fo=1, routed) 0.000 0.992 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117_n_0
+ SLICE_X142Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 1.233 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57/O
+ net (fo=1, routed) 0.000 1.233 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57_n_0
+ SLICE_X142Y96 MUXF8 (Prop_muxf8_I0_O) 0.098 1.331 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_27/O
+ net (fo=1, routed) 0.805 2.136 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X7Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.036 6.172 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.824 6.995 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X144Y103 LUT2 (Prop_lut2_I0_O) 0.124 7.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2/O
+ net (fo=1, routed) 0.000 7.119 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2_n_0
+ SLICE_X144Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.632 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.632 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
+ SLICE_X144Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.749 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.749 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ SLICE_X144Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.866 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.866 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
+ SLICE_X144Y106 CARRY4 (Prop_carry4_CI_O[0])
+ 0.219 8.085 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[0]
+ net (fo=1, routed) 0.000 8.085 leftFir/firUnit_1/operativeUnit_1/p_0_in[12]
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -711,31 +747,31 @@ Slack (MET) : 0.743ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.636 8.344 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/C
- clock pessimism 0.554 8.897
- clock uncertainty -0.084 8.814
- SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.923 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]
+ net (fo=773, routed) 1.635 8.343 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X144Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/C
+ clock pessimism 0.554 8.896
+ clock uncertainty -0.084 8.813
+ SLICE_X144Y106 FDCE (Setup_fdce_C_D) 0.109 8.922 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]
-------------------------------------------------------------------
- required time 8.923
- arrival time -8.180
+ required time 8.922
+ arrival time -8.085
-------------------------------------------------------------------
- slack 0.743
+ slack 0.836
-Slack (MET) : 0.769ns (required time - arrival time)
+Slack (MET) : 0.849ns (required time - arrival time)
Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.185ns (logic 6.198ns (67.481%) route 2.987ns (32.519%))
- Logic Levels: 8 (CARRY4=4 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.659ns = ( 8.341 - 10.000 )
- Source Clock Delay (SCD): -1.066ns
- Clock Pessimism Removal (CPR): 0.569ns
+ Data Path Delay: 9.136ns (logic 6.094ns (66.702%) route 3.042ns (33.298%))
+ Logic Levels: 8 (CARRY4=3 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.040ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
+ Source Clock Delay (SCD): -1.064ns
+ Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.151ns
@@ -753,33 +789,32 @@ Slack (MET) : 0.769ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.753 -1.066 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X145Y110 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X145Y110 FDCE (Prop_fdce_C_Q) 0.456 -0.610 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.538 0.928 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X137Y104 LUT6 (Prop_lut6_I2_O) 0.124 1.052 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122/O
- net (fo=1, routed) 0.000 1.052 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122_n_0
- SLICE_X137Y104 MUXF7 (Prop_muxf7_I1_O) 0.245 1.297 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59/O
- net (fo=1, routed) 0.000 1.297 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59_n_0
- SLICE_X137Y104 MUXF8 (Prop_muxf8_I0_O) 0.104 1.401 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_28/O
- net (fo=1, routed) 0.656 2.057 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[0]
- DSP48_X7Y42 DSP48E1 (Prop_dsp48e1_A[0]_P[16])
- 4.033 6.090 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[16]
- net (fo=2, routed) 0.793 6.883 leftFir/firUnit_1/operativeUnit_1/L[16]
- SLICE_X145Y106 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.674 7.557 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.557 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
- SLICE_X145Y107 CARRY4 (Prop_carry4_CI_CO[3])
- 0.114 7.671 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.671 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X145Y108 CARRY4 (Prop_carry4_CI_CO[3])
- 0.114 7.785 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.785 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
- SLICE_X145Y109 CARRY4 (Prop_carry4_CI_O[1])
- 0.334 8.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[1]
- net (fo=1, routed) 0.000 8.119 leftFir/firUnit_1/operativeUnit_1/p_0_in[13]
- SLICE_X145Y109 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+ net (fo=773, routed) 1.755 -1.064 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X142Y102 FDCE (Prop_fdce_C_Q) 0.518 -0.546 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=80, routed) 1.414 0.868 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X142Y96 LUT6 (Prop_lut6_I2_O) 0.124 0.992 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117/O
+ net (fo=1, routed) 0.000 0.992 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117_n_0
+ SLICE_X142Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 1.233 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57/O
+ net (fo=1, routed) 0.000 1.233 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57_n_0
+ SLICE_X142Y96 MUXF8 (Prop_muxf8_I0_O) 0.098 1.331 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_27/O
+ net (fo=1, routed) 0.805 2.136 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X7Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.036 6.172 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.824 6.995 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X144Y103 LUT2 (Prop_lut2_I0_O) 0.124 7.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2/O
+ net (fo=1, routed) 0.000 7.119 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2_n_0
+ SLICE_X144Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.632 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.632 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
+ SLICE_X144Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.749 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.749 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ SLICE_X144Y105 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 8.072 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[1]
+ net (fo=1, routed) 0.000 8.072 leftFir/firUnit_1/operativeUnit_1/p_0_in[9]
+ SLICE_X144Y105 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -792,31 +827,31 @@ Slack (MET) : 0.769ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.633 8.341 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X145Y109 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/C
- clock pessimism 0.569 8.909
- clock uncertainty -0.084 8.826
- SLICE_X145Y109 FDCE (Setup_fdce_C_D) 0.062 8.888 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]
+ net (fo=773, routed) 1.635 8.343 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X144Y105 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/C
+ clock pessimism 0.554 8.896
+ clock uncertainty -0.084 8.813
+ SLICE_X144Y105 FDCE (Setup_fdce_C_D) 0.109 8.922 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]
-------------------------------------------------------------------
- required time 8.888
- arrival time -8.119
+ required time 8.922
+ arrival time -8.072
-------------------------------------------------------------------
- slack 0.769
+ slack 0.849
-Slack (MET) : 0.790ns (required time - arrival time)
+Slack (MET) : 0.857ns (required time - arrival time)
Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.164ns (logic 6.177ns (67.406%) route 2.987ns (32.594%))
- Logic Levels: 8 (CARRY4=4 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.659ns = ( 8.341 - 10.000 )
- Source Clock Delay (SCD): -1.066ns
- Clock Pessimism Removal (CPR): 0.569ns
+ Data Path Delay: 9.128ns (logic 6.086ns (66.673%) route 3.042ns (33.327%))
+ Logic Levels: 8 (CARRY4=3 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.040ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.657ns = ( 8.343 - 10.000 )
+ Source Clock Delay (SCD): -1.064ns
+ Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.151ns
@@ -834,33 +869,32 @@ Slack (MET) : 0.790ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.753 -1.066 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X145Y110 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X145Y110 FDCE (Prop_fdce_C_Q) 0.456 -0.610 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.538 0.928 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X137Y104 LUT6 (Prop_lut6_I2_O) 0.124 1.052 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122/O
- net (fo=1, routed) 0.000 1.052 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122_n_0
- SLICE_X137Y104 MUXF7 (Prop_muxf7_I1_O) 0.245 1.297 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59/O
- net (fo=1, routed) 0.000 1.297 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59_n_0
- SLICE_X137Y104 MUXF8 (Prop_muxf8_I0_O) 0.104 1.401 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_28/O
- net (fo=1, routed) 0.656 2.057 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[0]
- DSP48_X7Y42 DSP48E1 (Prop_dsp48e1_A[0]_P[16])
- 4.033 6.090 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[16]
- net (fo=2, routed) 0.793 6.883 leftFir/firUnit_1/operativeUnit_1/L[16]
- SLICE_X145Y106 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.674 7.557 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.557 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
- SLICE_X145Y107 CARRY4 (Prop_carry4_CI_CO[3])
- 0.114 7.671 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.671 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
- SLICE_X145Y108 CARRY4 (Prop_carry4_CI_CO[3])
- 0.114 7.785 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.785 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
- SLICE_X145Y109 CARRY4 (Prop_carry4_CI_O[3])
- 0.313 8.098 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[3]
- net (fo=1, routed) 0.000 8.098 leftFir/firUnit_1/operativeUnit_1/p_0_in[15]
- SLICE_X145Y109 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+ net (fo=773, routed) 1.755 -1.064 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X142Y102 FDCE (Prop_fdce_C_Q) 0.518 -0.546 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=80, routed) 1.414 0.868 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X142Y96 LUT6 (Prop_lut6_I2_O) 0.124 0.992 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117/O
+ net (fo=1, routed) 0.000 0.992 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_117_n_0
+ SLICE_X142Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 1.233 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57/O
+ net (fo=1, routed) 0.000 1.233 leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_57_n_0
+ SLICE_X142Y96 MUXF8 (Prop_muxf8_I0_O) 0.098 1.331 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_27/O
+ net (fo=1, routed) 0.805 2.136 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X7Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.036 6.172 r leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.824 6.995 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X144Y103 LUT2 (Prop_lut2_I0_O) 0.124 7.119 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2/O
+ net (fo=1, routed) 0.000 7.119 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2_n_0
+ SLICE_X144Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.632 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.632 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
+ SLICE_X144Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.749 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
+ net (fo=1, routed) 0.000 7.749 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ SLICE_X144Y105 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 8.064 r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[3]
+ net (fo=1, routed) 0.000 8.064 leftFir/firUnit_1/operativeUnit_1/p_0_in[11]
+ SLICE_X144Y105 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -873,31 +907,31 @@ Slack (MET) : 0.790ns (required time - arrival time)
-7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.633 8.341 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X145Y109 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/C
- clock pessimism 0.569 8.909
- clock uncertainty -0.084 8.826
- SLICE_X145Y109 FDCE (Setup_fdce_C_D) 0.062 8.888 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]
+ net (fo=773, routed) 1.635 8.343 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X144Y105 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/C
+ clock pessimism 0.554 8.896
+ clock uncertainty -0.084 8.813
+ SLICE_X144Y105 FDCE (Setup_fdce_C_D) 0.109 8.922 leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]
-------------------------------------------------------------------
- required time 8.888
- arrival time -8.098
+ required time 8.922
+ arrival time -8.064
-------------------------------------------------------------------
- slack 0.790
+ slack 0.857
-Slack (MET) : 0.819ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.896ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]/D
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.094ns (logic 5.858ns (64.419%) route 3.236ns (35.581%))
- Logic Levels: 6 (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.113ns (DCD - SCD + CPR)
+ Data Path Delay: 8.843ns (logic 6.266ns (70.854%) route 2.577ns (29.146%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.286ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.656ns = ( 8.344 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Source Clock Delay (SCD): -0.889ns
+ Clock Pessimism Removal (CPR): 0.482ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.151ns
@@ -915,27 +949,35 @@ Slack (MET) : 0.819ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ net (fo=773, routed) 1.930 -0.889 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X148Y98 FDCE (Prop_fdce_C_Q) 0.478 -0.411 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/Q
+ net (fo=2, routed) 1.095 0.685 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_7[1]
+ SLICE_X149Y98 LUT6 (Prop_lut6_I1_O) 0.296 0.981 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0/O
+ net (fo=1, routed) 0.000 0.981 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0_n_0
+ SLICE_X149Y98 MUXF7 (Prop_muxf7_I1_O) 0.245 1.226 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0/O
+ net (fo=1, routed) 0.000 1.226 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0_n_0
+ SLICE_X149Y98 MUXF8 (Prop_muxf8_I0_O) 0.104 1.330 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_27__0/O
+ net (fo=1, routed) 0.682 2.011 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.033 6.044 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.801 6.845 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X152Y103 LUT2 (Prop_lut2_I0_O) 0.124 6.969 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0/O
+ net (fo=1, routed) 0.000 6.969 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0_n_0
+ SLICE_X152Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.482 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.482 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0_n_0
+ SLICE_X152Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.599 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.599 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0_n_0
+ SLICE_X152Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.716 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.716 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0_n_0
SLICE_X152Y106 CARRY4 (Prop_carry4_CI_O[2])
- 0.239 8.104 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[2]
- net (fo=1, routed) 0.000 8.104 rightFir/firUnit_1/operativeUnit_1/p_0_in[10]
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]/D
+ 0.239 7.955 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1__0/O[2]
+ net (fo=1, routed) 0.000 7.955 rightFir/firUnit_1/operativeUnit_1/p_0_in[14]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -949,30 +991,30 @@ Slack (MET) : 0.819ns (required time - arrival time)
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
net (fo=773, routed) 1.636 8.344 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]/C
- clock pessimism 0.554 8.897
- clock uncertainty -0.084 8.814
- SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.923 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/C
+ clock pessimism 0.482 8.825
+ clock uncertainty -0.084 8.742
+ SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.851 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]
-------------------------------------------------------------------
- required time 8.923
- arrival time -8.104
+ required time 8.851
+ arrival time -7.955
-------------------------------------------------------------------
- slack 0.819
+ slack 0.896
-Slack (MET) : 0.839ns (required time - arrival time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) : 0.916ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]/D
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 9.074ns (logic 5.838ns (64.340%) route 3.236ns (35.660%))
- Logic Levels: 6 (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
- Clock Path Skew: -0.113ns (DCD - SCD + CPR)
+ Data Path Delay: 8.823ns (logic 6.246ns (70.788%) route 2.577ns (29.212%))
+ Logic Levels: 9 (CARRY4=4 DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.286ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.656ns = ( 8.344 - 10.000 )
- Source Clock Delay (SCD): -0.990ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Source Clock Delay (SCD): -0.889ns
+ Clock Pessimism Removal (CPR): 0.482ns
Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.151ns
@@ -990,27 +1032,35 @@ Slack (MET) : 0.839ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 1.829 -0.990 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X156Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y108 FDCE (Prop_fdce_C_Q) 0.456 -0.534 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
- net (fo=79, routed) 1.549 1.015 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
- SLICE_X149Y103 LUT6 (Prop_lut6_I2_O) 0.124 1.139 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
- net (fo=1, routed) 0.000 1.139 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
- SLICE_X149Y103 MUXF7 (Prop_muxf7_I1_O) 0.245 1.384 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
- net (fo=1, routed) 0.000 1.384 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
- SLICE_X149Y103 MUXF8 (Prop_muxf8_I0_O) 0.104 1.488 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
- net (fo=15, routed) 0.761 2.249 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
- DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[23]_P[20])
- 4.033 6.282 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
- net (fo=2, routed) 0.925 7.208 rightFir/firUnit_1/operativeUnit_1/L[20]
- SLICE_X152Y105 CARRY4 (Prop_carry4_S[1]_CO[3])
- 0.657 7.865 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
- net (fo=1, routed) 0.000 7.865 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
+ net (fo=773, routed) 1.930 -0.889 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X148Y98 FDCE (Prop_fdce_C_Q) 0.478 -0.411 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][1]/Q
+ net (fo=2, routed) 1.095 0.685 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_7[1]
+ SLICE_X149Y98 LUT6 (Prop_lut6_I1_O) 0.296 0.981 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0/O
+ net (fo=1, routed) 0.000 0.981 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_118__0_n_0
+ SLICE_X149Y98 MUXF7 (Prop_muxf7_I1_O) 0.245 1.226 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0/O
+ net (fo=1, routed) 0.000 1.226 rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_57__0_n_0
+ SLICE_X149Y98 MUXF8 (Prop_muxf8_I0_O) 0.104 1.330 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_27__0/O
+ net (fo=1, routed) 0.682 2.011 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[1]
+ DSP48_X8Y40 DSP48E1 (Prop_dsp48e1_A[1]_P[14])
+ 4.033 6.044 r rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+ net (fo=3, routed) 0.801 6.845 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+ SLICE_X152Y103 LUT2 (Prop_lut2_I0_O) 0.124 6.969 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0/O
+ net (fo=1, routed) 0.000 6.969 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample[3]_i_2__0_n_0
+ SLICE_X152Y103 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 7.482 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.482 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1__0_n_0
+ SLICE_X152Y104 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.599 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.599 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1__0_n_0
+ SLICE_X152Y105 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 7.716 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0/CO[3]
+ net (fo=1, routed) 0.000 7.716 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1__0_n_0
SLICE_X152Y106 CARRY4 (Prop_carry4_CI_O[0])
- 0.219 8.084 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[0]
- net (fo=1, routed) 0.000 8.084 rightFir/firUnit_1/operativeUnit_1/p_0_in[8]
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]/D
+ 0.219 7.935 r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1__0/O[0]
+ net (fo=1, routed) 0.000 7.935 rightFir/firUnit_1/operativeUnit_1/p_0_in[12]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1024,15 +1074,15 @@ Slack (MET) : 0.839ns (required time - arrival time)
net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
net (fo=773, routed) 1.636 8.344 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]/C
- clock pessimism 0.554 8.897
- clock uncertainty -0.084 8.814
- SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.923 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]
+ SLICE_X152Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/C
+ clock pessimism 0.482 8.825
+ clock uncertainty -0.084 8.742
+ SLICE_X152Y106 FDCE (Setup_fdce_C_D) 0.109 8.851 rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]
-------------------------------------------------------------------
- required time 8.923
- arrival time -8.084
+ required time 8.851
+ arrival time -7.935
-------------------------------------------------------------------
- slack 0.839
+ slack 0.916
@@ -1040,20 +1090,20 @@ Slack (MET) : 0.839ns (required time - arrival time)
Min Delay Paths
--------------------------------------------------------------------------------------
-Slack (MET) : 0.134ns (arrival time - required time)
- Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+Slack (MET) : 0.050ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][4]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][4]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
+ Data Path Delay: 0.323ns (logic 0.164ns (50.852%) route 0.159ns (49.148%))
Logic Levels: 0
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.925ns
- Source Clock Delay (SCD): -0.683ns
- Clock Pessimism Removal (CPR): -0.242ns
+ Clock Path Skew: 0.200ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.921ns
+ Source Clock Delay (SCD): -0.612ns
+ Clock Pessimism Removal (CPR): -0.509ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1067,12 +1117,12 @@ Slack (MET) : 0.134ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.617 -0.683 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X143Y110 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+ net (fo=773, routed) 0.687 -0.612 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y99 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][4]/C
------------------------------------------------------------------- -------------------
- SLICE_X143Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/Q
- net (fo=2, routed) 0.068 -0.474 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[14]
- SLICE_X143Y110 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+ SLICE_X148Y99 FDCE (Prop_fdce_C_Q) 0.164 -0.448 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][4]/Q
+ net (fo=2, routed) 0.159 -0.290 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13]_14[4]
+ SLICE_X149Y100 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][4]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1085,30 +1135,30 @@ Slack (MET) : 0.134ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.889 -0.925 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X143Y110 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/C
- clock pessimism 0.242 -0.683
- SLICE_X143Y110 FDCE (Hold_fdce_C_D) 0.075 -0.608 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]
+ net (fo=773, routed) 0.893 -0.921 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X149Y100 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][4]/C
+ clock pessimism 0.509 -0.412
+ SLICE_X149Y100 FDCE (Hold_fdce_C_D) 0.072 -0.340 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][4]
-------------------------------------------------------------------
- required time 0.608
- arrival time -0.474
+ required time 0.340
+ arrival time -0.290
-------------------------------------------------------------------
- slack 0.134
+ slack 0.050
-Slack (MET) : 0.142ns (arrival time - required time)
- Source: audio_inout/Data_Out_int_reg[9]/C
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: audio_inout/Data_Out_int_reg[10]/D
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+Slack (MET) : 0.133ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.300ns (logic 0.186ns (62.061%) route 0.114ns (37.939%))
- Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.037ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.925ns
- Source Clock Delay (SCD): -0.682ns
- Clock Pessimism Removal (CPR): -0.280ns
+ Data Path Delay: 0.208ns (logic 0.141ns (67.788%) route 0.067ns (32.212%))
+ Logic Levels: 0
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.948ns
+ Source Clock Delay (SCD): -0.705ns
+ Clock Pessimism Removal (CPR): -0.243ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1122,14 +1172,12 @@ Slack (MET) : 0.142ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.618 -0.682 audio_inout/clk_out1
- SLICE_X155Y112 FDRE r audio_inout/Data_Out_int_reg[9]/C
+ net (fo=773, routed) 0.595 -0.705 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X139Y103 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
------------------------------------------------------------------- -------------------
- SLICE_X155Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r audio_inout/Data_Out_int_reg[9]/Q
- net (fo=1, routed) 0.114 -0.427 audio_inout/Data_Out_int_reg_n_0_[9]
- SLICE_X152Y112 LUT6 (Prop_lut6_I4_O) 0.045 -0.382 r audio_inout/Data_Out_int[10]_i_1/O
- net (fo=1, routed) 0.000 -0.382 audio_inout/Data_Out_int[10]_i_1_n_0
- SLICE_X152Y112 FDRE r audio_inout/Data_Out_int_reg[10]/D
+ SLICE_X139Y103 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/Q
+ net (fo=2, routed) 0.067 -0.497 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[14]
+ SLICE_X139Y103 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1142,30 +1190,30 @@ Slack (MET) : 0.142ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.889 -0.925 audio_inout/clk_out1
- SLICE_X152Y112 FDRE r audio_inout/Data_Out_int_reg[10]/C
- clock pessimism 0.280 -0.645
- SLICE_X152Y112 FDRE (Hold_fdre_C_D) 0.121 -0.524 audio_inout/Data_Out_int_reg[10]
+ net (fo=773, routed) 0.866 -0.948 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X139Y103 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/C
+ clock pessimism 0.243 -0.705
+ SLICE_X139Y103 FDCE (Hold_fdce_C_D) 0.075 -0.630 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]
-------------------------------------------------------------------
- required time 0.524
- arrival time -0.382
+ required time 0.630
+ arrival time -0.497
-------------------------------------------------------------------
- slack 0.142
+ slack 0.133
-Slack (MET) : 0.143ns (arrival time - required time)
- Source: audio_inout/Data_Out_int_reg[23]/C
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: audio_inout/Data_Out_int_reg[24]/D
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+Slack (MET) : 0.134ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][12]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][12]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.301ns (logic 0.186ns (61.698%) route 0.115ns (38.302%))
- Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.038ns (DCD - SCD - CPR)
+ Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
+ Logic Levels: 0
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.922ns
Source Clock Delay (SCD): -0.680ns
- Clock Pessimism Removal (CPR): -0.280ns
+ Clock Pessimism Removal (CPR): -0.242ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1179,14 +1227,12 @@ Slack (MET) : 0.143ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.620 -0.680 audio_inout/clk_out1
- SLICE_X153Y107 FDRE r audio_inout/Data_Out_int_reg[23]/C
+ net (fo=773, routed) 0.620 -0.680 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][12]/C
------------------------------------------------------------------- -------------------
- SLICE_X153Y107 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r audio_inout/Data_Out_int_reg[23]/Q
- net (fo=1, routed) 0.115 -0.423 audio_inout/Data_Out_int_reg_n_0_[23]
- SLICE_X154Y108 LUT6 (Prop_lut6_I3_O) 0.045 -0.378 r audio_inout/Data_Out_int[24]_i_1/O
- net (fo=1, routed) 0.000 -0.378 audio_inout/Data_Out_int[24]_i_1_n_0
- SLICE_X154Y108 FDRE r audio_inout/Data_Out_int_reg[24]/D
+ SLICE_X153Y108 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][12]/Q
+ net (fo=2, routed) 0.068 -0.471 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[12]
+ SLICE_X153Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][12]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1199,30 +1245,30 @@ Slack (MET) : 0.143ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.892 -0.922 audio_inout/clk_out1
- SLICE_X154Y108 FDRE r audio_inout/Data_Out_int_reg[24]/C
- clock pessimism 0.280 -0.642
- SLICE_X154Y108 FDRE (Hold_fdre_C_D) 0.120 -0.522 audio_inout/Data_Out_int_reg[24]
+ net (fo=773, routed) 0.892 -0.922 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y108 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][12]/C
+ clock pessimism 0.242 -0.680
+ SLICE_X153Y108 FDCE (Hold_fdce_C_D) 0.075 -0.605 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][12]
-------------------------------------------------------------------
- required time 0.522
- arrival time -0.378
+ required time 0.605
+ arrival time -0.471
-------------------------------------------------------------------
- slack 0.143
+ slack 0.134
-Slack (MET) : 0.159ns (arrival time - required time)
- Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/C
- (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]/D
- (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+Slack (MET) : 0.152ns (arrival time - required time)
+ Source: audio_inout/Cnt_Lrclk_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Cnt_Lrclk_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.253ns (logic 0.141ns (55.700%) route 0.112ns (44.300%))
- Logic Levels: 0
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.948ns
- Source Clock Delay (SCD): -0.705ns
- Clock Pessimism Removal (CPR): -0.259ns
+ Data Path Delay: 0.286ns (logic 0.186ns (65.123%) route 0.100ns (34.877%))
+ Logic Levels: 1 (LUT5=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.924ns
+ Source Clock Delay (SCD): -0.682ns
+ Clock Pessimism Removal (CPR): -0.255ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1236,12 +1282,14 @@ Slack (MET) : 0.159ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.595 -0.705 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X138Y106 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/C
+ net (fo=773, routed) 0.618 -0.682 audio_inout/clk_out1
+ SLICE_X149Y110 FDRE r audio_inout/Cnt_Lrclk_reg[1]/C
------------------------------------------------------------------- -------------------
- SLICE_X138Y106 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/Q
- net (fo=2, routed) 0.112 -0.452 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8]_15[7]
- SLICE_X137Y105 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]/D
+ SLICE_X149Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r audio_inout/Cnt_Lrclk_reg[1]/Q
+ net (fo=6, routed) 0.100 -0.441 audio_inout/Cnt_Lrclk[1]
+ SLICE_X148Y110 LUT5 (Prop_lut5_I2_O) 0.045 -0.396 r audio_inout/Cnt_Lrclk[4]_i_2/O
+ net (fo=1, routed) 0.000 -0.396 audio_inout/Cnt_Lrclk[4]_i_2_n_0
+ SLICE_X148Y110 FDRE r audio_inout/Cnt_Lrclk_reg[4]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1254,29 +1302,29 @@ Slack (MET) : 0.159ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.866 -0.948 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X137Y105 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]/C
- clock pessimism 0.259 -0.689
- SLICE_X137Y105 FDCE (Hold_fdce_C_D) 0.078 -0.611 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]
+ net (fo=773, routed) 0.890 -0.924 audio_inout/clk_out1
+ SLICE_X148Y110 FDRE r audio_inout/Cnt_Lrclk_reg[4]/C
+ clock pessimism 0.255 -0.669
+ SLICE_X148Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 audio_inout/Cnt_Lrclk_reg[4]
-------------------------------------------------------------------
- required time 0.611
- arrival time -0.452
+ required time 0.548
+ arrival time -0.396
-------------------------------------------------------------------
- slack 0.159
+ slack 0.152
-Slack (MET) : 0.160ns (arrival time - required time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][1]/C
+Slack (MET) : 0.153ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][15]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][15]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.268ns (logic 0.141ns (52.702%) route 0.127ns (47.298%))
+ Data Path Delay: 0.268ns (logic 0.141ns (52.581%) route 0.127ns (47.419%))
Logic Levels: 0
- Clock Path Skew: 0.038ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.894ns
- Source Clock Delay (SCD): -0.652ns
+ Clock Path Skew: 0.039ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.924ns
+ Source Clock Delay (SCD): -0.683ns
Clock Pessimism Removal (CPR): -0.280ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
@@ -1291,12 +1339,12 @@ Slack (MET) : 0.160ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.648 -0.652 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X161Y103 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][1]/C
+ net (fo=773, routed) 0.617 -0.683 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X141Y107 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][15]/C
------------------------------------------------------------------- -------------------
- SLICE_X161Y103 FDCE (Prop_fdce_C_Q) 0.141 -0.511 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][1]/Q
- net (fo=2, routed) 0.127 -0.384 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11]_3[1]
- SLICE_X159Y103 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]/D
+ SLICE_X141Y107 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][15]/Q
+ net (fo=2, routed) 0.127 -0.415 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12]_13[15]
+ SLICE_X142Y107 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][15]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1309,30 +1357,30 @@ Slack (MET) : 0.160ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.920 -0.894 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X159Y103 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]/C
- clock pessimism 0.280 -0.614
- SLICE_X159Y103 FDCE (Hold_fdce_C_D) 0.070 -0.544 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]
+ net (fo=773, routed) 0.890 -0.924 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X142Y107 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][15]/C
+ clock pessimism 0.280 -0.644
+ SLICE_X142Y107 FDCE (Hold_fdce_C_D) 0.076 -0.568 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][15]
-------------------------------------------------------------------
- required time 0.544
- arrival time -0.384
+ required time 0.568
+ arrival time -0.415
-------------------------------------------------------------------
- slack 0.160
+ slack 0.153
-Slack (MET) : 0.168ns (arrival time - required time)
- Source: audio_inout/D_L_O_int_reg[1]/C
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: audio_inout/Data_Out_int_reg[8]/D
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+Slack (MET) : 0.162ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][10]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][10]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.297ns (logic 0.186ns (62.622%) route 0.111ns (37.378%))
- Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.037ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.925ns
- Source Clock Delay (SCD): -0.682ns
- Clock Pessimism Removal (CPR): -0.280ns
+ Data Path Delay: 0.253ns (logic 0.141ns (55.664%) route 0.112ns (44.336%))
+ Logic Levels: 0
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.921ns
+ Source Clock Delay (SCD): -0.679ns
+ Clock Pessimism Removal (CPR): -0.258ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1346,14 +1394,12 @@ Slack (MET) : 0.168ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.618 -0.682 audio_inout/clk_out1
- SLICE_X153Y112 FDRE r audio_inout/D_L_O_int_reg[1]/C
+ net (fo=773, routed) 0.621 -0.679 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X151Y102 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][10]/C
------------------------------------------------------------------- -------------------
- SLICE_X153Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r audio_inout/D_L_O_int_reg[1]/Q
- net (fo=1, routed) 0.111 -0.430 audio_inout/in_audioL[1]
- SLICE_X155Y112 LUT6 (Prop_lut6_I1_O) 0.045 -0.385 r audio_inout/Data_Out_int[8]_i_1/O
- net (fo=1, routed) 0.000 -0.385 audio_inout/Data_Out_int[8]_i_1_n_0
- SLICE_X155Y112 FDRE r audio_inout/Data_Out_int_reg[8]/D
+ SLICE_X151Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.538 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][10]/Q
+ net (fo=2, routed) 0.112 -0.425 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1]_2[10]
+ SLICE_X148Y102 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][10]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1366,30 +1412,30 @@ Slack (MET) : 0.168ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.889 -0.925 audio_inout/clk_out1
- SLICE_X155Y112 FDRE r audio_inout/Data_Out_int_reg[8]/C
- clock pessimism 0.280 -0.645
- SLICE_X155Y112 FDRE (Hold_fdre_C_D) 0.092 -0.553 audio_inout/Data_Out_int_reg[8]
+ net (fo=773, routed) 0.893 -0.921 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y102 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][10]/C
+ clock pessimism 0.258 -0.663
+ SLICE_X148Y102 FDCE (Hold_fdce_C_D) 0.075 -0.588 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][10]
-------------------------------------------------------------------
- required time 0.553
- arrival time -0.385
+ required time 0.588
+ arrival time -0.425
-------------------------------------------------------------------
- slack 0.168
+ slack 0.162
-Slack (MET) : 0.172ns (arrival time - required time)
- Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][4]/C
- (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]/D
+Slack (MET) : 0.167ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[8]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.232ns (logic 0.164ns (70.680%) route 0.068ns (29.320%))
- Logic Levels: 0
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.923ns
- Source Clock Delay (SCD): -0.681ns
- Clock Pessimism Removal (CPR): -0.242ns
+ Data Path Delay: 0.625ns (logic 0.226ns (36.177%) route 0.399ns (63.823%))
+ Logic Levels: 1 (LUT5=1)
+ Clock Path Skew: 0.338ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.851ns
+ Source Clock Delay (SCD): -0.680ns
+ Clock Pessimism Removal (CPR): -0.509ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1403,12 +1449,14 @@ Slack (MET) : 0.172ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.619 -0.681 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X148Y107 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][4]/C
+ net (fo=773, routed) 0.620 -0.680 audio_inout/clk_out1
+ SLICE_X149Y105 FDRE r audio_inout/D_L_O_int_reg[8]/C
------------------------------------------------------------------- -------------------
- SLICE_X148Y107 FDCE (Prop_fdce_C_Q) 0.164 -0.517 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][4]/Q
- net (fo=2, routed) 0.068 -0.449 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[4]
- SLICE_X148Y107 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]/D
+ SLICE_X149Y105 FDRE (Prop_fdre_C_Q) 0.128 -0.552 r audio_inout/D_L_O_int_reg[8]/Q
+ net (fo=2, routed) 0.399 -0.153 audio_inout/Q[0]
+ SLICE_X146Y98 LUT5 (Prop_lut5_I0_O) 0.098 -0.055 r audio_inout/SR_shiftRegister[0][0]_i_1/O
+ net (fo=1, routed) 0.000 -0.055 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]_0[0]
+ SLICE_X146Y98 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1421,30 +1469,30 @@ Slack (MET) : 0.172ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.891 -0.923 leftFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X148Y107 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]/C
- clock pessimism 0.242 -0.681
- SLICE_X148Y107 FDCE (Hold_fdce_C_D) 0.060 -0.621 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]
+ net (fo=773, routed) 0.963 -0.851 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y98 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]/C
+ clock pessimism 0.509 -0.342
+ SLICE_X146Y98 FDCE (Hold_fdce_C_D) 0.120 -0.222 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]
-------------------------------------------------------------------
- required time 0.621
- arrival time -0.449
+ required time 0.222
+ arrival time -0.055
-------------------------------------------------------------------
- slack 0.172
+ slack 0.167
-Slack (MET) : 0.172ns (arrival time - required time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][11]/C
+Slack (MET) : 0.167ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][13]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][13]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.232ns (logic 0.164ns (70.680%) route 0.068ns (29.320%))
+ Data Path Delay: 0.255ns (logic 0.141ns (55.298%) route 0.114ns (44.702%))
Logic Levels: 0
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.921ns
- Source Clock Delay (SCD): -0.679ns
- Clock Pessimism Removal (CPR): -0.242ns
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.948ns
+ Source Clock Delay (SCD): -0.705ns
+ Clock Pessimism Removal (CPR): -0.259ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1458,12 +1506,12 @@ Slack (MET) : 0.172ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.621 -0.679 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X154Y104 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][11]/C
+ net (fo=773, routed) 0.595 -0.705 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X137Y104 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][13]/C
------------------------------------------------------------------- -------------------
- SLICE_X154Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.515 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][11]/Q
- net (fo=2, routed) 0.068 -0.447 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[11]
- SLICE_X154Y104 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]/D
+ SLICE_X137Y104 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][13]/Q
+ net (fo=2, routed) 0.114 -0.450 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14]_15[13]
+ SLICE_X138Y104 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][13]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1476,30 +1524,30 @@ Slack (MET) : 0.172ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.893 -0.921 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X154Y104 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]/C
- clock pessimism 0.242 -0.679
- SLICE_X154Y104 FDCE (Hold_fdce_C_D) 0.060 -0.619 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]
+ net (fo=773, routed) 0.866 -0.948 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X138Y104 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][13]/C
+ clock pessimism 0.259 -0.689
+ SLICE_X138Y104 FDCE (Hold_fdce_C_D) 0.072 -0.617 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][13]
-------------------------------------------------------------------
- required time 0.619
- arrival time -0.447
+ required time 0.617
+ arrival time -0.450
-------------------------------------------------------------------
- slack 0.172
+ slack 0.167
-Slack (MET) : 0.173ns (arrival time - required time)
- Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+Slack (MET) : 0.168ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][14]/C
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][14]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.265ns (logic 0.141ns (53.133%) route 0.124ns (46.867%))
+ Data Path Delay: 0.257ns (logic 0.141ns (54.847%) route 0.116ns (45.153%))
Logic Levels: 0
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.921ns
- Source Clock Delay (SCD): -0.680ns
- Clock Pessimism Removal (CPR): -0.258ns
+ Destination Clock Delay (DCD): -0.947ns
+ Source Clock Delay (SCD): -0.705ns
+ Clock Pessimism Removal (CPR): -0.259ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1513,12 +1561,12 @@ Slack (MET) : 0.173ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.620 -0.680 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X155Y107 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+ net (fo=773, routed) 0.595 -0.705 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X137Y103 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][14]/C
------------------------------------------------------------------- -------------------
- SLICE_X155Y107 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/Q
- net (fo=2, routed) 0.124 -0.414 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[14]
- SLICE_X154Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+ SLICE_X137Y103 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][14]/Q
+ net (fo=2, routed) 0.116 -0.448 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8]_9[14]
+ SLICE_X138Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][14]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1531,30 +1579,30 @@ Slack (MET) : 0.173ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.893 -0.921 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X154Y106 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/C
- clock pessimism 0.258 -0.663
- SLICE_X154Y106 FDCE (Hold_fdce_C_D) 0.075 -0.588 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]
+ net (fo=773, routed) 0.867 -0.947 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X138Y102 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][14]/C
+ clock pessimism 0.259 -0.688
+ SLICE_X138Y102 FDCE (Hold_fdce_C_D) 0.072 -0.616 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][14]
-------------------------------------------------------------------
- required time 0.588
- arrival time -0.414
+ required time 0.616
+ arrival time -0.448
-------------------------------------------------------------------
- slack 0.173
+ slack 0.168
-Slack (MET) : 0.175ns (arrival time - required time)
- Source: audio_inout/D_R_O_int_reg[15]/C
- (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
- Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/D
+Slack (MET) : 0.172ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]/D
(rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_out1_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.305ns (logic 0.186ns (60.913%) route 0.119ns (39.087%))
- Logic Levels: 1 (LUT2=1)
- Clock Path Skew: 0.038ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.921ns
- Source Clock Delay (SCD): -0.679ns
- Clock Pessimism Removal (CPR): -0.280ns
+ Data Path Delay: 0.232ns (logic 0.164ns (70.680%) route 0.068ns (29.320%))
+ Logic Levels: 0
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.851ns
+ Source Clock Delay (SCD): -0.612ns
+ Clock Pessimism Removal (CPR): -0.239ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -1568,14 +1616,12 @@ Slack (MET) : 0.175ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.621 -0.679 audio_inout/clk_out1
- SLICE_X153Y106 FDRE r audio_inout/D_R_O_int_reg[15]/C
+ net (fo=773, routed) 0.687 -0.612 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][1]/C
------------------------------------------------------------------- -------------------
- SLICE_X153Y106 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r audio_inout/D_R_O_int_reg[15]/Q
- net (fo=2, routed) 0.119 -0.418 audio_inout/D_R_O_int_reg[22]_0[3]
- SLICE_X155Y105 LUT2 (Prop_lut2_I0_O) 0.045 -0.373 r audio_inout/I_inputSample_IBUF[7]_inst_i_1/O
- net (fo=1, routed) 0.000 -0.373 rightFir/firUnit_1/operativeUnit_1/I_inputSample[7]
- SLICE_X155Y105 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/D
+ SLICE_X148Y98 FDCE (Prop_fdce_C_Q) 0.164 -0.448 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][1]/Q
+ net (fo=2, routed) 0.068 -0.380 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[1]
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_clk_wiz_0 rise edge)
@@ -1588,15 +1634,15 @@ Slack (MET) : 0.175ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
- net (fo=773, routed) 0.893 -0.921 rightFir/firUnit_1/operativeUnit_1/clk_out1
- SLICE_X155Y105 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/C
- clock pessimism 0.280 -0.641
- SLICE_X155Y105 FDCE (Hold_fdce_C_D) 0.092 -0.549 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]
+ net (fo=773, routed) 0.963 -0.851 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y98 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]/C
+ clock pessimism 0.239 -0.612
+ SLICE_X148Y98 FDCE (Hold_fdce_C_D) 0.060 -0.552 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]
-------------------------------------------------------------------
- required time 0.549
- arrival time -0.373
+ required time 0.552
+ arrival time -0.380
-------------------------------------------------------------------
- slack 0.175
+ slack 0.172
@@ -1612,35 +1658,35 @@ Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_1/inst/clkout1_buf/I
Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y112 lrclkD1_reg/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y112 lrclkD2_reg/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y111 lrclkcnt_reg[0]/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y111 lrclkcnt_reg[1]/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y111 lrclkcnt_reg[2]/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y111 lrclkcnt_reg[3]/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y112 pulse48kHz_reg/C
-Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X152Y115 audio_inout/BCLK_int_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y108 lrclkD1_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y108 lrclkD2_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X146Y108 lrclkcnt_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X146Y108 lrclkcnt_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X147Y108 lrclkcnt_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X147Y108 lrclkcnt_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y108 pulse48kHz_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y108 audio_inout/BCLK_int_reg/C
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
-Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD1_reg/C
-Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD1_reg/C
-Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD2_reg/C
-Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD2_reg/C
-Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[0]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[0]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[1]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[1]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y111 lrclkcnt_reg[2]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y111 lrclkcnt_reg[2]/C
-High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD1_reg/C
-High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD1_reg/C
-High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD2_reg/C
-High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y112 lrclkD2_reg/C
-High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[0]/C
-High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[0]/C
-High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[1]/C
-High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y111 lrclkcnt_reg[1]/C
-High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y111 lrclkcnt_reg[2]/C
-High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y111 lrclkcnt_reg[2]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD1_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD1_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD2_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD2_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X147Y108 lrclkcnt_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X147Y108 lrclkcnt_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD1_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD1_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD2_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y108 lrclkD2_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X146Y108 lrclkcnt_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X147Y108 lrclkcnt_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X147Y108 lrclkcnt_reg[2]/C
@@ -1672,28 +1718,28 @@ Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 83.333
From Clock: clk_out4_clk_wiz_0
To Clock: clk_out4_clk_wiz_0
-Setup : 0 Failing Endpoints, Worst Slack 14.589ns, Total Violation 0.000ns
-Hold : 0 Failing Endpoints, Worst Slack 0.109ns, Total Violation 0.000ns
+Setup : 0 Failing Endpoints, Worst Slack 14.342ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.132ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
-Slack (MET) : 14.589ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
+Slack (MET) : 14.342ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 5.080ns (logic 1.151ns (22.659%) route 3.929ns (77.341%))
- Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=2)
- Clock Path Skew: -0.032ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.588ns = ( 18.412 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Data Path Delay: 5.372ns (logic 1.185ns (22.060%) route 4.187ns (77.940%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.174ns
@@ -1711,20 +1757,20 @@ Slack (MET) : 14.589ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 0.782 2.285 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X159Y117 LUT4 (Prop_lut4_I3_O) 0.120 2.405 r initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
- net (fo=1, routed) 0.812 3.217 initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
- SLICE_X159Y118 LUT6 (Prop_lut6_I0_O) 0.327 3.544 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
- net (fo=4, routed) 0.533 4.077 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
- SLICE_X159Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=3, routed) 0.796 0.256 initialize_audio/twi_controller/sda_TRI
+ SLICE_X161Y118 LUT3 (Prop_lut3_I2_O) 0.149 0.405 f initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+ net (fo=6, routed) 1.294 1.699 initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+ SLICE_X159Y116 LUT5 (Prop_lut5_I4_O) 0.332 2.031 r initialize_audio/twi_controller/ERR_O_i_2/O
+ net (fo=3, routed) 0.656 2.687 initialize_audio/twi_controller/ERR_O_i_2_n_0
+ SLICE_X160Y115 LUT6 (Prop_lut6_I0_O) 0.124 2.811 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.799 3.610 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X160Y116 LUT6 (Prop_lut6_I1_O) 0.124 3.734 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.641 4.376 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X162Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -1737,31 +1783,31 @@ Slack (MET) : 14.589ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.704 18.412 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
- clock pessimism 0.554 18.965
- clock uncertainty -0.094 18.871
- SLICE_X159Y116 FDRE (Setup_fdre_C_CE) -0.205 18.666 initialize_audio/twi_controller/FSM_gray_state_reg[1]
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[2]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X162Y116 FDRE (Setup_fdre_C_CE) -0.169 18.718 initialize_audio/twi_controller/FSM_gray_state_reg[2]
-------------------------------------------------------------------
- required time 18.666
- arrival time -4.077
+ required time 18.718
+ arrival time -4.376
-------------------------------------------------------------------
- slack 14.589
+ slack 14.342
-Slack (MET) : 14.589ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) : 14.342ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 5.080ns (logic 1.151ns (22.659%) route 3.929ns (77.341%))
- Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=2)
- Clock Path Skew: -0.032ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.588ns = ( 18.412 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Data Path Delay: 5.372ns (logic 1.185ns (22.060%) route 4.187ns (77.940%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.174ns
@@ -1779,20 +1825,20 @@ Slack (MET) : 14.589ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 0.782 2.285 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X159Y117 LUT4 (Prop_lut4_I3_O) 0.120 2.405 r initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
- net (fo=1, routed) 0.812 3.217 initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
- SLICE_X159Y118 LUT6 (Prop_lut6_I0_O) 0.327 3.544 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
- net (fo=4, routed) 0.533 4.077 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
- SLICE_X159Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=3, routed) 0.796 0.256 initialize_audio/twi_controller/sda_TRI
+ SLICE_X161Y118 LUT3 (Prop_lut3_I2_O) 0.149 0.405 f initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+ net (fo=6, routed) 1.294 1.699 initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+ SLICE_X159Y116 LUT5 (Prop_lut5_I4_O) 0.332 2.031 r initialize_audio/twi_controller/ERR_O_i_2/O
+ net (fo=3, routed) 0.656 2.687 initialize_audio/twi_controller/ERR_O_i_2_n_0
+ SLICE_X160Y115 LUT6 (Prop_lut6_I0_O) 0.124 2.811 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.799 3.610 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X160Y116 LUT6 (Prop_lut6_I1_O) 0.124 3.734 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.641 4.376 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X162Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -1805,30 +1851,30 @@ Slack (MET) : 14.589ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.704 18.412 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[3]/C
- clock pessimism 0.554 18.965
- clock uncertainty -0.094 18.871
- SLICE_X159Y116 FDRE (Setup_fdre_C_CE) -0.205 18.666 initialize_audio/twi_controller/FSM_gray_state_reg[3]
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[3]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X162Y116 FDRE (Setup_fdre_C_CE) -0.169 18.718 initialize_audio/twi_controller/FSM_gray_state_reg[3]
-------------------------------------------------------------------
- required time 18.666
- arrival time -4.077
+ required time 18.718
+ arrival time -4.376
-------------------------------------------------------------------
- slack 14.589
+ slack 14.342
-Slack (MET) : 14.619ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+Slack (MET) : 14.605ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[6]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/state_reg[1]/CE
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 5.052ns (logic 1.151ns (22.783%) route 3.901ns (77.217%))
- Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=2)
- Clock Path Skew: -0.030ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
+ Data Path Delay: 5.057ns (logic 0.952ns (18.824%) route 4.105ns (81.176%))
+ Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.583ns = ( 18.417 - 20.000 )
+ Source Clock Delay (SCD): -0.991ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
@@ -1847,20 +1893,20 @@ Slack (MET) : 14.619ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 0.782 2.285 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X159Y117 LUT4 (Prop_lut4_I3_O) 0.120 2.405 r initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
- net (fo=1, routed) 0.812 3.217 initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
- SLICE_X159Y118 LUT6 (Prop_lut6_I0_O) 0.327 3.544 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
- net (fo=4, routed) 0.506 4.049 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
- SLICE_X160Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
+ net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
+ SLICE_X157Y109 FDSE r initialize_audio/delaycnt_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y109 FDSE (Prop_fdse_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[6]/Q
+ net (fo=3, routed) 1.159 0.625 initialize_audio/delaycnt_reg_n_0_[6]
+ SLICE_X156Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.749 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.444 1.193 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X156Y113 LUT5 (Prop_lut5_I4_O) 0.124 1.317 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 1.095 2.412 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X156Y110 LUT4 (Prop_lut4_I3_O) 0.124 2.536 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.778 3.314 initialize_audio/twi_controller/initEn_reg
+ SLICE_X158Y112 LUT6 (Prop_lut6_I1_O) 0.124 3.438 r initialize_audio/twi_controller/state[3]_i_1/O
+ net (fo=4, routed) 0.628 4.067 initialize_audio/twi_controller_n_6
+ SLICE_X161Y112 FDSE r initialize_audio/state_reg[1]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -1873,30 +1919,30 @@ Slack (MET) : 14.619ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
- SLICE_X160Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
- clock pessimism 0.554 18.967
- clock uncertainty -0.094 18.873
- SLICE_X160Y116 FDRE (Setup_fdre_C_CE) -0.205 18.668 initialize_audio/twi_controller/FSM_gray_state_reg[0]
+ net (fo=120, routed) 1.709 18.417 initialize_audio/clk_out4
+ SLICE_X161Y112 FDSE r initialize_audio/state_reg[1]/C
+ clock pessimism 0.554 18.970
+ clock uncertainty -0.094 18.876
+ SLICE_X161Y112 FDSE (Setup_fdse_C_CE) -0.205 18.671 initialize_audio/state_reg[1]
-------------------------------------------------------------------
- required time 18.668
- arrival time -4.049
+ required time 18.671
+ arrival time -4.067
-------------------------------------------------------------------
- slack 14.619
+ slack 14.605
-Slack (MET) : 14.619ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+Slack (MET) : 14.605ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[6]/C
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
+ Destination: initialize_audio/state_reg[3]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 5.052ns (logic 1.151ns (22.783%) route 3.901ns (77.217%))
- Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=2)
- Clock Path Skew: -0.030ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
+ Data Path Delay: 5.057ns (logic 0.952ns (18.824%) route 4.105ns (81.176%))
+ Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.583ns = ( 18.417 - 20.000 )
+ Source Clock Delay (SCD): -0.991ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
@@ -1915,20 +1961,20 @@ Slack (MET) : 14.619ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 0.782 2.285 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X159Y117 LUT4 (Prop_lut4_I3_O) 0.120 2.405 r initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
- net (fo=1, routed) 0.812 3.217 initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
- SLICE_X159Y118 LUT6 (Prop_lut6_I0_O) 0.327 3.544 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
- net (fo=4, routed) 0.506 4.049 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
- SLICE_X160Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
+ net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
+ SLICE_X157Y109 FDSE r initialize_audio/delaycnt_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y109 FDSE (Prop_fdse_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[6]/Q
+ net (fo=3, routed) 1.159 0.625 initialize_audio/delaycnt_reg_n_0_[6]
+ SLICE_X156Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.749 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.444 1.193 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X156Y113 LUT5 (Prop_lut5_I4_O) 0.124 1.317 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 1.095 2.412 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X156Y110 LUT4 (Prop_lut4_I3_O) 0.124 2.536 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.778 3.314 initialize_audio/twi_controller/initEn_reg
+ SLICE_X158Y112 LUT6 (Prop_lut6_I1_O) 0.124 3.438 r initialize_audio/twi_controller/state[3]_i_1/O
+ net (fo=4, routed) 0.628 4.067 initialize_audio/twi_controller_n_6
+ SLICE_X161Y112 FDRE r initialize_audio/state_reg[3]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -1941,31 +1987,31 @@ Slack (MET) : 14.619ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
- SLICE_X160Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[2]/C
- clock pessimism 0.554 18.967
- clock uncertainty -0.094 18.873
- SLICE_X160Y116 FDRE (Setup_fdre_C_CE) -0.205 18.668 initialize_audio/twi_controller/FSM_gray_state_reg[2]
+ net (fo=120, routed) 1.709 18.417 initialize_audio/clk_out4
+ SLICE_X161Y112 FDRE r initialize_audio/state_reg[3]/C
+ clock pessimism 0.554 18.970
+ clock uncertainty -0.094 18.876
+ SLICE_X161Y112 FDRE (Setup_fdre_C_CE) -0.205 18.671 initialize_audio/state_reg[3]
-------------------------------------------------------------------
- required time 18.668
- arrival time -4.049
+ required time 18.671
+ arrival time -4.067
-------------------------------------------------------------------
- slack 14.619
+ slack 14.605
-Slack (MET) : 14.696ns (required time - arrival time)
- Source: initialize_audio/delaycnt_reg[4]/C
+Slack (MET) : 14.746ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/state_reg[1]/CE
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 4.965ns (logic 0.952ns (19.176%) route 4.013ns (80.824%))
- Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
- Clock Path Skew: -0.040ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
- Source Clock Delay (SCD): -0.991ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Data Path Delay: 4.932ns (logic 1.185ns (24.027%) route 3.747ns (75.973%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.174ns
@@ -1983,20 +2029,20 @@ Slack (MET) : 14.696ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
- SLICE_X156Y109 FDRE r initialize_audio/delaycnt_reg[4]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y109 FDRE (Prop_fdre_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[4]/Q
- net (fo=3, routed) 0.833 0.298 initialize_audio/delaycnt_reg_n_0_[4]
- SLICE_X157Y110 LUT4 (Prop_lut4_I0_O) 0.124 0.422 f initialize_audio/initA[6]_i_13/O
- net (fo=1, routed) 0.877 1.299 initialize_audio/initA[6]_i_13_n_0
- SLICE_X157Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.423 r initialize_audio/initA[6]_i_9/O
- net (fo=1, routed) 0.781 2.204 initialize_audio/initA[6]_i_9_n_0
- SLICE_X157Y113 LUT4 (Prop_lut4_I1_O) 0.124 2.328 r initialize_audio/initA[6]_i_4/O
- net (fo=4, routed) 0.805 3.133 initialize_audio/twi_controller/initEn_reg
- SLICE_X158Y113 LUT6 (Prop_lut6_I1_O) 0.124 3.257 r initialize_audio/twi_controller/state[3]_i_1/O
- net (fo=4, routed) 0.717 3.974 initialize_audio/twi_controller_n_6
- SLICE_X160Y113 FDSE r initialize_audio/state_reg[1]/CE
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=3, routed) 0.796 0.256 initialize_audio/twi_controller/sda_TRI
+ SLICE_X161Y118 LUT3 (Prop_lut3_I2_O) 0.149 0.405 f initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+ net (fo=6, routed) 1.294 1.699 initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+ SLICE_X159Y116 LUT5 (Prop_lut5_I4_O) 0.332 2.031 r initialize_audio/twi_controller/ERR_O_i_2/O
+ net (fo=3, routed) 0.656 2.687 initialize_audio/twi_controller/ERR_O_i_2_n_0
+ SLICE_X160Y115 LUT6 (Prop_lut6_I0_O) 0.124 2.811 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.799 3.610 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X160Y116 LUT6 (Prop_lut6_I1_O) 0.124 3.734 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.202 3.936 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X161Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2009,31 +2055,31 @@ Slack (MET) : 14.696ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.708 18.416 initialize_audio/clk_out4
- SLICE_X160Y113 FDSE r initialize_audio/state_reg[1]/C
- clock pessimism 0.554 18.969
- clock uncertainty -0.094 18.875
- SLICE_X160Y113 FDSE (Setup_fdse_C_CE) -0.205 18.670 initialize_audio/state_reg[1]
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X161Y116 FDRE (Setup_fdre_C_CE) -0.205 18.682 initialize_audio/twi_controller/FSM_gray_state_reg[0]
-------------------------------------------------------------------
- required time 18.670
- arrival time -3.974
+ required time 18.682
+ arrival time -3.936
-------------------------------------------------------------------
- slack 14.696
+ slack 14.746
-Slack (MET) : 14.712ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/dataByte_reg[1]/CE
+Slack (MET) : 14.746ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 4.960ns (logic 0.952ns (19.193%) route 4.008ns (80.807%))
- Logic Levels: 4 (LUT2=2 LUT6=2)
- Clock Path Skew: -0.029ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Data Path Delay: 4.932ns (logic 1.185ns (24.027%) route 3.747ns (75.973%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.174ns
@@ -2051,20 +2097,20 @@ Slack (MET) : 14.712ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 1.002 2.505 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X158Y117 LUT6 (Prop_lut6_I3_O) 0.124 2.629 r initialize_audio/twi_controller/dataByte[7]_i_3/O
- net (fo=4, routed) 0.478 3.107 initialize_audio/twi_controller/dataByte0
- SLICE_X158Y117 LUT2 (Prop_lut2_I0_O) 0.124 3.231 r initialize_audio/twi_controller/dataByte[7]_i_1/O
- net (fo=8, routed) 0.727 3.957 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/CE
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=3, routed) 0.796 0.256 initialize_audio/twi_controller/sda_TRI
+ SLICE_X161Y118 LUT3 (Prop_lut3_I2_O) 0.149 0.405 f initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+ net (fo=6, routed) 1.294 1.699 initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+ SLICE_X159Y116 LUT5 (Prop_lut5_I4_O) 0.332 2.031 r initialize_audio/twi_controller/ERR_O_i_2/O
+ net (fo=3, routed) 0.656 2.687 initialize_audio/twi_controller/ERR_O_i_2_n_0
+ SLICE_X160Y115 LUT6 (Prop_lut6_I0_O) 0.124 2.811 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.799 3.610 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X160Y116 LUT6 (Prop_lut6_I1_O) 0.124 3.734 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.202 3.936 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X161Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2077,31 +2123,31 @@ Slack (MET) : 14.712ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.707 18.415 initialize_audio/twi_controller/clk_out4
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/C
- clock pessimism 0.554 18.968
- clock uncertainty -0.094 18.874
- SLICE_X161Y115 FDRE (Setup_fdre_C_CE) -0.205 18.669 initialize_audio/twi_controller/dataByte_reg[1]
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X161Y116 FDRE (Setup_fdre_C_CE) -0.205 18.682 initialize_audio/twi_controller/FSM_gray_state_reg[1]
-------------------------------------------------------------------
- required time 18.669
- arrival time -3.957
+ required time 18.682
+ arrival time -3.936
-------------------------------------------------------------------
- slack 14.712
+ slack 14.746
-Slack (MET) : 14.712ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+Slack (MET) : 14.890ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[6]/C
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/dataByte_reg[6]/CE
+ Destination: initialize_audio/state_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 4.960ns (logic 0.952ns (19.193%) route 4.008ns (80.807%))
- Logic Levels: 4 (LUT2=2 LUT6=2)
- Clock Path Skew: -0.029ns (DCD - SCD + CPR)
+ Data Path Delay: 4.820ns (logic 0.952ns (19.751%) route 3.868ns (80.249%))
+ Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
+ Clock Path Skew: -0.027ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Source Clock Delay (SCD): -0.991ns
+ Clock Pessimism Removal (CPR): 0.568ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.174ns
@@ -2119,20 +2165,20 @@ Slack (MET) : 14.712ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 1.002 2.505 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X158Y117 LUT6 (Prop_lut6_I3_O) 0.124 2.629 r initialize_audio/twi_controller/dataByte[7]_i_3/O
- net (fo=4, routed) 0.478 3.107 initialize_audio/twi_controller/dataByte0
- SLICE_X158Y117 LUT2 (Prop_lut2_I0_O) 0.124 3.231 r initialize_audio/twi_controller/dataByte[7]_i_1/O
- net (fo=8, routed) 0.727 3.957 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/CE
+ net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
+ SLICE_X157Y109 FDSE r initialize_audio/delaycnt_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y109 FDSE (Prop_fdse_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[6]/Q
+ net (fo=3, routed) 1.159 0.625 initialize_audio/delaycnt_reg_n_0_[6]
+ SLICE_X156Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.749 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.444 1.193 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X156Y113 LUT5 (Prop_lut5_I4_O) 0.124 1.317 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 1.095 2.412 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X156Y110 LUT4 (Prop_lut4_I3_O) 0.124 2.536 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.778 3.314 initialize_audio/twi_controller/initEn_reg
+ SLICE_X158Y112 LUT6 (Prop_lut6_I1_O) 0.124 3.438 r initialize_audio/twi_controller/state[3]_i_1/O
+ net (fo=4, routed) 0.391 3.829 initialize_audio/twi_controller_n_6
+ SLICE_X158Y112 FDRE r initialize_audio/state_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2145,31 +2191,31 @@ Slack (MET) : 14.712ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.707 18.415 initialize_audio/twi_controller/clk_out4
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
- clock pessimism 0.554 18.968
- clock uncertainty -0.094 18.874
- SLICE_X161Y115 FDRE (Setup_fdre_C_CE) -0.205 18.669 initialize_audio/twi_controller/dataByte_reg[6]
+ net (fo=120, routed) 1.707 18.415 initialize_audio/clk_out4
+ SLICE_X158Y112 FDRE r initialize_audio/state_reg[0]/C
+ clock pessimism 0.568 18.982
+ clock uncertainty -0.094 18.888
+ SLICE_X158Y112 FDRE (Setup_fdre_C_CE) -0.169 18.719 initialize_audio/state_reg[0]
-------------------------------------------------------------------
- required time 18.669
- arrival time -3.957
+ required time 18.719
+ arrival time -3.829
-------------------------------------------------------------------
- slack 14.712
+ slack 14.890
-Slack (MET) : 14.712ns (required time - arrival time)
- Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+Slack (MET) : 14.890ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[6]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/state_reg[2]/CE
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/dataByte_reg[7]/CE
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 4.960ns (logic 0.952ns (19.193%) route 4.008ns (80.807%))
- Logic Levels: 4 (LUT2=2 LUT6=2)
- Clock Path Skew: -0.029ns (DCD - SCD + CPR)
+ Data Path Delay: 4.820ns (logic 0.952ns (19.751%) route 3.868ns (80.249%))
+ Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
+ Clock Path Skew: -0.027ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
- Source Clock Delay (SCD): -1.003ns
- Clock Pessimism Removal (CPR): 0.554ns
+ Source Clock Delay (SCD): -0.991ns
+ Clock Pessimism Removal (CPR): 0.568ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.174ns
@@ -2187,20 +2233,20 @@ Slack (MET) : 14.712ns (required time - arrival time)
-7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.816 -1.003 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.456 -0.547 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
- net (fo=7, routed) 0.741 0.194 initialize_audio/twi_controller/sclCnt[0]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.124 0.318 f initialize_audio/twi_controller/sclCnt[6]_i_5/O
- net (fo=2, routed) 1.061 1.379 initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
- SLICE_X158Y121 LUT2 (Prop_lut2_I1_O) 0.124 1.503 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
- net (fo=15, routed) 1.002 2.505 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
- SLICE_X158Y117 LUT6 (Prop_lut6_I3_O) 0.124 2.629 r initialize_audio/twi_controller/dataByte[7]_i_3/O
- net (fo=4, routed) 0.478 3.107 initialize_audio/twi_controller/dataByte0
- SLICE_X158Y117 LUT2 (Prop_lut2_I0_O) 0.124 3.231 r initialize_audio/twi_controller/dataByte[7]_i_1/O
- net (fo=8, routed) 0.727 3.957 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/CE
+ net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
+ SLICE_X157Y109 FDSE r initialize_audio/delaycnt_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y109 FDSE (Prop_fdse_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[6]/Q
+ net (fo=3, routed) 1.159 0.625 initialize_audio/delaycnt_reg_n_0_[6]
+ SLICE_X156Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.749 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.444 1.193 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X156Y113 LUT5 (Prop_lut5_I4_O) 0.124 1.317 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 1.095 2.412 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X156Y110 LUT4 (Prop_lut4_I3_O) 0.124 2.536 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.778 3.314 initialize_audio/twi_controller/initEn_reg
+ SLICE_X158Y112 LUT6 (Prop_lut6_I1_O) 0.124 3.438 r initialize_audio/twi_controller/state[3]_i_1/O
+ net (fo=4, routed) 0.391 3.829 initialize_audio/twi_controller_n_6
+ SLICE_X158Y112 FDSE r initialize_audio/state_reg[2]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2213,29 +2259,29 @@ Slack (MET) : 14.712ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.707 18.415 initialize_audio/twi_controller/clk_out4
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/C
- clock pessimism 0.554 18.968
- clock uncertainty -0.094 18.874
- SLICE_X161Y115 FDRE (Setup_fdre_C_CE) -0.205 18.669 initialize_audio/twi_controller/dataByte_reg[7]
+ net (fo=120, routed) 1.707 18.415 initialize_audio/clk_out4
+ SLICE_X158Y112 FDSE r initialize_audio/state_reg[2]/C
+ clock pessimism 0.568 18.982
+ clock uncertainty -0.094 18.888
+ SLICE_X158Y112 FDSE (Setup_fdse_C_CE) -0.169 18.719 initialize_audio/state_reg[2]
-------------------------------------------------------------------
- required time 18.669
- arrival time -3.957
+ required time 18.719
+ arrival time -3.829
-------------------------------------------------------------------
- slack 14.712
+ slack 14.890
-Slack (MET) : 14.772ns (required time - arrival time)
- Source: initialize_audio/delaycnt_reg[4]/C
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/initA_reg[0]/CE
+Slack (MET) : 14.913ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[6]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[6]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 4.891ns (logic 0.952ns (19.463%) route 3.939ns (80.537%))
+ Data Path Delay: 4.785ns (logic 0.952ns (19.896%) route 3.833ns (80.104%))
Logic Levels: 4 (LUT4=2 LUT5=2)
- Clock Path Skew: -0.038ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.583ns = ( 18.417 - 20.000 )
Source Clock Delay (SCD): -0.991ns
Clock Pessimism Removal (CPR): 0.554ns
Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
@@ -2256,19 +2302,19 @@ Slack (MET) : 14.772ns (required time - arrival time)
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
- SLICE_X156Y109 FDRE r initialize_audio/delaycnt_reg[4]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y109 FDRE (Prop_fdre_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[4]/Q
- net (fo=3, routed) 0.833 0.298 initialize_audio/delaycnt_reg_n_0_[4]
- SLICE_X157Y110 LUT4 (Prop_lut4_I0_O) 0.124 0.422 f initialize_audio/initA[6]_i_13/O
- net (fo=1, routed) 0.877 1.299 initialize_audio/initA[6]_i_13_n_0
- SLICE_X157Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.423 r initialize_audio/initA[6]_i_9/O
- net (fo=1, routed) 0.781 2.204 initialize_audio/initA[6]_i_9_n_0
- SLICE_X157Y113 LUT4 (Prop_lut4_I1_O) 0.124 2.328 r initialize_audio/initA[6]_i_4/O
- net (fo=4, routed) 0.822 3.150 initialize_audio/twi_controller/initEn_reg
- SLICE_X158Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.274 r initialize_audio/twi_controller/initA[6]_i_2/O
- net (fo=7, routed) 0.627 3.900 initialize_audio/twi_controller_n_8
- SLICE_X160Y111 FDRE r initialize_audio/initA_reg[0]/CE
+ SLICE_X157Y109 FDSE r initialize_audio/delaycnt_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y109 FDSE (Prop_fdse_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[6]/Q
+ net (fo=3, routed) 1.159 0.625 initialize_audio/delaycnt_reg_n_0_[6]
+ SLICE_X156Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.749 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.444 1.193 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X156Y113 LUT5 (Prop_lut5_I4_O) 0.124 1.317 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 1.095 2.412 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X156Y110 LUT4 (Prop_lut4_I3_O) 0.124 2.536 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.638 3.174 initialize_audio/twi_controller/initEn_reg
+ SLICE_X158Y111 LUT5 (Prop_lut5_I1_O) 0.124 3.298 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.496 3.794 initialize_audio/twi_controller_n_8
+ SLICE_X162Y112 FDRE r initialize_audio/initA_reg[6]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2281,26 +2327,26 @@ Slack (MET) : 14.772ns (required time - arrival time)
-7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
- SLICE_X160Y111 FDRE r initialize_audio/initA_reg[0]/C
- clock pessimism 0.554 18.971
- clock uncertainty -0.094 18.877
- SLICE_X160Y111 FDRE (Setup_fdre_C_CE) -0.205 18.672 initialize_audio/initA_reg[0]
+ net (fo=120, routed) 1.709 18.417 initialize_audio/clk_out4
+ SLICE_X162Y112 FDRE r initialize_audio/initA_reg[6]/C
+ clock pessimism 0.554 18.970
+ clock uncertainty -0.094 18.876
+ SLICE_X162Y112 FDRE (Setup_fdre_C_CE) -0.169 18.707 initialize_audio/initA_reg[6]
-------------------------------------------------------------------
- required time 18.672
- arrival time -3.900
+ required time 18.707
+ arrival time -3.794
-------------------------------------------------------------------
- slack 14.772
+ slack 14.913
-Slack (MET) : 14.772ns (required time - arrival time)
- Source: initialize_audio/delaycnt_reg[4]/C
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/initA_reg[2]/CE
+Slack (MET) : 15.027ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[6]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 4.891ns (logic 0.952ns (19.463%) route 3.939ns (80.537%))
+ Data Path Delay: 4.636ns (logic 0.952ns (20.536%) route 3.684ns (79.464%))
Logic Levels: 4 (LUT4=2 LUT5=2)
Clock Path Skew: -0.038ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
@@ -2324,19 +2370,19 @@ Slack (MET) : 14.772ns (required time - arrival time)
net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
net (fo=120, routed) 1.828 -0.991 initialize_audio/clk_out4
- SLICE_X156Y109 FDRE r initialize_audio/delaycnt_reg[4]/C
- ------------------------------------------------------------------- -------------------
- SLICE_X156Y109 FDRE (Prop_fdre_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[4]/Q
- net (fo=3, routed) 0.833 0.298 initialize_audio/delaycnt_reg_n_0_[4]
- SLICE_X157Y110 LUT4 (Prop_lut4_I0_O) 0.124 0.422 f initialize_audio/initA[6]_i_13/O
- net (fo=1, routed) 0.877 1.299 initialize_audio/initA[6]_i_13_n_0
- SLICE_X157Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.423 r initialize_audio/initA[6]_i_9/O
- net (fo=1, routed) 0.781 2.204 initialize_audio/initA[6]_i_9_n_0
- SLICE_X157Y113 LUT4 (Prop_lut4_I1_O) 0.124 2.328 r initialize_audio/initA[6]_i_4/O
- net (fo=4, routed) 0.822 3.150 initialize_audio/twi_controller/initEn_reg
- SLICE_X158Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.274 r initialize_audio/twi_controller/initA[6]_i_2/O
- net (fo=7, routed) 0.627 3.900 initialize_audio/twi_controller_n_8
- SLICE_X160Y111 FDRE r initialize_audio/initA_reg[2]/CE
+ SLICE_X157Y109 FDSE r initialize_audio/delaycnt_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y109 FDSE (Prop_fdse_C_Q) 0.456 -0.535 f initialize_audio/delaycnt_reg[6]/Q
+ net (fo=3, routed) 1.159 0.625 initialize_audio/delaycnt_reg_n_0_[6]
+ SLICE_X156Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.749 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.444 1.193 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X156Y113 LUT5 (Prop_lut5_I4_O) 0.124 1.317 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 1.095 2.412 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X156Y110 LUT4 (Prop_lut4_I3_O) 0.124 2.536 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.638 3.174 initialize_audio/twi_controller/initEn_reg
+ SLICE_X158Y111 LUT5 (Prop_lut5_I1_O) 0.124 3.298 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.347 3.645 initialize_audio/twi_controller_n_8
+ SLICE_X160Y111 FDRE r initialize_audio/initA_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2350,15 +2396,15 @@ Slack (MET) : 14.772ns (required time - arrival time)
net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
- SLICE_X160Y111 FDRE r initialize_audio/initA_reg[2]/C
+ SLICE_X160Y111 FDRE r initialize_audio/initA_reg[0]/C
clock pessimism 0.554 18.971
clock uncertainty -0.094 18.877
- SLICE_X160Y111 FDRE (Setup_fdre_C_CE) -0.205 18.672 initialize_audio/initA_reg[2]
+ SLICE_X160Y111 FDRE (Setup_fdre_C_CE) -0.205 18.672 initialize_audio/initA_reg[0]
-------------------------------------------------------------------
required time 18.672
- arrival time -3.900
+ arrival time -3.645
-------------------------------------------------------------------
- slack 14.772
+ slack 15.027
@@ -2366,20 +2412,20 @@ Slack (MET) : 14.772ns (required time - arrival time)
Min Delay Paths
--------------------------------------------------------------------------------------
-Slack (MET) : 0.109ns (arrival time - required time)
- Source: initialize_audio/twi_controller/dataByte_reg[4]/C
+Slack (MET) : 0.132ns (arrival time - required time)
+ Source: initialize_audio/data_i_reg[5]/C
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: initialize_audio/twi_controller/dataByte_reg[5]/D
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.242ns (logic 0.186ns (76.827%) route 0.056ns (23.173%))
+ Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.900ns
- Source Clock Delay (SCD): -0.657ns
- Clock Pessimism Removal (CPR): -0.256ns
+ Destination Clock Delay (DCD): -0.898ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.255ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2393,14 +2439,14 @@ Slack (MET) : 0.109ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[4]/C
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/data_i_reg[5]/C
------------------------------------------------------------------- -------------------
- SLICE_X159Y115 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/dataByte_reg[4]/Q
- net (fo=1, routed) 0.056 -0.460 initialize_audio/twi_controller/dataByte[4]
- SLICE_X158Y115 LUT4 (Prop_lut4_I0_O) 0.045 -0.415 r initialize_audio/twi_controller/dataByte[5]_i_1/O
- net (fo=1, routed) 0.000 -0.415 initialize_audio/twi_controller/p_1_in[5]
- SLICE_X158Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/D
+ SLICE_X160Y113 FDRE (Prop_fdre_C_Q) 0.141 -0.515 r initialize_audio/data_i_reg[5]/Q
+ net (fo=1, routed) 0.051 -0.464 initialize_audio/twi_controller/dataByte_reg[5]_0
+ SLICE_X161Y113 LUT4 (Prop_lut4_I2_O) 0.045 -0.419 r initialize_audio/twi_controller/dataByte[5]_i_1/O
+ net (fo=1, routed) 0.000 -0.419 initialize_audio/twi_controller/p_1_in[5]
+ SLICE_X161Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2413,30 +2459,30 @@ Slack (MET) : 0.109ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.914 -0.900 initialize_audio/twi_controller/clk_out4
- SLICE_X158Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/C
- clock pessimism 0.256 -0.644
- SLICE_X158Y115 FDRE (Hold_fdre_C_D) 0.120 -0.524 initialize_audio/twi_controller/dataByte_reg[5]
+ net (fo=120, routed) 0.916 -0.898 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/C
+ clock pessimism 0.255 -0.643
+ SLICE_X161Y113 FDRE (Hold_fdre_C_D) 0.092 -0.551 initialize_audio/twi_controller/dataByte_reg[5]
-------------------------------------------------------------------
- required time 0.524
- arrival time -0.415
+ required time 0.551
+ arrival time -0.419
-------------------------------------------------------------------
- slack 0.109
+ slack 0.132
-Slack (MET) : 0.178ns (arrival time - required time)
- Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/sclCnt_reg[4]/D
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) : 0.148ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[3]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[3]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.283ns (logic 0.186ns (65.639%) route 0.097ns (34.361%))
- Logic Levels: 1 (LUT5=1)
+ Data Path Delay: 0.252ns (logic 0.186ns (73.783%) route 0.066ns (26.217%))
+ Logic Levels: 1 (LUT6=1)
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.906ns
- Source Clock Delay (SCD): -0.663ns
- Clock Pessimism Removal (CPR): -0.256ns
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.254ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2450,14 +2496,14 @@ Slack (MET) : 0.178ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.637 -0.663 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X160Y110 FDRE r initialize_audio/initWord_reg[3]/C
------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.141 -0.522 r initialize_audio/twi_controller/sclCnt_reg[2]/Q
- net (fo=5, routed) 0.097 -0.424 initialize_audio/twi_controller/sclCnt[2]
- SLICE_X157Y128 LUT5 (Prop_lut5_I1_O) 0.045 -0.379 r initialize_audio/twi_controller/sclCnt[4]_i_1/O
- net (fo=1, routed) 0.000 -0.379 initialize_audio/twi_controller/sclCnt[4]_i_1_n_0
- SLICE_X157Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[4]/D
+ SLICE_X160Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initWord_reg[3]/Q
+ net (fo=2, routed) 0.066 -0.447 initialize_audio/initWord_reg_n_0_[3]
+ SLICE_X161Y110 LUT6 (Prop_lut6_I4_O) 0.045 -0.402 r initialize_audio/data_i[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.402 initialize_audio/data_i[3]_i_1_n_0
+ SLICE_X161Y110 FDRE r initialize_audio/data_i_reg[3]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2470,30 +2516,30 @@ Slack (MET) : 0.178ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.908 -0.906 initialize_audio/twi_controller/clk_out4
- SLICE_X157Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[4]/C
- clock pessimism 0.256 -0.650
- SLICE_X157Y128 FDSE (Hold_fdse_C_D) 0.092 -0.558 initialize_audio/twi_controller/sclCnt_reg[4]
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X161Y110 FDRE r initialize_audio/data_i_reg[3]/C
+ clock pessimism 0.254 -0.641
+ SLICE_X161Y110 FDRE (Hold_fdre_C_D) 0.091 -0.550 initialize_audio/data_i_reg[3]
-------------------------------------------------------------------
- required time 0.558
- arrival time -0.379
+ required time 0.550
+ arrival time -0.402
-------------------------------------------------------------------
- slack 0.178
+ slack 0.148
-Slack (MET) : 0.180ns (arrival time - required time)
- Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/sclCnt_reg[3]/D
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) : 0.164ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[1]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.284ns (logic 0.186ns (65.408%) route 0.098ns (34.592%))
- Logic Levels: 1 (LUT4=1)
- Clock Path Skew: 0.013ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.906ns
- Source Clock Delay (SCD): -0.663ns
- Clock Pessimism Removal (CPR): -0.256ns
+ Data Path Delay: 0.300ns (logic 0.186ns (61.937%) route 0.114ns (38.063%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.257ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2507,14 +2553,14 @@ Slack (MET) : 0.180ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.637 -0.663 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X161Y111 FDRE r initialize_audio/initWord_reg[17]/C
------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.141 -0.522 r initialize_audio/twi_controller/sclCnt_reg[2]/Q
- net (fo=5, routed) 0.098 -0.423 initialize_audio/twi_controller/sclCnt[2]
- SLICE_X157Y128 LUT4 (Prop_lut4_I0_O) 0.045 -0.378 r initialize_audio/twi_controller/sclCnt[3]_i_1/O
- net (fo=1, routed) 0.000 -0.378 initialize_audio/twi_controller/sclCnt01_in[3]
- SLICE_X157Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[3]/D
+ SLICE_X161Y111 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.114 -0.398 initialize_audio/data1[1]
+ SLICE_X162Y111 LUT6 (Prop_lut6_I5_O) 0.045 -0.353 r initialize_audio/data_i[1]_i_1/O
+ net (fo=1, routed) 0.000 -0.353 initialize_audio/data_i[1]_i_1_n_0
+ SLICE_X162Y111 FDRE r initialize_audio/data_i_reg[1]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2527,30 +2573,30 @@ Slack (MET) : 0.180ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.908 -0.906 initialize_audio/twi_controller/clk_out4
- SLICE_X157Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[3]/C
- clock pessimism 0.256 -0.650
- SLICE_X157Y128 FDSE (Hold_fdse_C_D) 0.091 -0.559 initialize_audio/twi_controller/sclCnt_reg[3]
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X162Y111 FDRE r initialize_audio/data_i_reg[1]/C
+ clock pessimism 0.257 -0.638
+ SLICE_X162Y111 FDRE (Hold_fdre_C_D) 0.120 -0.518 initialize_audio/data_i_reg[1]
-------------------------------------------------------------------
- required time 0.559
- arrival time -0.378
+ required time 0.518
+ arrival time -0.353
-------------------------------------------------------------------
- slack 0.180
+ slack 0.164
-Slack (MET) : 0.187ns (arrival time - required time)
- Source: initialize_audio/twi_controller/sclCnt_reg[1]/C
- (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/sclCnt_reg[5]/D
+Slack (MET) : 0.177ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[15]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[7]/D
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.292ns (logic 0.186ns (63.646%) route 0.106ns (36.354%))
+ Data Path Delay: 0.284ns (logic 0.186ns (65.493%) route 0.098ns (34.507%))
Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.013ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.906ns
- Source Clock Delay (SCD): -0.663ns
- Clock Pessimism Removal (CPR): -0.256ns
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.897ns
+ Source Clock Delay (SCD): -0.655ns
+ Clock Pessimism Removal (CPR): -0.257ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2564,14 +2610,14 @@ Slack (MET) : 0.187ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.637 -0.663 initialize_audio/twi_controller/clk_out4
- SLICE_X156Y128 FDSE r initialize_audio/twi_controller/sclCnt_reg[1]/C
+ net (fo=120, routed) 0.645 -0.655 initialize_audio/clk_out4
+ SLICE_X160Y112 FDRE r initialize_audio/initWord_reg[15]/C
------------------------------------------------------------------- -------------------
- SLICE_X156Y128 FDSE (Prop_fdse_C_Q) 0.141 -0.522 r initialize_audio/twi_controller/sclCnt_reg[1]/Q
- net (fo=6, routed) 0.106 -0.416 initialize_audio/twi_controller/sclCnt[1]
- SLICE_X157Y128 LUT6 (Prop_lut6_I2_O) 0.045 -0.371 r initialize_audio/twi_controller/sclCnt[5]_i_1/O
- net (fo=1, routed) 0.000 -0.371 initialize_audio/twi_controller/sclCnt01_in[5]
- SLICE_X157Y128 FDRE r initialize_audio/twi_controller/sclCnt_reg[5]/D
+ SLICE_X160Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.514 r initialize_audio/initWord_reg[15]/Q
+ net (fo=1, routed) 0.098 -0.416 initialize_audio/data2[7]
+ SLICE_X163Y112 LUT6 (Prop_lut6_I2_O) 0.045 -0.371 r initialize_audio/data_i[7]_i_1/O
+ net (fo=1, routed) 0.000 -0.371 initialize_audio/data_i[7]_i_1_n_0
+ SLICE_X163Y112 FDRE r initialize_audio/data_i_reg[7]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2584,30 +2630,30 @@ Slack (MET) : 0.187ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.908 -0.906 initialize_audio/twi_controller/clk_out4
- SLICE_X157Y128 FDRE r initialize_audio/twi_controller/sclCnt_reg[5]/C
- clock pessimism 0.256 -0.650
- SLICE_X157Y128 FDRE (Hold_fdre_C_D) 0.092 -0.558 initialize_audio/twi_controller/sclCnt_reg[5]
+ net (fo=120, routed) 0.917 -0.897 initialize_audio/clk_out4
+ SLICE_X163Y112 FDRE r initialize_audio/data_i_reg[7]/C
+ clock pessimism 0.257 -0.640
+ SLICE_X163Y112 FDRE (Hold_fdre_C_D) 0.092 -0.548 initialize_audio/data_i_reg[7]
-------------------------------------------------------------------
- required time 0.558
+ required time 0.548
arrival time -0.371
-------------------------------------------------------------------
- slack 0.187
+ slack 0.177
-Slack (MET) : 0.189ns (arrival time - required time)
- Source: initialize_audio/twi_controller/dataByte_reg[0]/C
+Slack (MET) : 0.179ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[30]/C
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/dataByte_reg[1]/D
+ Destination: initialize_audio/data_i_reg[6]/D
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.318ns (logic 0.186ns (58.415%) route 0.132ns (41.585%))
- Logic Levels: 1 (LUT4=1)
- Clock Path Skew: 0.038ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.899ns
- Source Clock Delay (SCD): -0.657ns
- Clock Pessimism Removal (CPR): -0.280ns
+ Data Path Delay: 0.285ns (logic 0.186ns (65.263%) route 0.099ns (34.737%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.897ns
+ Source Clock Delay (SCD): -0.655ns
+ Clock Pessimism Removal (CPR): -0.257ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2621,14 +2667,14 @@ Slack (MET) : 0.189ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[0]/C
+ net (fo=120, routed) 0.645 -0.655 initialize_audio/clk_out4
+ SLICE_X160Y112 FDRE r initialize_audio/initWord_reg[30]/C
------------------------------------------------------------------- -------------------
- SLICE_X159Y115 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/dataByte_reg[0]/Q
- net (fo=3, routed) 0.132 -0.383 initialize_audio/twi_controller/dataByte_reg_n_0_[0]
- SLICE_X161Y115 LUT4 (Prop_lut4_I0_O) 0.045 -0.338 r initialize_audio/twi_controller/dataByte[1]_i_1/O
- net (fo=1, routed) 0.000 -0.338 initialize_audio/twi_controller/p_1_in[1]
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/D
+ SLICE_X160Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.514 r initialize_audio/initWord_reg[30]/Q
+ net (fo=1, routed) 0.099 -0.415 initialize_audio/data0[6]
+ SLICE_X163Y112 LUT6 (Prop_lut6_I2_O) 0.045 -0.370 r initialize_audio/data_i[6]_i_1/O
+ net (fo=1, routed) 0.000 -0.370 initialize_audio/data_i[6]_i_1_n_0
+ SLICE_X163Y112 FDRE r initialize_audio/data_i_reg[6]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2641,30 +2687,30 @@ Slack (MET) : 0.189ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.915 -0.899 initialize_audio/twi_controller/clk_out4
- SLICE_X161Y115 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/C
- clock pessimism 0.280 -0.619
- SLICE_X161Y115 FDRE (Hold_fdre_C_D) 0.091 -0.528 initialize_audio/twi_controller/dataByte_reg[1]
+ net (fo=120, routed) 0.917 -0.897 initialize_audio/clk_out4
+ SLICE_X163Y112 FDRE r initialize_audio/data_i_reg[6]/C
+ clock pessimism 0.257 -0.640
+ SLICE_X163Y112 FDRE (Hold_fdre_C_D) 0.091 -0.549 initialize_audio/data_i_reg[6]
-------------------------------------------------------------------
- required time 0.528
- arrival time -0.338
+ required time 0.549
+ arrival time -0.370
-------------------------------------------------------------------
- slack 0.189
+ slack 0.179
-Slack (MET) : 0.198ns (arrival time - required time)
- Source: initialize_audio/initWord_reg[30]/C
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/data_i_reg[6]/D
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) : 0.183ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.304ns (logic 0.209ns (68.711%) route 0.095ns (31.289%))
- Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.015ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.898ns
- Source Clock Delay (SCD): -0.656ns
- Clock Pessimism Removal (CPR): -0.257ns
+ Data Path Delay: 0.288ns (logic 0.186ns (64.606%) route 0.102ns (35.394%))
+ Logic Levels: 1 (LUT5=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.902ns
+ Source Clock Delay (SCD): -0.659ns
+ Clock Pessimism Removal (CPR): -0.256ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2678,14 +2724,14 @@ Slack (MET) : 0.198ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.644 -0.656 initialize_audio/clk_out4
- SLICE_X162Y114 FDRE r initialize_audio/initWord_reg[30]/C
+ net (fo=120, routed) 0.641 -0.659 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y118 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
------------------------------------------------------------------- -------------------
- SLICE_X162Y114 FDRE (Prop_fdre_C_Q) 0.164 -0.492 r initialize_audio/initWord_reg[30]/Q
- net (fo=1, routed) 0.095 -0.397 initialize_audio/data0[6]
- SLICE_X161Y114 LUT6 (Prop_lut6_I2_O) 0.045 -0.352 r initialize_audio/data_i[6]_i_1/O
- net (fo=1, routed) 0.000 -0.352 initialize_audio/data_i[6]_i_1_n_0
- SLICE_X161Y114 FDRE r initialize_audio/data_i_reg[6]/D
+ SLICE_X161Y118 FDSE (Prop_fdse_C_Q) 0.141 -0.518 r initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
+ net (fo=5, routed) 0.102 -0.416 initialize_audio/twi_controller/sel0[2]
+ SLICE_X160Y118 LUT5 (Prop_lut5_I3_O) 0.045 -0.371 r initialize_audio/twi_controller/busFreeCnt[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.371 initialize_audio/twi_controller/busFreeCnt00_in[4]
+ SLICE_X160Y118 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[4]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2698,30 +2744,30 @@ Slack (MET) : 0.198ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.916 -0.898 initialize_audio/clk_out4
- SLICE_X161Y114 FDRE r initialize_audio/data_i_reg[6]/C
- clock pessimism 0.257 -0.641
- SLICE_X161Y114 FDRE (Hold_fdre_C_D) 0.091 -0.550 initialize_audio/data_i_reg[6]
+ net (fo=120, routed) 0.912 -0.902 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y118 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[4]/C
+ clock pessimism 0.256 -0.646
+ SLICE_X160Y118 FDSE (Hold_fdse_C_D) 0.092 -0.554 initialize_audio/twi_controller/busFreeCnt_reg[4]
-------------------------------------------------------------------
- required time 0.550
- arrival time -0.352
+ required time 0.554
+ arrival time -0.371
-------------------------------------------------------------------
- slack 0.198
+ slack 0.183
-Slack (MET) : 0.199ns (arrival time - required time)
+Slack (MET) : 0.185ns (arrival time - required time)
Source: initialize_audio/twi_controller/busFreeCnt_reg[2]/C
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+ Destination: initialize_audio/twi_controller/busFreeCnt_reg[3]/D
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.304ns (logic 0.209ns (68.859%) route 0.095ns (31.141%))
- Logic Levels: 1 (LUT5=1)
+ Data Path Delay: 0.289ns (logic 0.186ns (64.382%) route 0.103ns (35.618%))
+ Logic Levels: 1 (LUT4=1)
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.907ns
- Source Clock Delay (SCD): -0.663ns
- Clock Pessimism Removal (CPR): -0.257ns
+ Destination Clock Delay (DCD): -0.902ns
+ Source Clock Delay (SCD): -0.659ns
+ Clock Pessimism Removal (CPR): -0.256ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2735,14 +2781,14 @@ Slack (MET) : 0.199ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.637 -0.663 initialize_audio/twi_controller/clk_out4
- SLICE_X158Y127 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ net (fo=120, routed) 0.641 -0.659 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y118 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
------------------------------------------------------------------- -------------------
- SLICE_X158Y127 FDSE (Prop_fdse_C_Q) 0.164 -0.499 r initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
- net (fo=5, routed) 0.095 -0.404 initialize_audio/twi_controller/sel0[2]
- SLICE_X159Y127 LUT5 (Prop_lut5_I3_O) 0.045 -0.359 r initialize_audio/twi_controller/busFreeCnt[4]_i_1/O
- net (fo=1, routed) 0.000 -0.359 initialize_audio/twi_controller/busFreeCnt00_in[4]
- SLICE_X159Y127 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+ SLICE_X161Y118 FDSE (Prop_fdse_C_Q) 0.141 -0.518 r initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
+ net (fo=5, routed) 0.103 -0.415 initialize_audio/twi_controller/sel0[2]
+ SLICE_X160Y118 LUT4 (Prop_lut4_I0_O) 0.045 -0.370 r initialize_audio/twi_controller/busFreeCnt[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.370 initialize_audio/twi_controller/busFreeCnt00_in[3]
+ SLICE_X160Y118 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[3]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2755,30 +2801,30 @@ Slack (MET) : 0.199ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.907 -0.907 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y127 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[4]/C
- clock pessimism 0.257 -0.650
- SLICE_X159Y127 FDSE (Hold_fdse_C_D) 0.092 -0.558 initialize_audio/twi_controller/busFreeCnt_reg[4]
+ net (fo=120, routed) 0.912 -0.902 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y118 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[3]/C
+ clock pessimism 0.256 -0.646
+ SLICE_X160Y118 FDSE (Hold_fdse_C_D) 0.091 -0.555 initialize_audio/twi_controller/busFreeCnt_reg[3]
-------------------------------------------------------------------
- required time 0.558
- arrival time -0.359
+ required time 0.555
+ arrival time -0.370
-------------------------------------------------------------------
- slack 0.199
+ slack 0.185
-Slack (MET) : 0.201ns (arrival time - required time)
- Source: initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+Slack (MET) : 0.199ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/busFreeCnt_reg[3]/D
+ Destination: initialize_audio/twi_controller/sclCnt_reg[4]/D
(rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.305ns (logic 0.209ns (68.633%) route 0.096ns (31.367%))
- Logic Levels: 1 (LUT4=1)
+ Data Path Delay: 0.304ns (logic 0.209ns (68.859%) route 0.095ns (31.141%))
+ Logic Levels: 1 (LUT5=1)
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.907ns
- Source Clock Delay (SCD): -0.663ns
- Clock Pessimism Removal (CPR): -0.257ns
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.256ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2792,14 +2838,14 @@ Slack (MET) : 0.201ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.637 -0.663 initialize_audio/twi_controller/clk_out4
- SLICE_X158Y127 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
------------------------------------------------------------------- -------------------
- SLICE_X158Y127 FDSE (Prop_fdse_C_Q) 0.164 -0.499 r initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
- net (fo=5, routed) 0.096 -0.403 initialize_audio/twi_controller/sel0[2]
- SLICE_X159Y127 LUT4 (Prop_lut4_I0_O) 0.045 -0.358 r initialize_audio/twi_controller/busFreeCnt[3]_i_1/O
- net (fo=1, routed) 0.000 -0.358 initialize_audio/twi_controller/busFreeCnt00_in[3]
- SLICE_X159Y127 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[3]/D
+ SLICE_X162Y115 FDSE (Prop_fdse_C_Q) 0.164 -0.492 r initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.095 -0.397 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X163Y115 LUT5 (Prop_lut5_I1_O) 0.045 -0.352 r initialize_audio/twi_controller/sclCnt[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.352 initialize_audio/twi_controller/sclCnt[4]_i_1_n_0
+ SLICE_X163Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[4]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2812,30 +2858,30 @@ Slack (MET) : 0.201ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.907 -0.907 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y127 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[3]/C
- clock pessimism 0.257 -0.650
- SLICE_X159Y127 FDSE (Hold_fdse_C_D) 0.091 -0.559 initialize_audio/twi_controller/busFreeCnt_reg[3]
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[4]/C
+ clock pessimism 0.256 -0.643
+ SLICE_X163Y115 FDSE (Hold_fdse_C_D) 0.092 -0.551 initialize_audio/twi_controller/sclCnt_reg[4]
-------------------------------------------------------------------
- required time 0.559
- arrival time -0.358
+ required time 0.551
+ arrival time -0.352
-------------------------------------------------------------------
- slack 0.201
+ slack 0.199
-Slack (MET) : 0.207ns (arrival time - required time)
- Source: initialize_audio/initWord_reg[17]/C
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/data_i_reg[1]/D
- (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) : 0.201ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/sclCnt_reg[3]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.314ns (logic 0.209ns (66.656%) route 0.105ns (33.344%))
- Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.015ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.898ns
+ Data Path Delay: 0.305ns (logic 0.209ns (68.633%) route 0.096ns (31.367%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
Source Clock Delay (SCD): -0.656ns
- Clock Pessimism Removal (CPR): -0.257ns
+ Clock Pessimism Removal (CPR): -0.256ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2849,14 +2895,14 @@ Slack (MET) : 0.207ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.644 -0.656 initialize_audio/clk_out4
- SLICE_X162Y113 FDRE r initialize_audio/initWord_reg[17]/C
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
------------------------------------------------------------------- -------------------
- SLICE_X162Y113 FDRE (Prop_fdre_C_Q) 0.164 -0.492 r initialize_audio/initWord_reg[17]/Q
- net (fo=2, routed) 0.105 -0.387 initialize_audio/data1[1]
- SLICE_X161Y114 LUT6 (Prop_lut6_I5_O) 0.045 -0.342 r initialize_audio/data_i[1]_i_1/O
- net (fo=1, routed) 0.000 -0.342 initialize_audio/data_i[1]_i_1_n_0
- SLICE_X161Y114 FDRE r initialize_audio/data_i_reg[1]/D
+ SLICE_X162Y115 FDSE (Prop_fdse_C_Q) 0.164 -0.492 r initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.096 -0.396 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X163Y115 LUT4 (Prop_lut4_I0_O) 0.045 -0.351 r initialize_audio/twi_controller/sclCnt[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.351 initialize_audio/twi_controller/sclCnt01_in[3]
+ SLICE_X163Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[3]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2869,30 +2915,30 @@ Slack (MET) : 0.207ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.916 -0.898 initialize_audio/clk_out4
- SLICE_X161Y114 FDRE r initialize_audio/data_i_reg[1]/C
- clock pessimism 0.257 -0.641
- SLICE_X161Y114 FDRE (Hold_fdre_C_D) 0.092 -0.549 initialize_audio/data_i_reg[1]
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[3]/C
+ clock pessimism 0.256 -0.643
+ SLICE_X163Y115 FDSE (Hold_fdse_C_D) 0.091 -0.552 initialize_audio/twi_controller/sclCnt_reg[3]
-------------------------------------------------------------------
- required time 0.549
- arrival time -0.342
+ required time 0.552
+ arrival time -0.351
-------------------------------------------------------------------
- slack 0.207
+ slack 0.201
-Slack (MET) : 0.208ns (arrival time - required time)
- Source: initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+Slack (MET) : 0.201ns (arrival time - required time)
+ Source: initialize_audio/initA_reg[1]/C
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
- Destination: initialize_audio/twi_controller/FSM_gray_state_reg[1]/D
+ Destination: initialize_audio/initWord_reg[9]/D
(rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: clk_out4_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
- Data Path Delay: 0.335ns (logic 0.186ns (55.563%) route 0.149ns (44.437%))
+ Data Path Delay: 0.306ns (logic 0.186ns (60.848%) route 0.120ns (39.152%))
Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.036ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.901ns
- Source Clock Delay (SCD): -0.657ns
- Clock Pessimism Removal (CPR): -0.280ns
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.254ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
@@ -2906,14 +2952,14 @@ Slack (MET) : 0.208ns (arrival time - required time)
-2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
- SLICE_X160Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X160Y111 FDRE r initialize_audio/initA_reg[1]/C
------------------------------------------------------------------- -------------------
- SLICE_X160Y116 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/FSM_gray_state_reg[0]/Q
- net (fo=26, routed) 0.149 -0.367 initialize_audio/twi_controller/state[0]
- SLICE_X159Y116 LUT6 (Prop_lut6_I5_O) 0.045 -0.322 r initialize_audio/twi_controller/FSM_gray_state[1]_i_1/O
- net (fo=1, routed) 0.000 -0.322 initialize_audio/twi_controller/FSM_gray_state[1]_i_1_n_0
- SLICE_X159Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/D
+ SLICE_X160Y111 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initA_reg[1]/Q
+ net (fo=25, routed) 0.120 -0.393 initialize_audio/initA_reg_n_0_[1]
+ SLICE_X161Y111 LUT6 (Prop_lut6_I3_O) 0.045 -0.348 r initialize_audio/initWord[9]_i_1/O
+ net (fo=1, routed) 0.000 -0.348 initialize_audio/initWord[9]_i_1_n_0
+ SLICE_X161Y111 FDRE r initialize_audio/initWord_reg[9]/D
------------------------------------------------------------------- -------------------
(clock clk_out4_clk_wiz_0 rise edge)
@@ -2926,15 +2972,15 @@ Slack (MET) : 0.208ns (arrival time - required time)
-3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
- net (fo=120, routed) 0.913 -0.901 initialize_audio/twi_controller/clk_out4
- SLICE_X159Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
- clock pessimism 0.280 -0.621
- SLICE_X159Y116 FDRE (Hold_fdre_C_D) 0.091 -0.530 initialize_audio/twi_controller/FSM_gray_state_reg[1]
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X161Y111 FDRE r initialize_audio/initWord_reg[9]/C
+ clock pessimism 0.254 -0.641
+ SLICE_X161Y111 FDRE (Hold_fdre_C_D) 0.092 -0.549 initialize_audio/initWord_reg[9]
-------------------------------------------------------------------
- required time 0.530
- arrival time -0.322
+ required time 0.549
+ arrival time -0.348
-------------------------------------------------------------------
- slack 0.208
+ slack 0.201
@@ -2950,35 +2996,35 @@ Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT3 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y2 clk_1/inst/clkout4_buf/I
Min Period n/a MMCME2_ADV/CLKOUT3 n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y114 initialize_audio/data_i_reg[1]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y113 initialize_audio/data_i_reg[3]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y113 initialize_audio/data_i_reg[5]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y114 initialize_audio/data_i_reg[6]/C
-Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y114 initialize_audio/data_i_reg[7]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y113 initialize_audio/data_i_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X162Y111 initialize_audio/data_i_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y113 initialize_audio/data_i_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y110 initialize_audio/data_i_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y110 initialize_audio/data_i_reg[4]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y113 initialize_audio/data_i_reg[5]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X163Y112 initialize_audio/data_i_reg[6]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X163Y112 initialize_audio/data_i_reg[7]/C
Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 20.000 193.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
-Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y114 initialize_audio/data_i_reg[1]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y114 initialize_audio/data_i_reg[1]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y113 initialize_audio/data_i_reg[3]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y113 initialize_audio/data_i_reg[3]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
-High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
-High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
-High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y114 initialize_audio/data_i_reg[1]/C
-High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y114 initialize_audio/data_i_reg[1]/C
-High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
-High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
-High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y113 initialize_audio/data_i_reg[3]/C
-High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y113 initialize_audio/data_i_reg[3]/C
-High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
-High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X162Y111 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X162Y111 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y110 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y110 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y110 initialize_audio/data_i_reg[4]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y110 initialize_audio/data_i_reg[4]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X162Y111 initialize_audio/data_i_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X162Y111 initialize_audio/data_i_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y113 initialize_audio/data_i_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y110 initialize_audio/data_i_reg[3]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y110 initialize_audio/data_i_reg[3]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y110 initialize_audio/data_i_reg[4]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y110 initialize_audio/data_i_reg[4]/C
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx
index 935dc27c0c7ba9c8c13a33662681dae45e70661d..54319a89252c4ea28d96ad8e084071cd7013c943 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb
index 6bf38ddf52649c8defe8e82e86e9d9f890205207..43739e2018853a4c82894788856b620eff025206 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb and b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
index 8b1f475778bc503e67e90fd07b9d1b45c770222c..701c993bfe9c405d48b3dec542fc00743ee85e54 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:21:52 2025
+| Date : Mon May 12 16:28:15 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
| Design : audioProc
@@ -32,8 +32,8 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs | 531 | 0 | 800 | 133800 | 0.40 |
-| LUT as Logic | 531 | 0 | 800 | 133800 | 0.40 |
+| Slice LUTs | 525 | 0 | 800 | 133800 | 0.39 |
+| LUT as Logic | 525 | 0 | 800 | 133800 | 0.39 |
| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
| Slice Registers | 903 | 0 | 1600 | 267600 | 0.34 |
| Register as Flip Flop | 893 | 0 | 1600 | 267600 | 0.33 |
@@ -69,13 +69,13 @@ Table of Contents
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
-| Slice | 263 | 0 | 200 | 33450 | 0.79 |
-| SLICEL | 162 | 0 | | | |
-| SLICEM | 101 | 0 | | | |
-| LUT as Logic | 531 | 0 | 800 | 133800 | 0.40 |
+| Slice | 273 | 0 | 200 | 33450 | 0.82 |
+| SLICEL | 164 | 0 | | | |
+| SLICEM | 109 | 0 | | | |
+| LUT as Logic | 525 | 0 | 800 | 133800 | 0.39 |
| using O5 output only | 0 | | | | |
-| using O6 output only | 487 | | | | |
-| using O5 and O6 | 44 | | | | |
+| using O6 output only | 482 | | | | |
+| using O5 and O6 | 43 | | | | |
| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | | |
| using O5 output only | 0 | | | | |
@@ -86,11 +86,11 @@ Table of Contents
| using O6 output only | 0 | | | | |
| using O5 and O6 | 0 | | | | |
| Slice Registers | 903 | 0 | 1600 | 267600 | 0.34 |
-| Register driven from within the Slice | 330 | | | | |
-| Register driven from outside the Slice | 573 | | | | |
-| LUT in front of the register is unused | 493 | | | | |
-| LUT in front of the register is used | 80 | | | | |
-| Unique Control Sets | 32 | | 200 | 33450 | 0.10 |
+| Register driven from within the Slice | 326 | | | | |
+| Register driven from outside the Slice | 577 | | | | |
+| LUT in front of the register is unused | 502 | | | | |
+| LUT in front of the register is used | 75 | | | | |
+| Unique Control Sets | 30 | | 200 | 33450 | 0.09 |
+--------------------------------------------+------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -187,14 +187,14 @@ Table of Contents
| Ref Name | Used | Functional Category |
+------------+------+---------------------+
| FDCE | 632 | Flop & Latch |
-| LUT6 | 248 | LUT |
+| LUT6 | 245 | LUT |
| FDRE | 239 | Flop & Latch |
-| LUT2 | 119 | LUT |
-| LUT4 | 79 | LUT |
+| LUT2 | 115 | LUT |
+| LUT4 | 78 | LUT |
| MUXF7 | 64 | MuxFx |
-| LUT5 | 52 | LUT |
+| LUT5 | 55 | LUT |
| LUT1 | 41 | LUT |
-| LUT3 | 36 | LUT |
+| LUT3 | 34 | LUT |
| MUXF8 | 32 | MuxFx |
| FDSE | 20 | Flop & Latch |
| CARRY4 | 20 | CarryLogic |
diff --git a/proj/AudioProc.runs/impl_1/clockInfo.txt b/proj/AudioProc.runs/impl_1/clockInfo.txt
index 0823fcaa13ac44328bde4c5da85728186c07a6e5..97073ec58c701c2daeedbb2443888542b8f7da38 100644
--- a/proj/AudioProc.runs/impl_1/clockInfo.txt
+++ b/proj/AudioProc.runs/impl_1/clockInfo.txt
@@ -1,6 +1,6 @@
-------------------------------------
| Tool Version : Vivado v.2024.1
-| Date : Fri May 9 16:21:48 2025
+| Date : Mon May 12 16:28:13 2025
| Host : fl-tp-br-520
| Design : design_1
| Device : xc7a200t-sbg484-1--
diff --git a/proj/AudioProc.runs/impl_1/gen_run.xml b/proj/AudioProc.runs/impl_1/gen_run.xml
index fdc0d51e8df692090f8ec6c094e3deb73c09f781..fa3d1fa7e26fa655c5a3cbda2b3bbe1105044b84 100644
--- a/proj/AudioProc.runs/impl_1/gen_run.xml
+++ b/proj/AudioProc.runs/impl_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1746800342">
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747059929">
<File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
<File Type="POSTROUTE-PHYSOPT-RQS" Name="audioProc_postroute_physopted.rqs"/>
<File Type="ROUTE-RQS" Name="audioProc_routed.rqs"/>
@@ -38,52 +38,52 @@
<File Type="ROUTE-BUS-SKEW-RPX" Name="audioProc_bus_skew_routed.rpx"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="audioProc_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW" Name="audioProc_bus_skew_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="audioProc_clock_utilization_routed.rpt"/>
+ <File Type="ROUTE-SIMILARITY" Name="audioProc_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-TIMING-RPX" Name="audioProc_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-TIMING-PB" Name="audioProc_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="audioProc_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="audioProc_route_status.pb"/>
+ <File Type="ROUTE-STATUS" Name="audioProc_route_status.rpt"/>
+ <File Type="ROUTE-PWR-RPX" Name="audioProc_power_routed.rpx"/>
+ <File Type="ROUTE-PWR-SUM" Name="audioProc_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="audioProc_power_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="audioProc_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="audioProc_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="audioProc_drc_routed.pb"/>
+ <File Type="ROUTE-DRC" Name="audioProc_drc_routed.rpt"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="audioProc_routed_bb.dcp"/>
+ <File Type="ROUTE-DCP" Name="audioProc_routed.dcp"/>
+ <File Type="ROUTE-ERROR-DCP" Name="audioProc_routed_error.dcp"/>
+ <File Type="PHYSOPT-TIMING" Name="audioProc_timing_summary_physopted.rpt"/>
+ <File Type="PHYSOPT-DRC" Name="audioProc_drc_physopted.rpt"/>
+ <File Type="PHYSOPT-DCP" Name="audioProc_physopt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="audioProc_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="audioProc_postplace_pwropt.dcp"/>
+ <File Type="PLACE-RQA-PB" Name="audioProc_rqa_placed.pb"/>
+ <File Type="PLACE-TIMING" Name="audioProc_timing_summary_placed.rpt"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="audioProc_incremental_reuse_pre_placed.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="audioProc_incremental_reuse_placed.rpt"/>
+ <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="audioProc_utilization_placed.pb"/>
- <File Type="OPT-METHODOLOGY-DRC" Name="audioProc_methodology_drc_opted.rpt"/>
<File Type="PLACE-UTIL" Name="audioProc_utilization_placed.rpt"/>
<File Type="PLACE-CLK" Name="audioProc_clock_utilization_placed.rpt"/>
<File Type="PLACE-IO" Name="audioProc_io_placed.rpt"/>
- <File Type="PHYSOPT-TIMING" Name="audioProc_timing_summary_physopted.rpt"/>
- <File Type="PWROPT-DRC" Name="audioProc_drc_pwropted.rpt"/>
+ <File Type="PLACE-DCP" Name="audioProc_placed.dcp"/>
<File Type="PWROPT-TIMING" Name="audioProc_timing_summary_pwropted.rpt"/>
- <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
- <File Type="PLACE-TIMING" Name="audioProc_timing_summary_placed.rpt"/>
- <File Type="INIT-TIMING" Name="audioProc_timing_summary_init.rpt"/>
- <File Type="PA-TCL" Name="audioProc.tcl"/>
- <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
- <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
- <File Type="OPT-DCP" Name="audioProc_opt.dcp"/>
+ <File Type="PWROPT-DRC" Name="audioProc_drc_pwropted.rpt"/>
+ <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
<File Type="OPT-RQA-PB" Name="audioProc_rqa_opted.pb"/>
<File Type="OPT-HWDEF" Name="audioProc.hwdef"/>
- <File Type="POSTPLACE-PWROPT-TIMING" Name="audioProc_timing_summary_postplace_pwropted.rpt"/>
- <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="audioProc_methodology_drc_opted.rpt"/>
+ <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
+ <File Type="OPT-DCP" Name="audioProc_opt.dcp"/>
<File Type="OPT-TIMING" Name="audioProc_timing_summary_opted.rpt"/>
- <File Type="PLACE-SIMILARITY" Name="audioProc_incremental_reuse_placed.rpt"/>
- <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
- <File Type="PLACE-DCP" Name="audioProc_placed.dcp"/>
- <File Type="PLACE-RQA-PB" Name="audioProc_rqa_placed.pb"/>
- <File Type="PLACE-PRE-SIMILARITY" Name="audioProc_incremental_reuse_pre_placed.rpt"/>
- <File Type="ROUTE-DRC-RPX" Name="audioProc_drc_routed.rpx"/>
- <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
- <File Type="POSTPLACE-PWROPT-DCP" Name="audioProc_postplace_pwropt.dcp"/>
- <File Type="PHYSOPT-DCP" Name="audioProc_physopt.dcp"/>
- <File Type="PHYSOPT-DRC" Name="audioProc_drc_physopted.rpt"/>
- <File Type="ROUTE-ERROR-DCP" Name="audioProc_routed_error.dcp"/>
- <File Type="ROUTE-DCP" Name="audioProc_routed.dcp"/>
- <File Type="ROUTE-BLACKBOX-DCP" Name="audioProc_routed_bb.dcp"/>
- <File Type="ROUTE-DRC" Name="audioProc_drc_routed.rpt"/>
- <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="audioProc_methodology_drc_routed.rpx"/>
- <File Type="ROUTE-DRC-PB" Name="audioProc_drc_routed.pb"/>
- <File Type="ROUTE-PWR" Name="audioProc_power_routed.rpt"/>
- <File Type="ROUTE-PWR-SUM" Name="audioProc_power_summary_routed.pb"/>
- <File Type="ROUTE-PWR-RPX" Name="audioProc_power_routed.rpx"/>
- <File Type="ROUTE-STATUS" Name="audioProc_route_status.rpt"/>
- <File Type="ROUTE-STATUS-PB" Name="audioProc_route_status.pb"/>
- <File Type="ROUTE-TIMINGSUMMARY" Name="audioProc_timing_summary_routed.rpt"/>
- <File Type="ROUTE-TIMING-PB" Name="audioProc_timing_summary_routed.pb"/>
- <File Type="ROUTE-TIMING-RPX" Name="audioProc_timing_summary_routed.rpx"/>
- <File Type="ROUTE-SIMILARITY" Name="audioProc_incremental_reuse_routed.rpt"/>
- <File Type="ROUTE-CLK" Name="audioProc_clock_utilization_routed.rpt"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="INIT-TIMING" Name="audioProc_timing_summary_init.rpt"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
@@ -107,20 +107,19 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -151,16 +150,17 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
<FileInfo>
- <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -184,14 +184,20 @@
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/audioProc.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
- <Desc>Vivado Implementation Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
diff --git a/proj/AudioProc.runs/impl_1/init_design.pb b/proj/AudioProc.runs/impl_1/init_design.pb
index 264e35a6379440036b7b3e62920775012e25769c..0fa1e36309ef010fb8ec39483a9630c60f51ff51 100644
Binary files a/proj/AudioProc.runs/impl_1/init_design.pb and b/proj/AudioProc.runs/impl_1/init_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/opt_design.pb b/proj/AudioProc.runs/impl_1/opt_design.pb
index a6475a3baee9e3f578565f5068a3eea03414bff7..37d3ed28b28517c07e65b0aad2459fdf6c581ab0 100644
Binary files a/proj/AudioProc.runs/impl_1/opt_design.pb and b/proj/AudioProc.runs/impl_1/opt_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/place_design.pb b/proj/AudioProc.runs/impl_1/place_design.pb
index a124a9a2be242dd0e15a5568cefbaf77ede96dbb..41c1b1befed4b37b906fbe13242a273b98199d0c 100644
Binary files a/proj/AudioProc.runs/impl_1/place_design.pb and b/proj/AudioProc.runs/impl_1/place_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/project.wdf b/proj/AudioProc.runs/impl_1/project.wdf
index 33496474106a77f36c7c79b22fbd9a6abe51f2f3..79fa23bfe4f6b324385176b89986ecab677245ff 100644
--- a/proj/AudioProc.runs/impl_1/project.wdf
+++ b/proj/AudioProc.runs/impl_1/project.wdf
@@ -14,7 +14,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c3c6970636f72656e616d653e5c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:36:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
@@ -29,4 +29,4 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6132646133366432613739383432626439363437623931393963636264373035:506172656e742050412070726f6a656374204944:00
-eof:765887299
+eof:1050317336
diff --git a/proj/AudioProc.runs/impl_1/route_design.pb b/proj/AudioProc.runs/impl_1/route_design.pb
index 66ab44fdc4cb969b12b96975295545e796e49b15..6776bdbad430c9a4c58eaa7e2484ae23526a17d4 100644
Binary files a/proj/AudioProc.runs/impl_1/route_design.pb and b/proj/AudioProc.runs/impl_1/route_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/runme.log b/proj/AudioProc.runs/impl_1/runme.log
index 18a39ab28c9dfa03b65674c5fd9f4d83e917988b..8be275c9946a8dd22f6f51ea314c682a8951afb7 100644
--- a/proj/AudioProc.runs/impl_1/runme.log
+++ b/proj/AudioProc.runs/impl_1/runme.log
@@ -7,12 +7,12 @@
**** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
**** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
**** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
- **** Start of session at: Fri May 9 16:20:38 2025
+ **** Start of session at: Mon May 12 16:27:04 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1680.582 ; gain = 326.840 ; free physical = 6369 ; free virtual = 15615
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.582 ; gain = 326.840 ; free physical = 3938 ; free virtual = 13924
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -23,7 +23,7 @@ Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a200tsbg484-1
INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
INFO: [Project 1-454] Reading design checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2098.465 ; gain = 0.000 ; free physical = 5935 ; free virtual = 15181
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2097.465 ; gain = 0.000 ; free physical = 3534 ; free virtual = 13487
INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.3
@@ -33,20 +33,20 @@ Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etu
Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
INFO: [Timing 38-2] Deriving generated clocks [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
-get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2743.926 ; gain = 548.961 ; free physical = 5350 ; free virtual = 14616
+get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2743.957 ; gain = 551.961 ; free physical = 2976 ; free virtual = 12929
Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/constraints/NexysVideo_Master.xdc]
Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/constraints/NexysVideo_Master.xdc]
INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.dcp'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.926 ; gain = 0.000 ; free physical = 5349 ; free virtual = 14615
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.957 ; gain = 0.000 ; free physical = 2976 ; free virtual = 12929
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 2743.926 ; gain = 1048.500 ; free physical = 5349 ; free virtual = 14615
+link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2743.957 ; gain = 1048.531 ; free physical = 2976 ; free virtual = 12929
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
@@ -57,113 +57,112 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:01 . Memory (MB): peak = 2819.832 ; gain = 75.906 ; free physical = 5327 ; free virtual = 14593
+Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2817.895 ; gain = 73.938 ; free physical = 2949 ; free virtual = 12902
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 3002b507b
+Ending Cache Timing Information Task | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2819.832 ; gain = 0.000 ; free physical = 5327 ; free virtual = 14593
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2817.895 ; gain = 0.000 ; free physical = 2949 ; free virtual = 12902
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 3002b507b
+Phase 1.1 Core Generation And Design Setup | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 3002b507b
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Phase 1 Initialization | Checksum: 3002b507b
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 1 Initialization | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
-Phase 2.1 Timer Update | Checksum: 3002b507b
+Phase 2.1 Timer Update | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 2.2 Timing Data Collection
-Phase 2.2 Timing Data Collection | Checksum: 3002b507b
+Phase 2.2 Timing Data Collection | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Phase 2 Timer Update And Timing Data Collection | Checksum: 3002b507b
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 3 Retarget
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 3002b507b
+Phase 3 Retarget | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Retarget | Checksum: 3002b507b
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Retarget | Checksum: 2e2fef6cb
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 3002b507b
+Phase 4 Constant propagation | Checksum: 2e2fef6cb
-Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Constant propagation | Checksum: 3002b507b
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Constant propagation | Checksum: 2e2fef6cb
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
-Phase 5 Sweep | Checksum: 26ac40cc4
+Phase 5 Sweep | Checksum: 278026854
-Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14286
-Sweep | Checksum: 26ac40cc4
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Sweep | Checksum: 278026854
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 6 BUFG optimization
-INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells
-Phase 6 BUFG optimization | Checksum: 2ceae85f4
+Phase 6 BUFG optimization | Checksum: 278026854
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-BUFG optimization | Checksum: 2ceae85f4
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells.
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+BUFG optimization | Checksum: 278026854
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 2ceae85f4
+Phase 7 Shift Register Optimization | Checksum: 278026854
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Shift Register Optimization | Checksum: 2ceae85f4
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Shift Register Optimization | Checksum: 278026854
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 300494802
+Phase 8 Post Processing Netlist | Checksum: 278026854
-Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Post Processing Netlist | Checksum: 300494802
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Post Processing Netlist | Checksum: 278026854
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 28a25b064
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 28a25b064
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Phase 9 Finalization | Checksum: 28a25b064
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Phase 9 Finalization | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Opt_design Change Summary
=========================
@@ -174,34 +173,34 @@ Opt_design Change Summary
| Retarget | 0 | 0 | 1 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 1 | 0 |
-| BUFG optimization | 0 | 2 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
-Ending Logic Optimization Task | Checksum: 28a25b064
+Ending Logic Optimization Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 28a25b064
+Ending Power Optimization Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 28a25b064
+Ending Final Cleanup Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
-Ending Netlist Obfuscation Task | Checksum: 28a25b064
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
+Ending Netlist Obfuscation Task | Checksum: 352c04e82
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.621 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14287
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3100.684 ; gain = 0.000 ; free physical = 2642 ; free virtual = 12595
INFO: [Common 17-83] Releasing license: Implementation
-34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
@@ -210,16 +209,16 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5011 ; free virtual = 14280
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5011 ; free virtual = 14280
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5011 ; free virtual = 14280
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5010 ; free virtual = 14279
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5007 ; free virtual = 14276
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5007 ; free virtual = 14276
-Write Physdb Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3180.660 ; gain = 0.000 ; free physical = 5007 ; free virtual = 14276
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2633 ; free virtual = 12586
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2632 ; free virtual = 12585
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2632 ; free virtual = 12585
+Write Physdb Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3180.723 ; gain = 0.000 ; free physical = 2632 ; free virtual = 12585
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -239,59 +238,59 @@ Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4971 ; free virtual = 14250
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1971e65b5
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2505 ; free virtual = 12458
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 27ecc6cee
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4971 ; free virtual = 14250
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4971 ; free virtual = 14250
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2505 ; free virtual = 12458
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2505 ; free virtual = 12458
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d834e537
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 167eef5db
-Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.49 . Memory (MB): peak = 3214.445 ; gain = 0.000 ; free physical = 4964 ; free virtual = 14246
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3212.508 ; gain = 0.000 ; free physical = 2497 ; free virtual = 12450
Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 24479b66e
+Phase 1.3 Build Placer Netlist Model | Checksum: 22978800d
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4962 ; free virtual = 14245
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2487 ; free virtual = 12440
Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 24479b66e
+Phase 1.4 Constrain Clocks/Macros | Checksum: 22978800d
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4962 ; free virtual = 14245
-Phase 1 Placer Initialization | Checksum: 24479b66e
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2487 ; free virtual = 12440
+Phase 1 Placer Initialization | Checksum: 22978800d
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.84 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4961 ; free virtual = 14245
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2487 ; free virtual = 12440
Phase 2 Global Placement
Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1f0769a16
+Phase 2.1 Floorplanning | Checksum: 224a3efaa
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.95 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 4988 ; free virtual = 14272
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2486 ; free virtual = 12439
Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2d5cde647
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 16f59aef9
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 5009 ; free virtual = 14292
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2538 ; free virtual = 12491
Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2d5cde647
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 16f59aef9
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3221.473 ; gain = 7.027 ; free physical = 5009 ; free virtual = 14292
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3219.535 ; gain = 7.027 ; free physical = 2538 ; free virtual = 12491
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
-Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 24e71af8c
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e559c04f
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3234.477 ; gain = 20.031 ; free physical = 5007 ; free virtual = 14283
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3233.539 ; gain = 21.031 ; free physical = 2522 ; free virtual = 12475
Phase 2.4.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 96 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 90 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 44 nets or LUTs. Breaked 0 LUT, combined 44 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 43 nets or LUTs. Breaked 0 LUT, combined 43 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
@@ -302,7 +301,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3234.477 ; gain = 0.000 ; free physical = 4980 ; free virtual = 14279
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3233.539 ; gain = 0.000 ; free physical = 2535 ; free virtual = 12488
Summary of Physical Synthesis Optimizations
============================================
@@ -311,7 +310,7 @@ Summary of Physical Synthesis Optimizations
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 44 | 44 | 0 | 1 | 00:00:00 |
+| LUT Combining | 0 | 43 | 43 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
@@ -320,59 +319,59 @@ Summary of Physical Synthesis Optimizations
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 44 | 44 | 0 | 4 | 00:00:00 |
+| Total | 0 | 43 | 43 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2d955f418
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 26385cb9f
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4980 ; free virtual = 14279
-Phase 2.4 Global Placement Core | Checksum: 24d73e065
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
+Phase 2.4 Global Placement Core | Checksum: 264b89dc8
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4971 ; free virtual = 14265
-Phase 2 Global Placement | Checksum: 24d73e065
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
+Phase 2 Global Placement | Checksum: 264b89dc8
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4971 ; free virtual = 14265
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 23d657603
+Phase 3.1 Commit Multi Column Macros | Checksum: 23022f2f1
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4963 ; free virtual = 14264
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2535 ; free virtual = 12488
Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22513e1c8
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c797472b
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4962 ; free virtual = 14264
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2534 ; free virtual = 12487
Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 1ea1af04a
+Phase 3.3 Area Swap Optimization | Checksum: 26d02ebbb
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4962 ; free virtual = 14264
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2534 ; free virtual = 12487
Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 178715a17
+Phase 3.4 Pipeline Register Optimization | Checksum: 1f51d677c
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4962 ; free virtual = 14264
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:02 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2534 ; free virtual = 12487
Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 2d4f2065c
+Phase 3.5 Small Shape Detail Placement | Checksum: 2a343d387
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4913 ; free virtual = 14235
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2490 ; free virtual = 12443
Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1f22d608d
+Phase 3.6 Re-assign LUT pins | Checksum: 26349eaea
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4905 ; free virtual = 14228
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2490 ; free virtual = 12443
Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 146f8e4d1
+Phase 3.7 Pipeline Register Optimization | Checksum: 214e05132
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4905 ; free virtual = 14228
-Phase 3 Detail Placement | Checksum: 146f8e4d1
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2490 ; free virtual = 12443
+Phase 3 Detail Placement | Checksum: 214e05132
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4905 ; free virtual = 14228
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2482 ; free virtual = 12435
Phase 4 Post Placement Optimization and Clean-Up
@@ -380,7 +379,7 @@ Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 236af2095
+Post Placement Optimization Initialization | Checksum: 1f3d6a612
Phase 4.1.1.1 BUFG Insertion
@@ -388,33 +387,33 @@ Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.794 | TNS=0.000 |
-Phase 1 Physical Synthesis Initialization | Checksum: 27a123550
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.890 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 200ae2f51
-Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4897 ; free virtual = 14215
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2474 ; free virtual = 12427
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 239910472
+Ending Physical Synthesis Task | Checksum: 2858bbf4e
-Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4897 ; free virtual = 14215
-Phase 4.1.1.1 BUFG Insertion | Checksum: 236af2095
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2474 ; free virtual = 12427
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1f3d6a612
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4896 ; free virtual = 14214
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2474 ; free virtual = 12427
Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.794. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 242e1e100
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.890. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2728a29e4
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2474 ; free virtual = 12427
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Phase 4.1 Post Commit Optimization | Checksum: 242e1e100
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2474 ; free virtual = 12427
+Phase 4.1 Post Commit Optimization | Checksum: 2728a29e4
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 242e1e100
+Phase 4.2 Post Placement Cleanup | Checksum: 2728a29e4
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
Phase 4.3 Placer Reporting
@@ -433,44 +432,43 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
| West| 1x1| 1x1|
|___________|___________________|___________________|
-Phase 4.3.1 Print Estimated Congestion | Checksum: 242e1e100
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2728a29e4
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Phase 4.3 Placer Reporting | Checksum: 242e1e100
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+Phase 4.3 Placer Reporting | Checksum: 2728a29e4
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4891 ; free virtual = 14209
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2466 ; free virtual = 12419
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c155315a
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 285157fe1
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-Ending Placer Task | Checksum: c4fd0a1d
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+Ending Placer Task | Checksum: 1c42333b7
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3244.285 ; gain = 29.840 ; free physical = 4891 ; free virtual = 14209
-69 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3245.348 ; gain = 32.840 ; free physical = 2466 ; free virtual = 12419
+68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
-place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3244.285 ; gain = 63.625 ; free physical = 4891 ; free virtual = 14209
INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
Running report generation with 3 threads.
INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4872 ; free virtual = 14193
+report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2452 ; free virtual = 12405
INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4848 ; free virtual = 14173
+report_io: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2443 ; free virtual = 12396
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4840 ; free virtual = 14169
-Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4834 ; free virtual = 14164
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14165
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2434 ; free virtual = 12387
+Wrote PlaceDB: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2434 ; free virtual = 12388
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12388
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
-Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3244.285 ; gain = 0.000 ; free physical = 4859 ; free virtual = 14166
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12388
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12388
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12389
+Write Physdb Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3245.348 ; gain = 0.000 ; free physical = 2433 ; free virtual = 12389
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -485,122 +483,116 @@ Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
-Checksum: PlaceDB: 17894a90 ConstDB: 0 ShapeSum: 1558d429 RouteDB: 981aeb64
-Post Restoration Checksum: NetGraph: a8773583 | NumContArr: fe331ce0 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 32bfc479d
+Checksum: PlaceDB: 2f016cf1 ConstDB: 0 ShapeSum: fd06db62 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 6f0615b9 | NumContArr: 99ab826b | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 28e038d5e
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 3434.043 ; gain = 168.945 ; free physical = 4726 ; free virtual = 14008
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 3432.137 ; gain = 166.945 ; free physical = 2328 ; free virtual = 12283
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 32bfc479d
+Phase 2.1 Fix Topology Constraints | Checksum: 28e038d5e
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 3434.043 ; gain = 168.945 ; free physical = 4718 ; free virtual = 14002
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 3432.137 ; gain = 166.945 ; free physical = 2328 ; free virtual = 12283
Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 32bfc479d
+Phase 2.2 Pre Route Cleanup | Checksum: 28e038d5e
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 3434.043 ; gain = 168.945 ; free physical = 4718 ; free virtual = 14002
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 3432.137 ; gain = 166.945 ; free physical = 2328 ; free virtual = 12283
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 2d1d4910a
+Phase 2.3 Update Timing | Checksum: 19e4dbff3
-Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 3501.801 ; gain = 236.703 ; free physical = 4649 ; free virtual = 13934
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.803 | TNS=0.000 | WHS=-0.144 | THS=-22.944|
+Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 3499.895 ; gain = 234.703 ; free physical = 2259 ; free virtual = 12213
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.910 | TNS=0.000 | WHS=-0.148 | THS=-25.785|
Router Utilization Summary
- Global Vertical Routing Utilization = 0.000182205 %
+ Global Vertical Routing Utilization = 0.00020245 %
Global Horizontal Routing Utilization = 0.000165235 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
- Number of Failed Nets = 1211
+ Number of Failed Nets = 1206
(Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 1201
+ Number of Unrouted Nets = 1196
Number of Partially Routed Nets = 10
Number of Node Overlaps = 11
-Phase 2 Router Initialization | Checksum: 269f51fe2
+Phase 2 Router Initialization | Checksum: 22e8cf3f2
-Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 269f51fe2
+Phase 3 Global Routing | Checksum: 22e8cf3f2
-Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
Phase 4 Initial Routing
Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 2c245566f
+Phase 4.1 Initial Net Routing Pass | Checksum: 2b7538a3c
-Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
-Phase 4 Initial Routing | Checksum: 2c245566f
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
+Phase 4 Initial Routing | Checksum: 2b7538a3c
-Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4645 ; free virtual = 13930
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2255 ; free virtual = 12209
Phase 5 Rip-up And Reroute
Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 238
- Number of Nodes with overlaps = 126
- Number of Nodes with overlaps = 68
+ Number of Nodes with overlaps = 217
+ Number of Nodes with overlaps = 106
+ Number of Nodes with overlaps = 62
Number of Nodes with overlaps = 32
- Number of Nodes with overlaps = 10
- Number of Nodes with overlaps = 6
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 19
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.534 | TNS=0.000 | WHS=N/A | THS=N/A |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.650 | TNS=0.000 | WHS=N/A | THS=N/A |
-Phase 5.1 Global Iteration 0 | Checksum: 2abe36016
+Phase 5.1 Global Iteration 0 | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-Phase 5 Rip-up And Reroute | Checksum: 2abe36016
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Phase 5 Rip-up And Reroute | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 6 Delay and Skew Optimization
Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 35ff68537
-Phase 6.1.1 Update Timing
-Phase 6.1.1 Update Timing | Checksum: 2efa28e2c
-
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613 | TNS=0.000 | WHS=N/A | THS=N/A |
-
-Phase 6.1 Delay CleanUp | Checksum: 2efa28e2c
-
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 2efa28e2c
+Phase 6.2 Clock Skew Optimization | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-Phase 6 Delay and Skew Optimization | Checksum: 2efa28e2c
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Phase 6 Delay and Skew Optimization | Checksum: 35ff68537
-Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 7 Post Hold Fix
Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613 | TNS=0.000 | WHS=0.107 | THS=0.000 |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.729 | TNS=0.000 | WHS=0.049 | THS=0.000 |
-Phase 7.1 Hold Fix Iter | Checksum: 2486ccefa
+Phase 7.1 Hold Fix Iter | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
-Phase 7 Post Hold Fix | Checksum: 2486ccefa
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Phase 7 Post Hold Fix | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 8 Route finalize
Router Utilization Summary
- Global Vertical Routing Utilization = 0.0942403 %
- Global Horizontal Routing Utilization = 0.118209 %
+ Global Vertical Routing Utilization = 0.0982691 %
+ Global Horizontal Routing Utilization = 0.114871 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -610,50 +602,50 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
-Phase 8 Route finalize | Checksum: 2486ccefa
+Phase 8 Route finalize | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4647 ; free virtual = 13930
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 9 Verifying routed nets
Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2486ccefa
+Phase 9 Verifying routed nets | Checksum: 361534e8f
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 16786fc76
+Phase 10 Depositing Routes | Checksum: 3780a9066
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 16786fc76
+Phase 11 Post Process Routing | Checksum: 3780a9066
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.613 | TNS=0.000 | WHS=0.107 | THS=0.000 |
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.729 | TNS=0.000 | WHS=0.049 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 16786fc76
+Phase 12 Post Router Timing | Checksum: 3780a9066
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
-Total Elapsed time in route_design: 35.78 secs
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
+Total Elapsed time in route_design: 33.94 secs
Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: d2e3295b
+Phase 13 Post-Route Event Processing | Checksum: 23c536cd6
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: d2e3295b
+Ending Routing Task | Checksum: 23c536cd6
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:36 . Memory (MB): peak = 3509.191 ; gain = 244.094 ; free physical = 4646 ; free virtual = 13929
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 3507.285 ; gain = 242.094 ; free physical = 2257 ; free virtual = 12212
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
-88 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+86 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:37 . Memory (MB): peak = 3509.191 ; gain = 252.098 ; free physical = 4646 ; free virtual = 13929
+route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 3507.285 ; gain = 250.098 ; free physical = 2257 ; free virtual = 12212
INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -683,22 +675,22 @@ Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summa
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
-108 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+106 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
WARNING: [Device 21-2174] Failed to initialize Virtual grid.
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4604 ; free virtual = 13917
-Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4603 ; free virtual = 13917
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12211
+Wrote PlaceDB: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12212
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12212
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4601 ; free virtual = 13920
-Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3597.234 ; gain = 0.000 ; free physical = 4600 ; free virtual = 13919
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12212
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12213
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12213
+Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.3 . Memory (MB): peak = 3595.328 ; gain = 0.000 ; free physical = 2255 ; free virtual = 12213
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
Command: write_bitstream -force audioProc.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -725,8 +717,8 @@ WARNING: [DRC DPOP-1] PREG Output pipelining: DSP leftFir/firUnit_1/operativeUni
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult output rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP leftFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
-WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
@@ -740,7 +732,7 @@ Writing bitstream ./audioProc.bit...
Writing bitstream ./audioProc.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
-119 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
+117 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3851.027 ; gain = 253.793 ; free physical = 4280 ; free virtual = 13588
-INFO: [Common 17-206] Exiting Vivado at Fri May 9 16:22:48 2025...
+write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3851.090 ; gain = 255.762 ; free physical = 1873 ; free virtual = 11848
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:29:09 2025...
diff --git a/proj/AudioProc.runs/impl_1/vivado.jou b/proj/AudioProc.runs/impl_1/vivado.jou
index 9388f1fc14cffa1bf2da1cd1275eeb9465371d2f..83f2238354aef19b37ca6a06ff85d5772c087f8b 100644
--- a/proj/AudioProc.runs/impl_1/vivado.jou
+++ b/proj/AudioProc.runs/impl_1/vivado.jou
@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May 9 16:20:38 2025
-# Process ID: 115256
+# Start of session at: Mon May 12 16:27:04 2025
+# Process ID: 128779
# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1
# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -13,12 +13,12 @@
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4199.706 MHz
+# CPU Frequency :4267.765 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
-# Available Virtual :16974 MB
+# Available Virtual :15208 MB
#-----------------------------------------------------------
source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado.pb b/proj/AudioProc.runs/impl_1/vivado.pb
index 48476abdf3bca2c8ad5052ba3767a981bc205687..b48f4a5703c0d97a6fee0cfde96adb4f04ddada3 100644
Binary files a/proj/AudioProc.runs/impl_1/vivado.pb and b/proj/AudioProc.runs/impl_1/vivado.pb differ
diff --git a/proj/AudioProc.runs/impl_1/vivado_125789.backup.jou b/proj/AudioProc.runs/impl_1/vivado_125789.backup.jou
new file mode 100644
index 0000000000000000000000000000000000000000..fea0cc70f096c1bb5b49b1880ff57d6563766f72
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado_125789.backup.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 16:10:27 2025
+# Process ID: 125789
+# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-520
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4368.551 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :15367 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado_95553.backup.jou b/proj/AudioProc.runs/impl_1/vivado_95553.backup.jou
new file mode 100644
index 0000000000000000000000000000000000000000..6783d1afc11dd25140dce15b3436493de370e5ee
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado_95553.backup.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 16:07:38 2025
+# Process ID: 95553
+# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-520
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4197.958 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :16521 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/write_bitstream.pb b/proj/AudioProc.runs/impl_1/write_bitstream.pb
index 47e5f36f192af5163eab3c17104d8578bc6ae249..85f9f12e22c4fa35a4571c10253a85e120e4c03c 100644
Binary files a/proj/AudioProc.runs/impl_1/write_bitstream.pb and b/proj/AudioProc.runs/impl_1/write_bitstream.pb differ
diff --git a/proj/AudioProc.runs/synth_1/.nfs000000000260d77500000134 b/proj/AudioProc.runs/synth_1/.nfs000000000260d77500000134
new file mode 100644
index 0000000000000000000000000000000000000000..c7d261ce7b1a026f250a96c905dbb8052c7139d6
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/.nfs000000000260d77500000134 differ
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
index 76f032ac4c29db4634573d51a9b3059edca4c77f..a8f98d3f742909cb333ec1c15c86943325c52184 100644
--- a/proj/AudioProc.runs/synth_1/.vivado.begin.rst
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="114649" HostCore="12" HostMemory="16146428">
+ <Process Command="vivado" Owner="m24wang" Host="fl-tp-br-520" Pid="128302" HostCore="12" HostMemory="16146432">
</Process>
</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/audioProc.dcp b/proj/AudioProc.runs/synth_1/audioProc.dcp
index 7e51b9b16abe024c728e00f704a4d60c1aec19de..68e51412cc08c54faab44bc272c2407a75936fa1 100644
Binary files a/proj/AudioProc.runs/synth_1/audioProc.dcp and b/proj/AudioProc.runs/synth_1/audioProc.dcp differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc.tcl b/proj/AudioProc.runs/synth_1/audioProc.tcl
index be11c7a1666e346e5e992e1507799fa3e840abdd..699d1405daadc413a03fbfd722c4b2a7b502d4c3 100644
--- a/proj/AudioProc.runs/synth_1/audioProc.tcl
+++ b/proj/AudioProc.runs/synth_1/audioProc.tcl
@@ -56,6 +56,7 @@ if {$::dispatch::connected} {
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param chipscope.maxJobs 3
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a200tsbg484-1
@@ -76,12 +77,12 @@ OPTRACE "Adding files" START { }
read_verilog -library xil_defaultlib {
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audio_init.v
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/debounce.v
- /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v
}
read_vhdl -library xil_defaultlib {
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/TWICtl.vhd
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/fir.vhd
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/i2s_ctl.vhd
@@ -106,6 +107,8 @@ set_property used_in_implementation false [get_files /homes/m24wang/Bureau/tp-vh
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
diff --git a/proj/AudioProc.runs/synth_1/audioProc.vds b/proj/AudioProc.runs/synth_1/audioProc.vds
index 0837b63ddf27e2d0352167eb8d42cd2090b486b7..55b8d6b24542c394462775e82eb78f5ba49e89e6 100644
--- a/proj/AudioProc.runs/synth_1/audioProc.vds
+++ b/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May 9 16:19:05 2025
-# Process ID: 114720
+# Start of session at: Mon May 12 16:25:33 2025
+# Process ID: 128373
# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1
# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -13,20 +13,23 @@
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4288.160 MHz
+# CPU Frequency :4357.542 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
-# Available Virtual :16979 MB
+# Available Virtual :15128 MB
#-----------------------------------------------------------
source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 6410 ; free virtual = 15595
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.551 ; gain = 325.840 ; free physical = 3993 ; free virtual = 13934
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: read_checkpoint -auto_incremental -incremental /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
Starting synth_design
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
@@ -41,14 +44,16 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Device 21-403] Loading part xc7a200tsbg484-1
INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 114883
+INFO: [Synth 8-7075] Helper process launched with PID 128517
---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2503.699 ; gain = 422.496 ; free physical = 5196 ; free virtual = 14422
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2501.820 ; gain = 420.559 ; free physical = 2869 ; free virtual = 12812
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:13]
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/.Xil/Vivado-114720-fl-tp-br-520/realtime/clk_wiz_0_stub.vhdl:18]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/.Xil/Vivado-128373-fl-tp-br-520/realtime/clk_wiz_0_stub.vhdl:18]
WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:87]
WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:87]
INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audio_init.v:24]
@@ -75,124 +80,8 @@ INFO: [Synth 8-6054] Found Dynamic range expression with variable size [/homes/m
INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd:42]
INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd:45]
-INFO: [Synth 8-6157] synthesizing module 'operativeUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:17]
-INFO: [Synth 8-6157] synthesizing module 'GND' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6155] done synthesizing module 'GND' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6157] synthesizing module 'OBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6157] synthesizing module 'LUT3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
- Parameter INIT bound to: 8'b10000000
-INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'DSP48E1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
- Parameter ACASCREG bound to: 0 - type: integer
- Parameter ADREG bound to: 1 - type: integer
- Parameter ALUMODEREG bound to: 0 - type: integer
- Parameter AREG bound to: 0 - type: integer
- Parameter AUTORESET_PATDET bound to: NO_RESET - type: string
- Parameter A_INPUT bound to: DIRECT - type: string
- Parameter BCASCREG bound to: 0 - type: integer
- Parameter BREG bound to: 0 - type: integer
- Parameter B_INPUT bound to: DIRECT - type: string
- Parameter CARRYINREG bound to: 0 - type: integer
- Parameter CARRYINSELREG bound to: 0 - type: integer
- Parameter CREG bound to: 0 - type: integer
- Parameter DREG bound to: 1 - type: integer
- Parameter INMODEREG bound to: 0 - type: integer
- Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111
- Parameter MREG bound to: 0 - type: integer
- Parameter OPMODEREG bound to: 0 - type: integer
- Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000
- Parameter PREG bound to: 0 - type: integer
- Parameter SEL_MASK bound to: MASK - type: string
- Parameter SEL_PATTERN bound to: PATTERN - type: string
- Parameter USE_DPORT bound to: FALSE - type: string
- Parameter USE_MULT bound to: MULTIPLY - type: string
- Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string
- Parameter USE_SIMD bound to: ONE48 - type: string
-INFO: [Synth 8-6155] done synthesizing module 'DSP48E1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
-WARNING: [Synth 8-689] width (36) of port connection 'P' does not match port width (48) of module 'DSP48E1' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:422]
-WARNING: [Synth 8-7071] port 'ACOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'BCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYCASCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'MULTSIGNOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'OVERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNBDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'UNDERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7023] instance 'SC_addResult' of module 'DSP48E1' has 49 connections declared, but only 39 given [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-INFO: [Synth 8-6157] synthesizing module 'LUT2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b0110
-INFO: [Synth 8-6155] done synthesizing module 'LUT2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1011111111111101
-INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
- Parameter INIT bound to: 64'b1010111110100000110011111100111110101111101000001100000011000000
-INFO: [Synth 8-6155] done synthesizing module 'LUT6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0101100000011010
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1111011001101111
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0001111001111000
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1110100110010111
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0110000110000110
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
- Parameter INIT bound to: 8'b01000010
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1010001001000101
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1111000110001111
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1101010110101011
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'FDCE' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
- Parameter INIT bound to: 1'b0
-INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
-INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:1478]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b0001
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
- Parameter INIT bound to: 8'b00000110
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0000000001101010
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b1110
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
- Parameter INIT bound to: 32'b00000000000000000110101010101010
-INFO: [Synth 8-6155] done synthesizing module 'LUT5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b0010
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'VCC' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'VCC' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'operativeUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:17]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/fir.vhd:28]
WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:199]
@@ -241,20 +130,18 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2589.668 ; gain = 508.465 ; free physical = 5105 ; free virtual = 14324
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2585.789 ; gain = 504.527 ; free physical = 2762 ; free virtual = 12703
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2607.480 ; gain = 526.277 ; free physical = 5105 ; free virtual = 14324
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2603.602 ; gain = 522.340 ; free physical = 2758 ; free virtual = 12700
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2607.480 ; gain = 526.277 ; free physical = 5105 ; free virtual = 14324
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2603.602 ; gain = 522.340 ; free physical = 2758 ; free virtual = 12700
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2613.418 ; gain = 0.000 ; free physical = 5097 ; free virtual = 14316
-INFO: [Netlist 29-17] Analyzing 106 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2603.602 ; gain = 0.000 ; free physical = 2758 ; free virtual = 12700
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -269,20 +156,22 @@ Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24
Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2680.418 ; gain = 0.000 ; free physical = 5090 ; free virtual = 14324
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2751.352 ; gain = 0.000 ; free physical = 2742 ; free virtual = 12683
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2680.418 ; gain = 0.000 ; free physical = 5090 ; free virtual = 14324
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2751.352 ; gain = 0.000 ; free physical = 2741 ; free virtual = 12683
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2680.418 ; gain = 599.215 ; free physical = 4992 ; free virtual = 14238
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2751.352 ; gain = 670.090 ; free physical = 2737 ; free virtual = 12682
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a200tsbg484-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 4992 ; free virtual = 14238
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2737 ; free virtual = 12682
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
@@ -290,7 +179,7 @@ Start Applying 'set_property' XDC Constraints
Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5000 ; free virtual = 14246
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2737 ; free virtual = 12682
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
INFO: [Synth 8-802] inferred FSM for state register 'SR_currentState_reg' in module 'controlUnit'
@@ -320,7 +209,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding
INFO: [Synth 8-3354] encoded FSM with state register 'SR_currentState_reg' using encoding 'one-hot' in module 'controlUnit'
WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_nextState_reg' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd:64]
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5025 ; free virtual = 14259
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2732 ; free virtual = 12676
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -330,39 +219,44 @@ Detailed RTL Component Info :
2 Input 32 Bit Adders := 3
2 Input 31 Bit Adders := 1
2 Input 24 Bit Adders := 2
+ 2 Input 16 Bit Adders := 2
2 Input 13 Bit Adders := 5
2 Input 7 Bit Adders := 3
2 Input 5 Bit Adders := 2
- 2 Input 4 Bit Adders := 1
+ 2 Input 4 Bit Adders := 3
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
+ 36 Bit Registers := 2
33 Bit Registers := 1
32 Bit Registers := 3
31 Bit Registers := 1
24 Bit Registers := 2
+ 16 Bit Registers := 34
13 Bit Registers := 5
8 Bit Registers := 3
7 Bit Registers := 3
5 Bit Registers := 4
- 4 Bit Registers := 2
+ 4 Bit Registers := 4
3 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 18
+---Muxes :
+ 2 Input 36 Bit Muxes := 2
2 Input 32 Bit Muxes := 3
2 Input 24 Bit Muxes := 2
2 Input 16 Bit Muxes := 6
+ 16 Input 12 Bit Muxes := 2
2 Input 8 Bit Muxes := 2
2 Input 5 Bit Muxes := 9
8 Input 5 Bit Muxes := 1
5 Input 5 Bit Muxes := 2
9 Input 4 Bit Muxes := 1
21 Input 4 Bit Muxes := 1
- 2 Input 4 Bit Muxes := 7
+ 2 Input 4 Bit Muxes := 9
5 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 39
+ 2 Input 1 Bit Muxes := 43
4 Input 1 Bit Muxes := 21
3 Input 1 Bit Muxes := 5
9 Input 1 Bit Muxes := 1
@@ -386,6 +280,12 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
@@ -408,25 +308,43 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 4975 ; free virtual = 14230
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2699 ; free virtual = 12649
+---------------------------------------------------------------------------------
+ Sort Area is firUnit_1/operativeUnit_1/SC_addResult_0 : 0 0 : 1641 1641 : Used 1 time 0
+ Sort Area is firUnit_1/operativeUnit_1/SC_addResult_2 : 0 0 : 1641 1641 : Used 1 time 0
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B | 16 | 13 | 36 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
+|operativeUnit | C+A*B | 16 | 13 | 36 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5085 ; free virtual = 14344
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2709 ; free virtual = 12656
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5087 ; free virtual = 14346
+Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2693 ; free virtual = 12645
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5088 ; free virtual = 14347
+Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2686 ; free virtual = 12635
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -446,49 +364,49 @@ Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|operativeUnit_3 | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
-|operativeUnit | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
+|operativeUnit | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
@@ -503,217 +421,52 @@ Report Cell Usage:
| |Cell |Count |
+------+--------+------+
|1 |clk_wiz | 1|
-|2 |BUFG | 2|
-|3 |CARRY4 | 20|
-|4 |DSP48E1 | 2|
-|5 |LUT1 | 41|
-|6 |LUT2 | 119|
-|7 |LUT3 | 36|
-|8 |LUT4 | 79|
-|9 |LUT5 | 52|
-|10 |LUT6 | 248|
-|11 |MUXF7 | 64|
-|12 |MUXF8 | 32|
-|13 |FDCE | 632|
-|14 |FDPE | 2|
-|15 |FDRE | 239|
-|16 |FDSE | 20|
-|17 |LD | 10|
-|18 |IBUF | 57|
-|19 |IOBUF | 2|
-|20 |OBUF | 44|
+|2 |CARRY4 | 20|
+|3 |DSP48E1 | 2|
+|4 |LUT1 | 41|
+|5 |LUT2 | 115|
+|6 |LUT3 | 34|
+|7 |LUT4 | 78|
+|8 |LUT5 | 55|
+|9 |LUT6 | 245|
+|10 |MUXF7 | 64|
+|11 |MUXF8 | 32|
+|12 |FDCE | 632|
+|13 |FDPE | 2|
+|14 |FDRE | 239|
+|15 |FDSE | 20|
+|16 |LD | 10|
+|17 |IBUF | 9|
+|18 |IOBUF | 2|
+|19 |OBUF | 10|
+------+--------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 1 critical warnings and 23 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2688.422 ; gain = 534.281 ; free physical = 5097 ; free virtual = 14358
-Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.430 ; gain = 607.219 ; free physical = 5095 ; free virtual = 14357
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2759.355 ; gain = 530.344 ; free physical = 2684 ; free virtual = 12637
+Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.363 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2688.430 ; gain = 0.000 ; free physical = 5392 ; free virtual = 14655
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2759.363 ; gain = 0.000 ; free physical = 2969 ; free virtual = 12920
INFO: [Netlist 29-17] Analyzing 130 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2688.430 ; gain = 0.000 ; free physical = 5328 ; free virtual = 14592
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2759.363 ; gain = 0.000 ; free physical = 2978 ; free virtual = 12929
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 12 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
LD => LDCE: 10 instances
-Synth Design complete | Checksum: c0995345
+Synth Design complete | Checksum: 37e28a73
INFO: [Common 17-83] Releasing license: Synthesis
-112 Infos, 167 Warnings, 1 Critical Warnings and 0 Errors encountered.
+58 Infos, 72 Warnings, 1 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:48 . Memory (MB): peak = 2688.430 ; gain = 993.969 ; free physical = 5319 ; free virtual = 14584
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2274.703; main = 1919.844; forked = 402.079
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3749.527; main = 2688.426; forked = 1061.102
+synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2759.363 ; gain = 1064.938 ; free physical = 2979 ; free virtual = 12930
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2251.291; main = 1929.988; forked = 387.510
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3808.555; main = 2759.359; forked = 1049.195
INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2712.434 ; gain = 0.000 ; free physical = 5315 ; free virtual = 14580
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2783.367 ; gain = 0.000 ; free physical = 2981 ; free virtual = 12932
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri May 9 16:20:34 2025...
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:26:59 2025...
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb
index 3d1cb5d828a3e6e04ebf438ca6a7834f268cb835..32b82498090109d0b665f838787a25c6b124ada1 100644
Binary files a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb and b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
index 4fa63f43cf980e7cbb3dad9d75fbaa55c9997566..3237c344dc86cbbac67fc281890291894d4ee713 100644
--- a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
+++ b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Fri May 9 16:20:33 2025
+| Date : Mon May 12 16:26:59 2025
| Host : fl-tp-br-520 running 64-bit Ubuntu 24.04.2 LTS
| Command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
| Design : audioProc
@@ -31,8 +31,8 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs* | 575 | 0 | 0 | 134600 | 0.43 |
-| LUT as Logic | 575 | 0 | 0 | 134600 | 0.43 |
+| Slice LUTs* | 568 | 0 | 0 | 134600 | 0.42 |
+| LUT as Logic | 568 | 0 | 0 | 134600 | 0.42 |
| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
| Slice Registers | 903 | 0 | 0 | 269200 | 0.34 |
| Register as Flip Flop | 893 | 0 | 0 | 269200 | 0.33 |
@@ -119,7 +119,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
-| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
@@ -154,14 +154,14 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 632 | Flop & Latch |
-| LUT6 | 248 | LUT |
+| LUT6 | 245 | LUT |
| FDRE | 239 | Flop & Latch |
-| LUT2 | 119 | LUT |
-| LUT4 | 79 | LUT |
+| LUT2 | 115 | LUT |
+| LUT4 | 78 | LUT |
| MUXF7 | 64 | MuxFx |
-| LUT5 | 52 | LUT |
+| LUT5 | 55 | LUT |
| LUT1 | 41 | LUT |
-| LUT3 | 36 | LUT |
+| LUT3 | 34 | LUT |
| MUXF8 | 32 | MuxFx |
| FDSE | 20 | Flop & Latch |
| CARRY4 | 20 | CarryLogic |
@@ -171,7 +171,6 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| OBUFT | 2 | IO |
| FDPE | 2 | Flop & Latch |
| DSP48E1 | 2 | Block Arithmetic |
-| BUFG | 2 | Clock |
+----------+------+---------------------+
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
index 4e877819e8a3de6b753db92714f0f8a9ba5f3d86..74335ab7d1eb481fb6ee198e887ac81d09bd48b6 100644
--- a/proj/AudioProc.runs/synth_1/gen_run.xml
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1746800341">
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747059929" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/audioProc.dcp">
<File Type="VDS-TIMINGSUMMARY" Name="audioProc_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="audioProc.dcp"/>
<File Type="RDS-UTIL-PB" Name="audioProc_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="audioProc_utilization_synth.rpt"/>
+ <File Type="RDS-PROPCONSTRS" Name="audioProc_drc_synth.rpt"/>
+ <File Type="RDS-RDS" Name="audioProc.vds"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
<File Type="VDS-TIMING-PB" Name="audioProc_timing_summary_synth.pb"/>
<File Type="PA-TCL" Name="audioProc.tcl"/>
- <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
- <File Type="RDS-RDS" Name="audioProc.vds"/>
- <File Type="RDS-PROPCONSTRS" Name="audioProc_drc_synth.rpt"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
@@ -32,20 +32,19 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -76,16 +75,17 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
<FileInfo>
- <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -109,14 +109,20 @@
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/audioProc.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
- <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
- </StratHandle>
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design">
<Option Id="FsmExtraction">1</Option>
<Option Id="KeepEquivalentRegisters">1</Option>
diff --git a/proj/AudioProc.runs/synth_1/incr_synth_reason.pb b/proj/AudioProc.runs/synth_1/incr_synth_reason.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4cb4ed43e865edf4e8dcb3c9857bfe8acfc68b23
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/incr_synth_reason.pb
@@ -0,0 +1 @@
+� 6No compile time benefit to using incremental synthesis
\ No newline at end of file
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
index 2b13f060156f6e5e14d028cb50bc2692aa235868..e0dd417a487e18fad516672a520e2c1774e790d7 100644
--- a/proj/AudioProc.runs/synth_1/runme.log
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -7,16 +7,19 @@
**** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
**** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
**** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
- **** Start of session at: Fri May 9 16:19:05 2025
+ **** Start of session at: Mon May 12 16:25:33 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 6410 ; free virtual = 15595
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.551 ; gain = 325.840 ; free physical = 3993 ; free virtual = 13934
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: read_checkpoint -auto_incremental -incremental /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
Starting synth_design
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
@@ -31,14 +34,16 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
INFO: [Device 21-403] Loading part xc7a200tsbg484-1
INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 114883
+INFO: [Synth 8-7075] Helper process launched with PID 128517
---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2503.699 ; gain = 422.496 ; free physical = 5196 ; free virtual = 14422
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2501.820 ; gain = 420.559 ; free physical = 2869 ; free virtual = 12812
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:13]
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/.Xil/Vivado-114720-fl-tp-br-520/realtime/clk_wiz_0_stub.vhdl:18]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/.Xil/Vivado-128373-fl-tp-br-520/realtime/clk_wiz_0_stub.vhdl:18]
WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:87]
WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:87]
INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audio_init.v:24]
@@ -65,124 +70,8 @@ INFO: [Synth 8-6054] Found Dynamic range expression with variable size [/homes/m
INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd:42]
INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd:45]
-INFO: [Synth 8-6157] synthesizing module 'operativeUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:17]
-INFO: [Synth 8-6157] synthesizing module 'GND' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6155] done synthesizing module 'GND' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6157] synthesizing module 'OBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6157] synthesizing module 'LUT3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
- Parameter INIT bound to: 8'b10000000
-INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'DSP48E1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
- Parameter ACASCREG bound to: 0 - type: integer
- Parameter ADREG bound to: 1 - type: integer
- Parameter ALUMODEREG bound to: 0 - type: integer
- Parameter AREG bound to: 0 - type: integer
- Parameter AUTORESET_PATDET bound to: NO_RESET - type: string
- Parameter A_INPUT bound to: DIRECT - type: string
- Parameter BCASCREG bound to: 0 - type: integer
- Parameter BREG bound to: 0 - type: integer
- Parameter B_INPUT bound to: DIRECT - type: string
- Parameter CARRYINREG bound to: 0 - type: integer
- Parameter CARRYINSELREG bound to: 0 - type: integer
- Parameter CREG bound to: 0 - type: integer
- Parameter DREG bound to: 1 - type: integer
- Parameter INMODEREG bound to: 0 - type: integer
- Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111
- Parameter MREG bound to: 0 - type: integer
- Parameter OPMODEREG bound to: 0 - type: integer
- Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000
- Parameter PREG bound to: 0 - type: integer
- Parameter SEL_MASK bound to: MASK - type: string
- Parameter SEL_PATTERN bound to: PATTERN - type: string
- Parameter USE_DPORT bound to: FALSE - type: string
- Parameter USE_MULT bound to: MULTIPLY - type: string
- Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string
- Parameter USE_SIMD bound to: ONE48 - type: string
-INFO: [Synth 8-6155] done synthesizing module 'DSP48E1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
-WARNING: [Synth 8-689] width (36) of port connection 'P' does not match port width (48) of module 'DSP48E1' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:422]
-WARNING: [Synth 8-7071] port 'ACOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'BCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYCASCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'MULTSIGNOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'OVERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNBDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'UNDERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7023] instance 'SC_addResult' of module 'DSP48E1' has 49 connections declared, but only 39 given [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:394]
-INFO: [Synth 8-6157] synthesizing module 'LUT2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b0110
-INFO: [Synth 8-6155] done synthesizing module 'LUT2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1011111111111101
-INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
- Parameter INIT bound to: 64'b1010111110100000110011111100111110101111101000001100000011000000
-INFO: [Synth 8-6155] done synthesizing module 'LUT6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0101100000011010
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1111011001101111
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0001111001111000
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1110100110010111
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0110000110000110
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
- Parameter INIT bound to: 8'b01000010
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1010001001000101
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1111000110001111
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b1101010110101011
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'FDCE' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
- Parameter INIT bound to: 1'b0
-INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
-INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:1478]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b0001
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
- Parameter INIT bound to: 8'b00000110
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
- Parameter INIT bound to: 16'b0000000001101010
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b1110
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
- Parameter INIT bound to: 32'b00000000000000000110101010101010
-INFO: [Synth 8-6155] done synthesizing module 'LUT5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
- Parameter INIT bound to: 4'b0010
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'VCC' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'VCC' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'operativeUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:17]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/fir.vhd:28]
WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:199]
@@ -231,20 +120,18 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2589.668 ; gain = 508.465 ; free physical = 5105 ; free virtual = 14324
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2585.789 ; gain = 504.527 ; free physical = 2762 ; free virtual = 12703
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2607.480 ; gain = 526.277 ; free physical = 5105 ; free virtual = 14324
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2603.602 ; gain = 522.340 ; free physical = 2758 ; free virtual = 12700
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2607.480 ; gain = 526.277 ; free physical = 5105 ; free virtual = 14324
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2603.602 ; gain = 522.340 ; free physical = 2758 ; free virtual = 12700
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2613.418 ; gain = 0.000 ; free physical = 5097 ; free virtual = 14316
-INFO: [Netlist 29-17] Analyzing 106 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2603.602 ; gain = 0.000 ; free physical = 2758 ; free virtual = 12700
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -259,20 +146,22 @@ Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24
Finished Parsing XDC File [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2680.418 ; gain = 0.000 ; free physical = 5090 ; free virtual = 14324
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2751.352 ; gain = 0.000 ; free physical = 2742 ; free virtual = 12683
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2680.418 ; gain = 0.000 ; free physical = 5090 ; free virtual = 14324
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2751.352 ; gain = 0.000 ; free physical = 2741 ; free virtual = 12683
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2680.418 ; gain = 599.215 ; free physical = 4992 ; free virtual = 14238
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2751.352 ; gain = 670.090 ; free physical = 2737 ; free virtual = 12682
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a200tsbg484-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 4992 ; free virtual = 14238
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2737 ; free virtual = 12682
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
@@ -280,7 +169,7 @@ Start Applying 'set_property' XDC Constraints
Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5000 ; free virtual = 14246
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2737 ; free virtual = 12682
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
INFO: [Synth 8-802] inferred FSM for state register 'SR_currentState_reg' in module 'controlUnit'
@@ -310,7 +199,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding
INFO: [Synth 8-3354] encoded FSM with state register 'SR_currentState_reg' using encoding 'one-hot' in module 'controlUnit'
WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_nextState_reg' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd:64]
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5025 ; free virtual = 14259
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2732 ; free virtual = 12676
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -320,39 +209,44 @@ Detailed RTL Component Info :
2 Input 32 Bit Adders := 3
2 Input 31 Bit Adders := 1
2 Input 24 Bit Adders := 2
+ 2 Input 16 Bit Adders := 2
2 Input 13 Bit Adders := 5
2 Input 7 Bit Adders := 3
2 Input 5 Bit Adders := 2
- 2 Input 4 Bit Adders := 1
+ 2 Input 4 Bit Adders := 3
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
+ 36 Bit Registers := 2
33 Bit Registers := 1
32 Bit Registers := 3
31 Bit Registers := 1
24 Bit Registers := 2
+ 16 Bit Registers := 34
13 Bit Registers := 5
8 Bit Registers := 3
7 Bit Registers := 3
5 Bit Registers := 4
- 4 Bit Registers := 2
+ 4 Bit Registers := 4
3 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 18
+---Muxes :
+ 2 Input 36 Bit Muxes := 2
2 Input 32 Bit Muxes := 3
2 Input 24 Bit Muxes := 2
2 Input 16 Bit Muxes := 6
+ 16 Input 12 Bit Muxes := 2
2 Input 8 Bit Muxes := 2
2 Input 5 Bit Muxes := 9
8 Input 5 Bit Muxes := 1
5 Input 5 Bit Muxes := 2
9 Input 4 Bit Muxes := 1
21 Input 4 Bit Muxes := 1
- 2 Input 4 Bit Muxes := 7
+ 2 Input 4 Bit Muxes := 9
5 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 39
+ 2 Input 1 Bit Muxes := 43
4 Input 1 Bit Muxes := 21
3 Input 1 Bit Muxes := 5
9 Input 1 Bit Muxes := 1
@@ -376,6 +270,12 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
@@ -398,25 +298,43 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 4975 ; free virtual = 14230
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2699 ; free virtual = 12649
+---------------------------------------------------------------------------------
+ Sort Area is firUnit_1/operativeUnit_1/SC_addResult_0 : 0 0 : 1641 1641 : Used 1 time 0
+ Sort Area is firUnit_1/operativeUnit_1/SC_addResult_2 : 0 0 : 1641 1641 : Used 1 time 0
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B | 16 | 13 | 36 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
+|operativeUnit | C+A*B | 16 | 13 | 36 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5085 ; free virtual = 14344
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2709 ; free virtual = 12656
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5087 ; free virtual = 14346
+Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2693 ; free virtual = 12645
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5088 ; free virtual = 14347
+Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2686 ; free virtual = 12635
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -436,49 +354,49 @@ Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|operativeUnit_3 | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
-|operativeUnit | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
+|operativeUnit | C+A*B | 30 | 12 | 48 | - | 36 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
@@ -493,217 +411,52 @@ Report Cell Usage:
| |Cell |Count |
+------+--------+------+
|1 |clk_wiz | 1|
-|2 |BUFG | 2|
-|3 |CARRY4 | 20|
-|4 |DSP48E1 | 2|
-|5 |LUT1 | 41|
-|6 |LUT2 | 119|
-|7 |LUT3 | 36|
-|8 |LUT4 | 79|
-|9 |LUT5 | 52|
-|10 |LUT6 | 248|
-|11 |MUXF7 | 64|
-|12 |MUXF8 | 32|
-|13 |FDCE | 632|
-|14 |FDPE | 2|
-|15 |FDRE | 239|
-|16 |FDSE | 20|
-|17 |LD | 10|
-|18 |IBUF | 57|
-|19 |IOBUF | 2|
-|20 |OBUF | 44|
+|2 |CARRY4 | 20|
+|3 |DSP48E1 | 2|
+|4 |LUT1 | 41|
+|5 |LUT2 | 115|
+|6 |LUT3 | 34|
+|7 |LUT4 | 78|
+|8 |LUT5 | 55|
+|9 |LUT6 | 245|
+|10 |MUXF7 | 64|
+|11 |MUXF8 | 32|
+|12 |FDCE | 632|
+|13 |FDPE | 2|
+|14 |FDRE | 239|
+|15 |FDSE | 20|
+|16 |LD | 10|
+|17 |IBUF | 9|
+|18 |IOBUF | 2|
+|19 |OBUF | 10|
+------+--------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.422 ; gain = 607.219 ; free physical = 5097 ; free virtual = 14358
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.355 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 1 critical warnings and 23 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2688.422 ; gain = 534.281 ; free physical = 5097 ; free virtual = 14358
-Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2688.430 ; gain = 607.219 ; free physical = 5095 ; free virtual = 14357
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2759.355 ; gain = 530.344 ; free physical = 2684 ; free virtual = 12637
+Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2759.363 ; gain = 678.094 ; free physical = 2684 ; free virtual = 12637
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2688.430 ; gain = 0.000 ; free physical = 5392 ; free virtual = 14655
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2759.363 ; gain = 0.000 ; free physical = 2969 ; free virtual = 12920
INFO: [Netlist 29-17] Analyzing 130 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2688.430 ; gain = 0.000 ; free physical = 5328 ; free virtual = 14592
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2759.363 ; gain = 0.000 ; free physical = 2978 ; free virtual = 12929
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 12 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 2 instances
LD => LDCE: 10 instances
-Synth Design complete | Checksum: c0995345
+Synth Design complete | Checksum: 37e28a73
INFO: [Common 17-83] Releasing license: Synthesis
-112 Infos, 167 Warnings, 1 Critical Warnings and 0 Errors encountered.
+58 Infos, 72 Warnings, 1 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:48 . Memory (MB): peak = 2688.430 ; gain = 993.969 ; free physical = 5319 ; free virtual = 14584
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2274.703; main = 1919.844; forked = 402.079
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3749.527; main = 2688.426; forked = 1061.102
+synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2759.363 ; gain = 1064.938 ; free physical = 2979 ; free virtual = 12930
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2251.291; main = 1929.988; forked = 387.510
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3808.555; main = 2759.359; forked = 1049.195
INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2712.434 ; gain = 0.000 ; free physical = 5315 ; free virtual = 14580
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2783.367 ; gain = 0.000 ; free physical = 2981 ; free virtual = 12932
INFO: [Common 17-1381] The checkpoint '/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri May 9 16:20:34 2025...
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:26:59 2025...
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
index 26f7130843913368c2b48b2bd6a866af427559e8..6c81d19c0535c714901bdb76b476a12ee32b6af5 100644
--- a/proj/AudioProc.runs/synth_1/vivado.jou
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May 9 16:19:05 2025
-# Process ID: 114720
+# Start of session at: Mon May 12 16:25:33 2025
+# Process ID: 128373
# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1
# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -13,12 +13,12 @@
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4288.160 MHz
+# CPU Frequency :4357.542 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
-# Available Virtual :16979 MB
+# Available Virtual :15128 MB
#-----------------------------------------------------------
source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
index 98ffc47411fe66cc7f355fbd7eb8bcb14e5e7d0e..299daa62269bee7a4880835da88b49d17ecaa5da 100644
Binary files a/proj/AudioProc.runs/synth_1/vivado.pb and b/proj/AudioProc.runs/synth_1/vivado.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/.nfs000000000260de590000012e b/proj/AudioProc.sim/sim_1/behav/xsim/.nfs000000000260de590000012e
deleted file mode 100644
index 79a058010db34189da47e53ae7ae5b8953865743..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/.nfs000000000260de590000012e
+++ /dev/null
@@ -1,55 +0,0 @@
-Vivado Simulator v2024.1
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot audioProc_behav xil_defaultlib.audioProc xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Pass Through NonSizing Optimizer
-WARNING: [VRFC 10-9380] size mismatch in mixed-language port association of VHDL port 'en_tx_i' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:138]
-WARNING: [VRFC 10-3091] actual bit length 36 differs from formal bit length 48 for port 'P' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:422]
-WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'CO' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:1478]
-WARNING: [VRFC 10-5021] port 'reset' is not connected on this instance [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:87]
-WARNING: [VRFC 10-5021] port 'dbg_output_0' is not connected on this instance [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:199]
-WARNING: [VRFC 10-5021] port 'dbg_output_0' is not connected on this instance [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v:208]
-Completed static elaboration
-Starting simulation data flow analysis
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling package std.standard
-Compiling package std.textio
-Compiling package ieee.std_logic_1164
-Compiling package ieee.std_logic_arith
-Compiling package ieee.std_logic_unsigned
-Compiling package ieee.math_real
-Compiling package ieee.numeric_std
-Compiling module unisims_ver.IBUF
-Compiling module unisims_ver.MMCME2_ADV(CLKFBOUT_MULT_F=6.0,C...
-Compiling module unisims_ver.BUFG
-Compiling module xil_defaultlib.clk_wiz_0_clk_wiz
-Compiling module xil_defaultlib.clk_wiz_0
-Compiling architecture behavioral of entity xil_defaultlib.TWICtl [twictl_default]
-Compiling module xil_defaultlib.audio_init
-Compiling module xil_defaultlib.debounce
-Compiling architecture behavioral of entity xil_defaultlib.i2s_ctl [i2s_ctl_default]
-Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
-Compiling module unisims_ver.GND
-Compiling module unisims_ver.OBUF
-Compiling module unisims_ver.x_lut3_mux8
-Compiling module unisims_ver.LUT3
-Compiling module unisims_ver.DSP48E1(ACASCREG=0,ALUMODEREG=0,...
-Compiling module unisims_ver.x_lut2_mux4
-Compiling module unisims_ver.LUT2
-Compiling module unisims_ver.LUT4
-Compiling module unisims_ver.LUT6
-Compiling module unisims_ver.MUXF8
-Compiling module unisims_ver.MUXF7
-Compiling module unisims_ver.FDCE_default
-Compiling module unisims_ver.CARRY4
-Compiling module unisims_ver.LUT5(INIT=32'b0110101010101010)
-Compiling module unisims_ver.VCC
-Compiling module xil_defaultlib.operativeUnit
-Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
-Compiling architecture myarch of entity xil_defaultlib.fir [\fir(ntaps=16)\]
-Compiling module xil_defaultlib.audioProc
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot audioProc_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/.nfs000000000260de6f0000012f b/proj/AudioProc.sim/sim_1/behav/xsim/.nfs000000000260de6f0000012f
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
deleted file mode 100644
index 3b5d77ebb8fde4e3736c8b046ff863d3d5203e80..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
+++ /dev/null
@@ -1,2 +0,0 @@
-INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
index 78462d1e08d81feda83f207097f1943b305f1a8e..5876f7e7638257b60a4d35b1d7dbba3ed3e437ba 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
-# Generated by Vivado on Fri May 09 15:52:36 CEST 2025
+# Generated by Vivado on Mon May 12 16:24:12 CEST 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -16,13 +16,9 @@
#
# ****************************************************************************
set -Eeuo pipefail
-# compile Verilog/System Verilog design sources
-echo "xvlog --incr --relax -prj tb_firUnit_vlog.prj"
-xvlog --incr --relax -prj tb_firUnit_vlog.prj 2>&1 | tee compile.log
-
# compile VHDL design sources
echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
-xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee -a compile.log
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee compile.log
echo "Waiting for jobs to finish..."
echo "No pending jobs, compilation finished."
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
index 2d15452e9d40cda65725f42508fa04fb18014f2f..ca74b1ceae89ecaafc2730eed71d53d797cf5f35 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
@@ -1,12 +1,9 @@
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
Using 8 slave threads.
Starting static elaboration
-Pass Through NonSizing Optimizer
-WARNING: [VRFC 10-3091] actual bit length 36 differs from formal bit length 48 for port 'P' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:422]
-WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'CO' [/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v:1478]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
@@ -15,27 +12,8 @@ Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
-Compiling package vl.vl_types
-Compiling module xil_defaultlib.glbl
Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
-Compiling module unisims_ver.GND
-Compiling module unisims_ver.BUFG
-Compiling module unisims_ver.IBUF
-Compiling module unisims_ver.OBUF
-Compiling module unisims_ver.x_lut3_mux8
-Compiling module unisims_ver.LUT3
-Compiling module unisims_ver.DSP48E1(ACASCREG=0,ALUMODEREG=0,...
-Compiling module unisims_ver.x_lut2_mux4
-Compiling module unisims_ver.LUT2
-Compiling module unisims_ver.LUT4
-Compiling module unisims_ver.LUT6
-Compiling module unisims_ver.MUXF8
-Compiling module unisims_ver.MUXF7
-Compiling module unisims_ver.FDCE_default
-Compiling module unisims_ver.CARRY4
-Compiling module unisims_ver.LUT5(INIT=32'b0110101010101010)
-Compiling module unisims_ver.VCC
-Compiling module xil_defaultlib.operativeUnit
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
Built simulation snapshot tb_firUnit_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
index d32d6f62bccfd9f1ec861c15cd23d653fdd75371..c8774794bb35babb059fcecc8b643639e079d08d 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
-# Generated by Vivado on Fri May 09 15:52:38 CEST 2025
+# Generated by Vivado on Mon May 12 16:24:14 CEST 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -17,6 +17,6 @@
# ****************************************************************************
set -Eeuo pipefail
# elaborate design
-echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log"
-xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
index 14236a3903208f0693c61b72eb3adcedbad2c068..ee87b5f24b607a90ae366bde3af746cd8a7a128d 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
-# Generated by Vivado on Fri May 09 15:52:44 CEST 2025
+# Generated by Vivado on Mon May 12 15:34:25 CEST 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index 359990173cd42ad5cff6b42af0987f385ee342cc..5a39a9c06c7c6becf8a05791a41186f8c13c49e7 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb and b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
index f5164303db8b7813dd76fdb363b7c18c0c679809..0107b4e0d82614c83b8f672cdff5fbeac1c3cfc2 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -1,6 +1,7 @@
# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
"../../../../../src/hdl/firUnit.vhd" \
"../../../../../src/hdl/tb_firUnit.vhd" \
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
deleted file mode 100644
index 4918d41c886ff6e9c7b433572c2692552e42d4f0..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
+++ /dev/null
@@ -1,9 +0,0 @@
-# compile verilog/system verilog design source files
-verilog xil_defaultlib \
-"../../../../../src/hdl/operativeUnit.v" \
-
-# compile glbl module
-verilog xil_defaultlib "glbl.v"
-
-# Do not sort compile order
-nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb
index 468a6403c4d67b7af81e6821f43a5ce710d857b8..f17fb2dfa33c0317a5b8bf49cd8cf2f51e64bf31 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb and b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
index 2965ab3b73825075d89f3fba7755ebff3606c69a..8a25a911b8deeb63be565a8d140a089d2d79bd2f 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -1 +1 @@
---incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" "xil_defaultlib.glbl" -log "elaborate.log"
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log"
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
index 573e796a729516424ace4e17f82292d7adcc2970..8f0b409a528019b10f877c514e6fb086eeff0ed2 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
index 82891810cefac246dd5535788ebac91bf57678ef..c9f38b089b7890e304c5c8351f5a219f05e35b77 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -54,595 +54,40 @@
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
-IKI_DLLESPEC extern void execute_2(char*, char *);
-IKI_DLLESPEC extern void execute_3(char*, char *);
-IKI_DLLESPEC extern void execute_4(char*, char *);
-IKI_DLLESPEC extern void execute_5(char*, char *);
-IKI_DLLESPEC extern void execute_6(char*, char *);
-IKI_DLLESPEC extern void execute_7(char*, char *);
-IKI_DLLESPEC extern void execute_8(char*, char *);
-IKI_DLLESPEC extern void execute_9(char*, char *);
-IKI_DLLESPEC extern void execute_10(char*, char *);
-IKI_DLLESPEC extern void execute_11(char*, char *);
-IKI_DLLESPEC extern void execute_21(char*, char *);
-IKI_DLLESPEC extern void execute_22(char*, char *);
-IKI_DLLESPEC extern void execute_23(char*, char *);
-IKI_DLLESPEC extern void execute_24(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
IKI_DLLESPEC extern void execute_27(char*, char *);
IKI_DLLESPEC extern void execute_28(char*, char *);
IKI_DLLESPEC extern void execute_29(char*, char *);
-IKI_DLLESPEC extern void execute_30(char*, char *);
-IKI_DLLESPEC extern void execute_31(char*, char *);
IKI_DLLESPEC extern void execute_32(char*, char *);
IKI_DLLESPEC extern void execute_33(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
-IKI_DLLESPEC extern void execute_3821(char*, char *);
-IKI_DLLESPEC extern void execute_3822(char*, char *);
-IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
-IKI_DLLESPEC extern void execute_1958(char*, char *);
-IKI_DLLESPEC extern void execute_41(char*, char *);
-IKI_DLLESPEC extern void execute_1959(char*, char *);
-IKI_DLLESPEC extern void execute_89(char*, char *);
-IKI_DLLESPEC extern void execute_1983(char*, char *);
-IKI_DLLESPEC extern void execute_1984(char*, char *);
-IKI_DLLESPEC extern void execute_1985(char*, char *);
-IKI_DLLESPEC extern void execute_124(char*, char *);
-IKI_DLLESPEC extern void execute_2035(char*, char *);
-IKI_DLLESPEC extern void execute_2036(char*, char *);
-IKI_DLLESPEC extern void execute_2037(char*, char *);
-IKI_DLLESPEC extern void execute_2038(char*, char *);
-IKI_DLLESPEC extern void execute_2039(char*, char *);
-IKI_DLLESPEC extern void execute_2040(char*, char *);
-IKI_DLLESPEC extern void execute_2041(char*, char *);
-IKI_DLLESPEC extern void execute_2042(char*, char *);
-IKI_DLLESPEC extern void execute_2034(char*, char *);
-IKI_DLLESPEC extern void execute_126(char*, char *);
-IKI_DLLESPEC extern void execute_127(char*, char *);
-IKI_DLLESPEC extern void execute_128(char*, char *);
-IKI_DLLESPEC extern void execute_129(char*, char *);
-IKI_DLLESPEC extern void execute_130(char*, char *);
-IKI_DLLESPEC extern void execute_131(char*, char *);
-IKI_DLLESPEC extern void execute_132(char*, char *);
-IKI_DLLESPEC extern void execute_133(char*, char *);
-IKI_DLLESPEC extern void execute_134(char*, char *);
-IKI_DLLESPEC extern void execute_135(char*, char *);
-IKI_DLLESPEC extern void execute_136(char*, char *);
-IKI_DLLESPEC extern void execute_137(char*, char *);
-IKI_DLLESPEC extern void execute_138(char*, char *);
-IKI_DLLESPEC extern void execute_139(char*, char *);
-IKI_DLLESPEC extern void execute_140(char*, char *);
-IKI_DLLESPEC extern void execute_141(char*, char *);
-IKI_DLLESPEC extern void execute_142(char*, char *);
-IKI_DLLESPEC extern void execute_143(char*, char *);
-IKI_DLLESPEC extern void execute_144(char*, char *);
-IKI_DLLESPEC extern void execute_145(char*, char *);
-IKI_DLLESPEC extern void execute_146(char*, char *);
-IKI_DLLESPEC extern void execute_147(char*, char *);
-IKI_DLLESPEC extern void execute_148(char*, char *);
-IKI_DLLESPEC extern void execute_149(char*, char *);
-IKI_DLLESPEC extern void execute_150(char*, char *);
-IKI_DLLESPEC extern void execute_151(char*, char *);
-IKI_DLLESPEC extern void execute_152(char*, char *);
-IKI_DLLESPEC extern void execute_153(char*, char *);
-IKI_DLLESPEC extern void execute_156(char*, char *);
-IKI_DLLESPEC extern void execute_157(char*, char *);
-IKI_DLLESPEC extern void execute_158(char*, char *);
-IKI_DLLESPEC extern void execute_159(char*, char *);
-IKI_DLLESPEC extern void execute_160(char*, char *);
-IKI_DLLESPEC extern void execute_161(char*, char *);
-IKI_DLLESPEC extern void execute_162(char*, char *);
-IKI_DLLESPEC extern void execute_163(char*, char *);
-IKI_DLLESPEC extern void execute_164(char*, char *);
-IKI_DLLESPEC extern void execute_165(char*, char *);
-IKI_DLLESPEC extern void execute_166(char*, char *);
-IKI_DLLESPEC extern void execute_167(char*, char *);
-IKI_DLLESPEC extern void execute_168(char*, char *);
-IKI_DLLESPEC extern void execute_169(char*, char *);
-IKI_DLLESPEC extern void execute_170(char*, char *);
-IKI_DLLESPEC extern void execute_171(char*, char *);
-IKI_DLLESPEC extern void execute_2043(char*, char *);
-IKI_DLLESPEC extern void execute_2044(char*, char *);
-IKI_DLLESPEC extern void execute_2045(char*, char *);
-IKI_DLLESPEC extern void execute_2046(char*, char *);
-IKI_DLLESPEC extern void execute_2047(char*, char *);
-IKI_DLLESPEC extern void execute_2048(char*, char *);
-IKI_DLLESPEC extern void execute_2049(char*, char *);
-IKI_DLLESPEC extern void execute_2050(char*, char *);
-IKI_DLLESPEC extern void execute_2051(char*, char *);
-IKI_DLLESPEC extern void execute_2052(char*, char *);
-IKI_DLLESPEC extern void execute_2053(char*, char *);
-IKI_DLLESPEC extern void execute_2054(char*, char *);
-IKI_DLLESPEC extern void execute_2055(char*, char *);
-IKI_DLLESPEC extern void execute_2056(char*, char *);
-IKI_DLLESPEC extern void execute_2057(char*, char *);
-IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
-IKI_DLLESPEC extern void vlog_simple_process_execute_1_fast_no_reg_no_agg(char*, char*, char*);
-IKI_DLLESPEC extern void execute_2098(char*, char *);
-IKI_DLLESPEC extern void execute_2103(char*, char *);
-IKI_DLLESPEC extern void execute_2118(char*, char *);
-IKI_DLLESPEC extern void execute_2120(char*, char *);
-IKI_DLLESPEC extern void execute_2122(char*, char *);
-IKI_DLLESPEC extern void execute_2134(char*, char *);
-IKI_DLLESPEC extern void execute_2135(char*, char *);
-IKI_DLLESPEC extern void execute_2136(char*, char *);
-IKI_DLLESPEC extern void execute_2138(char*, char *);
-IKI_DLLESPEC extern void execute_2139(char*, char *);
-IKI_DLLESPEC extern void execute_2140(char*, char *);
-IKI_DLLESPEC extern void execute_2141(char*, char *);
-IKI_DLLESPEC extern void execute_2142(char*, char *);
-IKI_DLLESPEC extern void execute_2143(char*, char *);
-IKI_DLLESPEC extern void execute_2144(char*, char *);
-IKI_DLLESPEC extern void execute_2145(char*, char *);
-IKI_DLLESPEC extern void execute_2147(char*, char *);
-IKI_DLLESPEC extern void execute_2148(char*, char *);
-IKI_DLLESPEC extern void execute_2149(char*, char *);
-IKI_DLLESPEC extern void execute_2150(char*, char *);
-IKI_DLLESPEC extern void execute_2151(char*, char *);
-IKI_DLLESPEC extern void execute_2152(char*, char *);
-IKI_DLLESPEC extern void execute_2153(char*, char *);
-IKI_DLLESPEC extern void execute_2154(char*, char *);
-IKI_DLLESPEC extern void execute_2155(char*, char *);
-IKI_DLLESPEC extern void execute_2156(char*, char *);
-IKI_DLLESPEC extern void execute_2157(char*, char *);
-IKI_DLLESPEC extern void execute_2162(char*, char *);
-IKI_DLLESPEC extern void execute_2163(char*, char *);
-IKI_DLLESPEC extern void execute_2164(char*, char *);
-IKI_DLLESPEC extern void execute_2165(char*, char *);
-IKI_DLLESPEC extern void execute_2166(char*, char *);
-IKI_DLLESPEC extern void execute_2167(char*, char *);
-IKI_DLLESPEC extern void execute_2168(char*, char *);
-IKI_DLLESPEC extern void execute_2169(char*, char *);
-IKI_DLLESPEC extern void execute_2170(char*, char *);
-IKI_DLLESPEC extern void execute_2171(char*, char *);
-IKI_DLLESPEC extern void execute_2172(char*, char *);
-IKI_DLLESPEC extern void execute_2173(char*, char *);
-IKI_DLLESPEC extern void execute_2174(char*, char *);
-IKI_DLLESPEC extern void execute_2175(char*, char *);
-IKI_DLLESPEC extern void execute_2176(char*, char *);
-IKI_DLLESPEC extern void execute_2177(char*, char *);
-IKI_DLLESPEC extern void execute_2178(char*, char *);
-IKI_DLLESPEC extern void execute_2179(char*, char *);
-IKI_DLLESPEC extern void execute_2180(char*, char *);
-IKI_DLLESPEC extern void execute_2181(char*, char *);
-IKI_DLLESPEC extern void execute_2182(char*, char *);
-IKI_DLLESPEC extern void execute_2183(char*, char *);
-IKI_DLLESPEC extern void execute_2184(char*, char *);
-IKI_DLLESPEC extern void execute_174(char*, char *);
-IKI_DLLESPEC extern void execute_2186(char*, char *);
-IKI_DLLESPEC extern void execute_2187(char*, char *);
-IKI_DLLESPEC extern void execute_2188(char*, char *);
-IKI_DLLESPEC extern void execute_2189(char*, char *);
-IKI_DLLESPEC extern void execute_2185(char*, char *);
-IKI_DLLESPEC extern void execute_177(char*, char *);
-IKI_DLLESPEC extern void execute_178(char*, char *);
-IKI_DLLESPEC extern void execute_181(char*, char *);
-IKI_DLLESPEC extern void execute_182(char*, char *);
-IKI_DLLESPEC extern void execute_288(char*, char *);
-IKI_DLLESPEC extern void execute_324(char*, char *);
-IKI_DLLESPEC extern void execute_573(char*, char *);
-IKI_DLLESPEC extern void execute_574(char*, char *);
-IKI_DLLESPEC extern void execute_575(char*, char *);
-IKI_DLLESPEC extern void execute_2330(char*, char *);
-IKI_DLLESPEC extern void execute_2331(char*, char *);
-IKI_DLLESPEC extern void execute_2332(char*, char *);
-IKI_DLLESPEC extern void execute_2333(char*, char *);
-IKI_DLLESPEC extern void execute_2342(char*, char *);
-IKI_DLLESPEC extern void execute_2343(char*, char *);
-IKI_DLLESPEC extern void execute_2344(char*, char *);
-IKI_DLLESPEC extern void execute_2347(char*, char *);
-IKI_DLLESPEC extern void execute_2348(char*, char *);
-IKI_DLLESPEC extern void execute_2349(char*, char *);
-IKI_DLLESPEC extern void execute_2350(char*, char *);
-IKI_DLLESPEC extern void execute_656(char*, char *);
-IKI_DLLESPEC extern void execute_657(char*, char *);
-IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_205(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_206(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_207(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_208(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_215(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_237(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_270(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_350(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_994(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1000(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1006(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1020(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1026(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1032(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1038(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1051(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1057(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1063(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1078(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1084(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1090(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1096(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1110(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1116(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1159(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1165(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1171(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1177(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1183(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1189(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1195(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1201(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1207(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1213(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1219(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1225(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1231(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1237(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1243(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1249(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1255(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1261(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1267(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1273(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1279(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1285(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1291(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1297(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1303(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1309(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1315(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1321(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1327(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1333(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1339(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1345(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1351(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1357(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1363(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1369(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1375(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1381(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1387(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1393(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1399(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1405(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1411(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1417(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1423(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1429(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1435(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1441(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1447(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1453(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1459(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1465(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1471(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1477(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1483(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1489(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1495(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1501(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1507(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1513(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1519(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1525(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1531(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1537(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1543(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1549(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1555(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1561(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1567(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1573(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1579(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1585(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1591(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1597(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1603(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1609(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1615(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1621(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1627(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1633(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1639(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1645(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1651(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1657(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1663(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1669(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1675(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1681(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1687(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1693(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1699(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1705(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1711(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1717(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1723(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1729(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1735(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1741(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1747(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1753(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1759(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1765(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1771(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1777(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1783(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1789(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1795(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1801(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1807(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1813(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1819(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1825(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1831(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1837(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1843(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1849(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1855(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1861(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1867(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1873(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1879(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1885(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1891(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1897(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1903(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1909(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1915(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1921(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1927(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1933(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1939(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1945(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1951(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1957(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1963(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1969(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1975(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1981(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1987(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1993(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1999(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2005(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2011(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2017(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2023(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2029(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2035(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2041(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2047(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2053(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2059(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2065(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2071(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2077(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2083(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2089(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2095(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2101(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2107(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2113(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2119(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2125(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2131(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2137(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2143(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2149(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2155(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2161(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2167(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2173(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2179(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2185(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2191(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2197(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2203(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2209(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2215(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2221(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2227(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2233(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2239(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2245(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2251(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2257(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2263(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2269(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2275(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2281(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2287(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2293(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2299(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2305(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2311(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2317(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2323(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2329(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2335(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2341(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2347(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2353(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2359(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2365(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2371(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2377(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2383(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2389(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2395(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2401(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2407(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2413(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2419(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2425(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2431(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2437(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2443(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2449(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2455(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2461(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2467(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2473(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2479(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2485(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2491(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2497(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2503(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2509(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2515(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2521(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2527(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2533(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2539(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2545(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2551(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2557(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2563(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2569(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2575(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2581(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2587(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2593(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2599(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2605(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2611(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2617(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2623(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2629(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2635(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2641(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2647(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2653(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2659(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2665(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2671(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2677(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2683(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2689(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2695(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2701(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2707(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2713(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2941(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2947(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2953(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2959(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2965(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2971(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2977(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2983(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2989(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2995(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3001(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3007(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3013(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3019(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3025(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3031(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3037(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3043(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3049(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3055(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3061(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3067(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3073(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3079(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3085(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3091(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3097(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3103(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3109(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3115(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3121(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3127(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3133(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3139(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3145(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3151(char*, char*, unsigned, unsigned, unsigned);
-funcp funcTab[581] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_3821, (funcp)execute_3822, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_1958, (funcp)execute_41, (funcp)execute_1959, (funcp)execute_89, (funcp)execute_1983, (funcp)execute_1984, (funcp)execute_1985, (funcp)execute_124, (funcp)execute_2035, (funcp)execute_2036, (funcp)execute_2037, (funcp)execute_2038, (funcp)execute_2039, (funcp)execute_2040, (funcp)execute_2041, (funcp)execute_2042, (funcp)execute_2034, (funcp)execute_126, (funcp)execute_127, (funcp)execute_128, (funcp)execute_129, (funcp)execute_130, (funcp)execute_131, (funcp)execute_132, (funcp)execute_133, (funcp)execute_134, (funcp)execute_135, (funcp)execute_136, (funcp)execute_137, (funcp)execute_138, (funcp)execute_139, (funcp)execute_140, (funcp)execute_141, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_145, (funcp)execute_146, (funcp)execute_147, (funcp)execute_148, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_152, (funcp)execute_153, (funcp)execute_156, (funcp)execute_157, (funcp)execute_158, (funcp)execute_159, (funcp)execute_160, (funcp)execute_161, (funcp)execute_162, (funcp)execute_163, (funcp)execute_164, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_168, (funcp)execute_169, (funcp)execute_170, (funcp)execute_171, (funcp)execute_2043, (funcp)execute_2044, (funcp)execute_2045, (funcp)execute_2046, (funcp)execute_2047, (funcp)execute_2048, (funcp)execute_2049, (funcp)execute_2050, (funcp)execute_2051, (funcp)execute_2052, (funcp)execute_2053, (funcp)execute_2054, (funcp)execute_2055, (funcp)execute_2056, (funcp)execute_2057, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)vlog_simple_process_execute_1_fast_no_reg_no_agg, (funcp)execute_2098, (funcp)execute_2103, (funcp)execute_2118, (funcp)execute_2120, (funcp)execute_2122, (funcp)execute_2134, (funcp)execute_2135, (funcp)execute_2136, (funcp)execute_2138, (funcp)execute_2139, (funcp)execute_2140, (funcp)execute_2141, (funcp)execute_2142, (funcp)execute_2143, (funcp)execute_2144, (funcp)execute_2145, (funcp)execute_2147, (funcp)execute_2148, (funcp)execute_2149, (funcp)execute_2150, (funcp)execute_2151, (funcp)execute_2152, (funcp)execute_2153, (funcp)execute_2154, (funcp)execute_2155, (funcp)execute_2156, (funcp)execute_2157, (funcp)execute_2162, (funcp)execute_2163, (funcp)execute_2164, (funcp)execute_2165, (funcp)execute_2166, (funcp)execute_2167, (funcp)execute_2168, (funcp)execute_2169, (funcp)execute_2170, (funcp)execute_2171, (funcp)execute_2172, (funcp)execute_2173, (funcp)execute_2174, (funcp)execute_2175, (funcp)execute_2176, (funcp)execute_2177, (funcp)execute_2178, (funcp)execute_2179, (funcp)execute_2180, (funcp)execute_2181, (funcp)execute_2182, (funcp)execute_2183, (funcp)execute_2184, (funcp)execute_174, (funcp)execute_2186, (funcp)execute_2187, (funcp)execute_2188, (funcp)execute_2189, (funcp)execute_2185, (funcp)execute_177, (funcp)execute_178, (funcp)execute_181, (funcp)execute_182, (funcp)execute_288, (funcp)execute_324, (funcp)execute_573, (funcp)execute_574, (funcp)execute_575, (funcp)execute_2330, (funcp)execute_2331, (funcp)execute_2332, (funcp)execute_2333, (funcp)execute_2342, (funcp)execute_2343, (funcp)execute_2344, (funcp)execute_2347, (funcp)execute_2348, (funcp)execute_2349, (funcp)execute_2350, (funcp)execute_656, (funcp)execute_657, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_38, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_73, (funcp)transaction_183, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_205, (funcp)transaction_206, (funcp)transaction_207, (funcp)transaction_208, (funcp)transaction_215, (funcp)transaction_232, (funcp)transaction_237, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_270, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_298, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_306, (funcp)transaction_309, (funcp)transaction_311, (funcp)transaction_313, (funcp)transaction_315, (funcp)transaction_320, (funcp)transaction_323, (funcp)transaction_329, (funcp)transaction_334, (funcp)transaction_350, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_366, (funcp)transaction_994, (funcp)transaction_1000, (funcp)transaction_1006, (funcp)transaction_1020, (funcp)transaction_1026, (funcp)transaction_1032, (funcp)transaction_1038, (funcp)transaction_1051, (funcp)transaction_1057, (funcp)transaction_1063, (funcp)transaction_1078, (funcp)transaction_1084, (funcp)transaction_1090, (funcp)transaction_1096, (funcp)transaction_1110, (funcp)transaction_1116, (funcp)transaction_1159, (funcp)transaction_1165, (funcp)transaction_1171, (funcp)transaction_1177, (funcp)transaction_1183, (funcp)transaction_1189, (funcp)transaction_1195, (funcp)transaction_1201, (funcp)transaction_1207, (funcp)transaction_1213, (funcp)transaction_1219, (funcp)transaction_1225, (funcp)transaction_1231, (funcp)transaction_1237, (funcp)transaction_1243, (funcp)transaction_1249, (funcp)transaction_1255, (funcp)transaction_1261, (funcp)transaction_1267, (funcp)transaction_1273, (funcp)transaction_1279, (funcp)transaction_1285, (funcp)transaction_1291, (funcp)transaction_1297, (funcp)transaction_1303, (funcp)transaction_1309, (funcp)transaction_1315, (funcp)transaction_1321, (funcp)transaction_1327, (funcp)transaction_1333, (funcp)transaction_1339, (funcp)transaction_1345, (funcp)transaction_1351, (funcp)transaction_1357, (funcp)transaction_1363, (funcp)transaction_1369, (funcp)transaction_1375, (funcp)transaction_1381, (funcp)transaction_1387, (funcp)transaction_1393, (funcp)transaction_1399, (funcp)transaction_1405, (funcp)transaction_1411, (funcp)transaction_1417, (funcp)transaction_1423, (funcp)transaction_1429, (funcp)transaction_1435, (funcp)transaction_1441, (funcp)transaction_1447, (funcp)transaction_1453, (funcp)transaction_1459, (funcp)transaction_1465, (funcp)transaction_1471, (funcp)transaction_1477, (funcp)transaction_1483, (funcp)transaction_1489, (funcp)transaction_1495, (funcp)transaction_1501, (funcp)transaction_1507, (funcp)transaction_1513, (funcp)transaction_1519, (funcp)transaction_1525, (funcp)transaction_1531, (funcp)transaction_1537, (funcp)transaction_1543, (funcp)transaction_1549, (funcp)transaction_1555, (funcp)transaction_1561, (funcp)transaction_1567, (funcp)transaction_1573, (funcp)transaction_1579, (funcp)transaction_1585, (funcp)transaction_1591, (funcp)transaction_1597, (funcp)transaction_1603, (funcp)transaction_1609, (funcp)transaction_1615, (funcp)transaction_1621, (funcp)transaction_1627, (funcp)transaction_1633, (funcp)transaction_1639, (funcp)transaction_1645, (funcp)transaction_1651, (funcp)transaction_1657, (funcp)transaction_1663, (funcp)transaction_1669, (funcp)transaction_1675, (funcp)transaction_1681, (funcp)transaction_1687, (funcp)transaction_1693, (funcp)transaction_1699, (funcp)transaction_1705, (funcp)transaction_1711, (funcp)transaction_1717, (funcp)transaction_1723, (funcp)transaction_1729, (funcp)transaction_1735, (funcp)transaction_1741, (funcp)transaction_1747, (funcp)transaction_1753, (funcp)transaction_1759, (funcp)transaction_1765, (funcp)transaction_1771, (funcp)transaction_1777, (funcp)transaction_1783, (funcp)transaction_1789, (funcp)transaction_1795, (funcp)transaction_1801, (funcp)transaction_1807, (funcp)transaction_1813, (funcp)transaction_1819, (funcp)transaction_1825, (funcp)transaction_1831, (funcp)transaction_1837, (funcp)transaction_1843, (funcp)transaction_1849, (funcp)transaction_1855, (funcp)transaction_1861, (funcp)transaction_1867, (funcp)transaction_1873, (funcp)transaction_1879, (funcp)transaction_1885, (funcp)transaction_1891, (funcp)transaction_1897, (funcp)transaction_1903, (funcp)transaction_1909, (funcp)transaction_1915, (funcp)transaction_1921, (funcp)transaction_1927, (funcp)transaction_1933, (funcp)transaction_1939, (funcp)transaction_1945, (funcp)transaction_1951, (funcp)transaction_1957, (funcp)transaction_1963, (funcp)transaction_1969, (funcp)transaction_1975, (funcp)transaction_1981, (funcp)transaction_1987, (funcp)transaction_1993, (funcp)transaction_1999, (funcp)transaction_2005, (funcp)transaction_2011, (funcp)transaction_2017, (funcp)transaction_2023, (funcp)transaction_2029, (funcp)transaction_2035, (funcp)transaction_2041, (funcp)transaction_2047, (funcp)transaction_2053, (funcp)transaction_2059, (funcp)transaction_2065, (funcp)transaction_2071, (funcp)transaction_2077, (funcp)transaction_2083, (funcp)transaction_2089, (funcp)transaction_2095, (funcp)transaction_2101, (funcp)transaction_2107, (funcp)transaction_2113, (funcp)transaction_2119, (funcp)transaction_2125, (funcp)transaction_2131, (funcp)transaction_2137, (funcp)transaction_2143, (funcp)transaction_2149, (funcp)transaction_2155, (funcp)transaction_2161, (funcp)transaction_2167, (funcp)transaction_2173, (funcp)transaction_2179, (funcp)transaction_2185, (funcp)transaction_2191, (funcp)transaction_2197, (funcp)transaction_2203, (funcp)transaction_2209, (funcp)transaction_2215, (funcp)transaction_2221, (funcp)transaction_2227, (funcp)transaction_2233, (funcp)transaction_2239, (funcp)transaction_2245, (funcp)transaction_2251, (funcp)transaction_2257, (funcp)transaction_2263, (funcp)transaction_2269, (funcp)transaction_2275, (funcp)transaction_2281, (funcp)transaction_2287, (funcp)transaction_2293, (funcp)transaction_2299, (funcp)transaction_2305, (funcp)transaction_2311, (funcp)transaction_2317, (funcp)transaction_2323, (funcp)transaction_2329, (funcp)transaction_2335, (funcp)transaction_2341, (funcp)transaction_2347, (funcp)transaction_2353, (funcp)transaction_2359, (funcp)transaction_2365, (funcp)transaction_2371, (funcp)transaction_2377, (funcp)transaction_2383, (funcp)transaction_2389, (funcp)transaction_2395, (funcp)transaction_2401, (funcp)transaction_2407, (funcp)transaction_2413, (funcp)transaction_2419, (funcp)transaction_2425, (funcp)transaction_2431, (funcp)transaction_2437, (funcp)transaction_2443, (funcp)transaction_2449, (funcp)transaction_2455, (funcp)transaction_2461, (funcp)transaction_2467, (funcp)transaction_2473, (funcp)transaction_2479, (funcp)transaction_2485, (funcp)transaction_2491, (funcp)transaction_2497, (funcp)transaction_2503, (funcp)transaction_2509, (funcp)transaction_2515, (funcp)transaction_2521, (funcp)transaction_2527, (funcp)transaction_2533, (funcp)transaction_2539, (funcp)transaction_2545, (funcp)transaction_2551, (funcp)transaction_2557, (funcp)transaction_2563, (funcp)transaction_2569, (funcp)transaction_2575, (funcp)transaction_2581, (funcp)transaction_2587, (funcp)transaction_2593, (funcp)transaction_2599, (funcp)transaction_2605, (funcp)transaction_2611, (funcp)transaction_2617, (funcp)transaction_2623, (funcp)transaction_2629, (funcp)transaction_2635, (funcp)transaction_2641, (funcp)transaction_2647, (funcp)transaction_2653, (funcp)transaction_2659, (funcp)transaction_2665, (funcp)transaction_2671, (funcp)transaction_2677, (funcp)transaction_2683, (funcp)transaction_2689, (funcp)transaction_2695, (funcp)transaction_2701, (funcp)transaction_2707, (funcp)transaction_2713, (funcp)transaction_2941, (funcp)transaction_2947, (funcp)transaction_2953, (funcp)transaction_2959, (funcp)transaction_2965, (funcp)transaction_2971, (funcp)transaction_2977, (funcp)transaction_2983, (funcp)transaction_2989, (funcp)transaction_2995, (funcp)transaction_3001, (funcp)transaction_3007, (funcp)transaction_3013, (funcp)transaction_3019, (funcp)transaction_3025, (funcp)transaction_3031, (funcp)transaction_3037, (funcp)transaction_3043, (funcp)transaction_3049, (funcp)transaction_3055, (funcp)transaction_3061, (funcp)transaction_3067, (funcp)transaction_3073, (funcp)transaction_3079, (funcp)transaction_3085, (funcp)transaction_3091, (funcp)transaction_3097, (funcp)transaction_3103, (funcp)transaction_3109, (funcp)transaction_3115, (funcp)transaction_3121, (funcp)transaction_3127, (funcp)transaction_3133, (funcp)transaction_3139, (funcp)transaction_3145, (funcp)transaction_3151};
-const int NumRelocateId= 581;
+funcp funcTab[26] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 26;
void relocate(char *dp)
{
- iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 581);
- iki_vhdl_file_variable_register(dp + 701048);
- iki_vhdl_file_variable_register(dp + 701104);
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 26);
+ iki_vhdl_file_variable_register(dp + 8352);
+ iki_vhdl_file_variable_register(dp + 8408);
/*Populate the transaction function pointer field in the whole net structure */
@@ -653,37 +98,10 @@ void sensitize(char *dp)
iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
}
- // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
-
-void wrapper_func_0(char *dp)
-
-{
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 706376, dp + 710584, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 706432, dp + 711536, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 706488, dp + 711088, 0, 15, 0, 15, 16, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707760, dp + 711312, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707816, dp + 710864, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707872, dp + 710752, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707928, dp + 710976, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707984, dp + 711424, 0, 0, 0, 0, 1, 1);
-
- iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 708040, dp + 711200, 0, 0, 0, 0, 1, 1);
-
-}
-
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
- wrapper_func_0(dp);
-
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
index a9f97708d37957c5b7332b318e1a8328f23eb48b..6347e4da7209e8b0908794cf5461bd74caade9b7 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
index 00604124821f0b4f449cc8c1c7ec948c5ccccb20..17139dd998d0c110d59bf397ddd4ce19441d7b32 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
index 654d9d5f31d1016fe47bfe578b23cbeda3351ed2..4c357508e316a43bb74d1191535382ac985d1f2a 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
index fc47b423b3ee70d11db834f8c2a490b5d1c6d05a..e7d39ee0967a061b829edbb12134665e01b30d21 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
index 2409dda78b21425b16455146ef0527996f5de60f..bd92edf6a9e93e243bde2e6a87aadbd83722cbdb 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -1,8 +1,8 @@
{
- crc : 9228793524818688136 ,
+ crc : 2108844090366237881 ,
ccp_crc : 0 ,
- cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl" ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
buildDate : "May 22 2024" ,
buildTime : "18:54:44" ,
linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_firUnit_behav/xsimk\" \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
index 1524aeced9783562feb97bfb93a6f0b8f0a44727..e41d85ec02c26df6006fffd26e0ea0ef6b84a4da 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
index 57a1c98a5f6d4cad2df1f5c52fb8d6f99ce7db99..6dc1deb65a85fafe2dcea36f677983510a180e28 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
index d4da0fede0218ccebe0e39c70c6dcb3fc56f4784..89c53562a84ef2da97b3c2c7cadbb34ec6aa694e 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
index 0ca012898438fc6c69f3840237e449a9f9560a1c..dc7af65bce53bc7666338241f5f176dd87aa1cce 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..146833572c7242c90efaa05b8b9c7bcd436869c6
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=193
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=84
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=209
+OBJECT_NAME_COLUMN_WIDTH=207
+OBJECT_VALUE_COLUMN_WIDTH=512
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
index ad44bec345690ad6cde3be1fb6fabc64bf32c4de..8677a5d44aca90b74b5f3cf27877ed8f0f29f802 100755
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
index b88eca9b4355ca697893784813c9e9e77546c6ee..7a3786f49b033e345f39ad812daf930555e7ab4e 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -1,4 +1,4 @@
-Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 53621
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 52777
Design successfully loaded
-Design Loading Memory Usage: 22124 KB (Peak: 22132 KB)
-Design Loading CPU Usage: 10 ms
+Design Loading Memory Usage: 20176 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 20 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
index 907c385b0ee77ab99b57dd3194b200e3e3216df5..33ed857ef6cff4307b6dca8fc7d63bf04ab39a19 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..0d0d05f41a21c759b71944f94b584775676cb554
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
index fa47448ff3bb8507793265ed5c60c397d55fe926..f79152b91da7ce6012562c0f205cff0741632c1d 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index e381fcad0cacc68635be2904ceaa5322bf4ade7e..da65b36fba39d18c165fc39f6ccac6e382d3b992 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -9,9 +9,10 @@ May 22 2024
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/controlUnit.vhd,1746798045,vhdl,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/debounce.v,1746793138,verilog,,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v,,debounce,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/fir.vhd,1746793138,vhdl,,,,fir,,,,,,,,
-/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd,1746793138,vhdl,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd,1747055023,vhdl,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/i2s_ctl.vhd,1746793138,vhdl,,,,i2s_ctl,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.v,1746793138,verilog,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audioProc.v,,\operativeUnit\,,,,,,,,
+/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd,1747059794,vhdl,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/tb_firUnit.vhd,1746793138,vhdl,,,,tb_firunit,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.v,1746793138,verilog,,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/audio_init.v,,clk_wiz_0,,,,,,,,
/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,1746793138,verilog,,/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/ip/clk_wiz_0/clk_wiz_0.v,,clk_wiz_0_clk_wiz,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
index 3b5d77ebb8fde4e3736c8b046ff863d3d5203e80..8790d43a785fe8a5040740102a8d0b4539f34302 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -1,2 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
index ae30c9941ccb269fb84a7d71d0a00a6788a70f89..cedddd01abc28a201be55e07de76187d9777a09b 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb and b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp b/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp
new file mode 100755
index 0000000000000000000000000000000000000000..7b885e5937b7994e471ca3a2278d33f7e0f95e82
Binary files /dev/null and b/proj/AudioProc.srcs/utils_1/imports/synth_1/audioProc.dcp differ
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
index 999412c00e8c0434089d8fe267525ed42b26a534..e473b05a82b58219516c09deb97cfbcfac7eaf0b 100644
--- a/proj/AudioProc.xpr
+++ b/proj/AudioProc.xpr
@@ -60,7 +60,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="2"/>
+ <Option Name="WTXSimLaunchSim" Val="6"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -158,7 +158,6 @@
<File Path="$PPRDIR/../src/hdl/operativeUnit.v">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -189,6 +188,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_firUnit"/>
@@ -205,6 +205,14 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/audioProc.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@@ -232,11 +240,9 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/audioProc.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
- <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
- </StratHandle>
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design">
<Option Id="FsmExtraction">1</Option>
<Option Id="KeepEquivalentRegisters">1</Option>
@@ -251,11 +257,9 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 12 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
- <Desc>Vivado Implementation Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 00c36d01de18b6a368d7e04c10895b0d5d6e471c..283ab071abc82610b4ae483d753cfb70b65fbab6 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -66,7 +66,7 @@ architecture archi_firUnit of firUnit is
I_incrAddress : in std_logic;
I_initSum : in std_logic;
I_loadSum : in std_logic;
- I_loadOutput : in std_logic;
+ I_loadY : in std_logic;
O_processingDone : out std_logic;
O_filteredSample : out std_logic_vector(15 downto 0));
end component operativeUnit;
@@ -105,7 +105,7 @@ begin
I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum,
I_loadSum => SC_loadSum,
- I_loadOutput => SC_loadOutput,
+ I_loadY => SC_loadOutput,
O_processingDone => SC_processingDone,
O_filteredSample => O_filteredSample);
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 66d962b26fae039789a0610b88e4ca1d36d9da89..549375ead1e92d66ca8a4231de81e8283297d798 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -118,35 +118,50 @@ begin
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));
+
elsif rising_edge(I_clock) then
if I_loadShift = '1' then
-
-
+ for i in 15 downto 1 loop
+ SR_shiftRegister(i) <= SR_shiftRegister(i-1);
+ end loop;
+ SR_shiftRegister(0) <= signed(I_inputSample);
+ end if;
+
end if;
end process shift;
-- Process to describe the counter providing the selection adresses
-- of the multiplexers
- incr_address : process (I_reset) is
+ incr_address : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0;
- elsif _BLANK_
-
+
+ elsif rising_edge(I_clock) then
+
+ if I_initAddress ='1' then
+ SR_readAddress <= 0;
+
+ elsif I_incrAddress = '1' then
+ SR_readAddress <= SR_readAddress + 1;
+
+ end if;
+
end if;
+
end process incr_address;
-- Signal detecting that the next cycle will be the one
-- providing the last product used to compute the convolution
- O_processingDone <= '1' when I_incrAddress = '1' and SR_readAddress ;
+ O_processingDone <= '1' when I_incrAddress = '1' and SR_readAddress = 14 else '0';
-- Signals connected with multiplexers (SIMPLY inferred with table indices)
- SC_multOperand1 <= _BLANK_; -- 16 bits
- SC_multOperand2 <= _BLANK_; -- 16 bits
+ SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 16 bits
+ SC_multOperand2 <= SR_coefRegister(SR_readAddress); -- 16 bits
-- Multiplication of the operands
- SC_MultResult <= _BLANK_; -- 32 bits
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 32 bits
-- Sum of the multiplication result and the accumulated value
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
@@ -154,18 +169,41 @@ begin
-- Register to store the accumulated value if the loadSum is active
-- It also reduces the width of the sum to fit to the input and output
-- signal widths (be careful with truncating/rounding)
- sum_acc : process (I_reset,) is
+ sum_acc : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_sum <= (others => '0');
- elsif _BLANK_
+
+ elsif rising_edge(I_clock) then
+
+ if I_initSum = '1' then
+ SR_sum <= (others => '0');
+
+ elsif I_loadSum = '1' then
+ SR_sum <= SC_addResult;
+
+ end if;
+
end if;
end process sum_acc;
- -- Register to store the final result if the loadOuput is active
- store_result : process (_BLANK_) is
+ -- Register to store the final result if the loadOuput (loadY) is active
+ store_result : process (I_reset, I_clock) is
begin
- _BLANK_
+ if I_reset = '1' then
+ SR_filteredSample <= (others => '0');
+
+ elsif rising_edge(I_clock) then
+
+ if I_loadY = '1' then
+ if SC_addResult(14) = '1' then
+ SR_filteredSample <= SC_addResult(30 downto 15) + 1;
+ else
+ SR_filteredSample <= SC_addResult(30 downto 15);
+ end if;
+ end if;
+
+ end if;
end process store_result;
diff --git a/vivado.jou b/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..4c11dc0b19c555e32e3c07b48fb9d29a0f3b79fe
--- /dev/null
+++ b/vivado.jou
@@ -0,0 +1,27 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 14:07:01 2025
+# Process ID: 73480
+# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang
+# Command line: vivado
+# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/vivado.log
+# Journal file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/vivado.jou
+# Running On :fl-tp-br-520
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4312.167 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :18912 MB
+#-----------------------------------------------------------
+start_gui
+cd tp-filtre-etudiant-m24wang/proj
+cd proj
+source ./create_project.tcl
diff --git a/vivado.log b/vivado.log
new file mode 100644
index 0000000000000000000000000000000000000000..61be6f1c25339ebeb3ccc587815674fcbfdee8c5
--- /dev/null
+++ b/vivado.log
@@ -0,0 +1,60 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May 12 14:07:01 2025
+# Process ID: 73480
+# Current directory: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang
+# Command line: vivado
+# Log file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/vivado.log
+# Journal file: /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/vivado.jou
+# Running On :fl-tp-br-520
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4312.167 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16533 MB
+# Swap memory :4294 MB
+# Total Virtual :20828 MB
+# Available Virtual :18912 MB
+#-----------------------------------------------------------
+start_gui
+cd tp-filtre-etudiant-m24wang/proj
+couldn't change working directory to "tp-filtre-etudiant-m24wang/proj": no such file or directory
+cd proj
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+source ./create_project.tcl
+# if {[info exists ::create_path]} {
+# set dest_dir $::create_path
+# } else {
+# set dest_dir [pwd]
+# }
+# puts "INFO: Creating new project in $dest_dir"
+INFO: Creating new project in /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj
+# set proj_name "AudioProc"
+# set origin_dir ".."
+# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+# set src_dir $origin_dir/src
+# set repo_dir $origin_dir/repo
+# set part_num "xc7a200tsbg484-1"
+# create_project $proj_name $dest_dir
+ERROR: [Common 17-53] User Exception: Project already exists on disk, please use '-force' option to overwrite:
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.xpr
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.runs
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.sim
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.cache
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.hw
+ /homes/m24wang/Bureau/tp-vhdl-mee/UE-EE/tp-filtre-etudiant-m24wang/proj/AudioProc.ip_user_files
+exit
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 14:10:32 2025...