From 84d30184d4946cea82071b32f9697f79adca0c1d Mon Sep 17 00:00:00 2001
From: Oren TORJMAN <o24torjm@fl-tp-br-553.imta.fr>
Date: Mon, 5 May 2025 16:51:41 +0200
Subject: [PATCH] tp-fini
---
src/hdl/module_B.vhd | 4 +--
src/hdl/wave_generator.vhd | 60 +++++++++++++++++++-------------------
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/src/hdl/module_B.vhd b/src/hdl/module_B.vhd
index 8fca774..90bc7d8 100644
--- a/src/hdl/module_B.vhd
+++ b/src/hdl/module_B.vhd
@@ -20,7 +20,7 @@ end module_B;
architecture behavioral of module_B is
signal SR_val_reg : natural range 0 to G_MAX_VAL := 0;
- constant C_middle_val : natural := G_MAX_VAL/2;
+ constant C_middle_val : natural := G_MAX_VAL/2; -- = 12 (round(25/2))
begin
@@ -28,7 +28,7 @@ begin
begin
if rising_edge(I_clk) then
if I_rst = '1' then
- SR_val_reg <= 0;
+ SR_val_reg <= 0; -- REVIENT à 0 à CHAQUE RESET
else
if I_u_d = '1' then
SR_val_reg <= SR_val_reg + 1;
diff --git a/src/hdl/wave_generator.vhd b/src/hdl/wave_generator.vhd
index 310c78f..8254903 100644
--- a/src/hdl/wave_generator.vhd
+++ b/src/hdl/wave_generator.vhd
@@ -64,12 +64,12 @@ begin
G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
)
port map (
- I_clk => ,
- I_rst => ,
- I_u_d => ,
- O_val => ,
- O_last => ,
- O_middle =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_u_d => S_u_d,
+ O_val => S_addr,
+ O_last => S_last,
+ O_middle => S_middle
);
-- Module C
@@ -94,10 +94,10 @@ begin
G_fs => G_fs
)
port map (
- I_clk => ,
- I_rst => ,
- I_addr => ,
- O_triangle =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_addr => S_addr(C_addr_half_w-1 downto 0),
+ O_triangle => S_triangle_out_lut
);
-- Module E
@@ -108,10 +108,10 @@ begin
G_fs => G_fs
)
port map (
- I_clk => ,
- I_rst => ,
- I_addr => ,
- O_saw_tooth =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_addr => S_addr,
+ O_saw_tooth => S_saw_tooth_out_lut
);
S_square <= ((G_N-1) => '0', others => '1');
@@ -119,12 +119,12 @@ begin
-- Module F
F_inst : entity work.module_F
port map (
- I_sel => ,
- I_din0 => ,
- I_din1 => ,
- I_din2 => ,
- I_din3 => ,
- O_dout =>
+ I_sel => I_wave_sel,
+ I_din0 => S_sine_out_lut,
+ I_din1 => S_square,
+ I_din2 => S_saw_tooth_out_lut,
+ I_din3 => S_triangle_out_lut,
+ O_dout => S_wave_sample
);
-- Module G
@@ -133,17 +133,17 @@ begin
G_N => G_N
)
port map (
- I_din => ,
- O_dout =>
+ I_din => S_wave_sample,
+ O_dout => S_opposite_wave_sample
);
-- Module H
H_inst : entity work.module_H
port map (
- I_sel => ,
- I_din0 => ,
- I_din1 => ,
- O_dout =>
+ I_sel => S_sign_sel,
+ I_din0 => S_wave_sample,
+ I_din1 => S_opposite_wave_sample,
+ O_dout => S_wave_value
);
-- Module I
@@ -152,10 +152,10 @@ begin
G_N => G_N
)
port map (
- I_clk => ,
- I_rst => ,
- I_din => ,
- O_dout =>
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_din => S_wave_value,
+ O_dout => O_wav
);
end arch;
--
GitLab