diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 95a2986103c935d9a4784506312acb1c9df2cd18..b2da76c37dfc3b5f0d252507e548fb68d778b4c0 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -19,9 +19,12 @@ La séquence correspond bien à celle attendue. La simulation ne contre-indique
 Après tests, le filtre fonctionne correctement.
 
 ### Question filtre 4 : Combien de processus sont utilisés et de quelles natures sont-ils ?
+Quatre processus sont utilisés, tous sont séquentiels.
 
 
 ### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
-
+La simulation a dans un premier temps fait apparaître un décalage entre les valeurs renvoyées par notre description et les valeurs attendues. Une fois ce problème réglé (problème d'arrondi de la valeur finale), nous avons pu valider notre description.
 
 ### Question filtre 6 : Validez-vous la conception de l’unité opérative ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ?
+Nous validons la conception de l'unité opérative.
+
diff --git a/docs/img/FSM.png b/docs/img/FSM.png
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..f6c9166c587117c9eb1f545e9da6545c5b54aa71 100644
Binary files a/docs/img/FSM.png and b/docs/img/FSM.png differ
diff --git a/proj/AudioProc.cache/sim/ssm.db b/proj/AudioProc.cache/sim/ssm.db
index 8d93642693c11d37914186d13710d58b8482049b..c56a9293fce5d8b687cb8f029bebafdb29ac8090 100644
--- a/proj/AudioProc.cache/sim/ssm.db
+++ b/proj/AudioProc.cache/sim/ssm.db
@@ -2,7 +2,7 @@
 #                            DONOT REMOVE THIS FILE
 # Unified simulation database file for selected simulation model for IP
 #
-# File: ssm.db (Fri May  9 15:22:33 2025)
+# File: ssm.db (Mon May 12 15:43:41 2025)
 #
 # This file is generated by the unified simulation automation and contains the
 # selected simulation model information for the IP/BD instances.
diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
index 9b342093142bd1b298b4af63bdebdead3a3ef56e..6888edec1ac73923cacb7d6dea38f6663dae769b 100644
--- a/proj/AudioProc.cache/wt/project.wpc
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
 eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
index d43701ad4b145ba76aaad0ab677e1a3df26ea933..971bdabc04d44f9e3fe121a3cfa62a1f237d7775 100644
--- a/proj/AudioProc.cache/wt/synthesis.wdf
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -46,7 +46,7 @@ version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333973:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323731322e3535394d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313031312e3132394d42:00:00
-eof:467829327
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343273:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323735322e3333324d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313035302e3933344d42:00:00
+eof:3636536115
diff --git a/proj/AudioProc.cache/wt/webtalk_pa.xml b/proj/AudioProc.cache/wt/webtalk_pa.xml
index df3d6f91536c0051f19108f5b6d324020332ffcb..2e4fa242517ad1943ce7f992b06afbe83a75efe4 100644
--- a/proj/AudioProc.cache/wt/webtalk_pa.xml
+++ b/proj/AudioProc.cache/wt/webtalk_pa.xml
@@ -3,9 +3,9 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri May  9 15:47:07 2025">
+<application name="pa" timeStamp="Mon May 12 16:19:26 2025">
 <section name="Project Information" visible="false">
-<property name="ProjectID" value="233f84b594fa4fc19d7847b04f8aa38c" type="ProjectID"/>
+<property name="ProjectID" value="c1a922aa6dbe4e1ea1e73efc3c211b76" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
 </section>
 <section name="PlanAhead Usage" visible="true">
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
index 51d5206f7011f2f0764fb661278617e58456141a..50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af 100644
--- a/proj/AudioProc.cache/wt/xsim.wdf
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -1,4 +1,4 @@
 version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:2427094519
+eof:241934075
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_1.xml b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
index 0981fda01cbf38386212c0ee5f2e9468a28fb6d4..7b1ba1dd94d630fc83057b3b9a4396c3948041dd 100644
--- a/proj/AudioProc.runs/.jobs/vrs_config_1.xml
+++ b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
@@ -1,6 +1,9 @@
 <?xml version="1.0"?>
 <Runs Version="1" Minor="0">
 	<Run Id="synth_1" LaunchDir="/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
 	<Parameters>
 		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
 		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_2.xml b/proj/AudioProc.runs/.jobs/vrs_config_2.xml
deleted file mode 100644
index a28b6f8aecef9455386247e20612373be5151d07..0000000000000000000000000000000000000000
--- a/proj/AudioProc.runs/.jobs/vrs_config_2.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0"?>
-<Runs Version="1" Minor="0">
-	<Run Id="impl_1" LaunchDir="/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
-	<Parameters>
-		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
-		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
-		<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
-		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
-	</Parameters>
-	<ProductInfo Name="vivado"/>
-</Runs>
-
diff --git a/proj/AudioProc.runs/impl_1/.init_design.begin.rst b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
index 498437dc8362bc83e8b2efd81cae50f02158f589..569b4bc2bd91af6372af7e7db030e2a0fbc2e6a7 100644
--- a/proj/AudioProc.runs/impl_1/.init_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="2029775">
+    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="78259">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
index 498437dc8362bc83e8b2efd81cae50f02158f589..569b4bc2bd91af6372af7e7db030e2a0fbc2e6a7 100644
--- a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="2029775">
+    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="78259">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.place_design.begin.rst b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
index 498437dc8362bc83e8b2efd81cae50f02158f589..569b4bc2bd91af6372af7e7db030e2a0fbc2e6a7 100644
--- a/proj/AudioProc.runs/impl_1/.place_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="2029775">
+    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="78259">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.route_design.begin.rst b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
index 498437dc8362bc83e8b2efd81cae50f02158f589..569b4bc2bd91af6372af7e7db030e2a0fbc2e6a7 100644
--- a/proj/AudioProc.runs/impl_1/.route_design.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="2029775">
+    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="78259">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.vivado.begin.rst b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
index 677fa23e53c4a4288c54f7a81596949aeaa86c33..2f6a5dc87a73b7ce25573fee1e827178e71823db 100644
--- a/proj/AudioProc.runs/impl_1/.vivado.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command="vivado" Owner="g24demon" Host="fl-tp-br-551" Pid="2029704" HostCore="4" HostMemory="16296788">
+    <Process Command="vivado" Owner="g24demon" Host="fl-tp-br-551" Pid="78188" HostCore="4" HostMemory="16296780">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
index 498437dc8362bc83e8b2efd81cae50f02158f589..569b4bc2bd91af6372af7e7db030e2a0fbc2e6a7 100644
--- a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
+++ b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="2029775">
+    <Process Command=".planAhead." Owner="g24demon" Host="" Pid="78259">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bin b/proj/AudioProc.runs/impl_1/audioProc.bin
index c82b3e4348f6991d14acfba79b9a58b1355d38ea..51a5c988dfec781a6f3c35dec757ebff8b2b5cd8 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc.bin and b/proj/AudioProc.runs/impl_1/audioProc.bin differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bit b/proj/AudioProc.runs/impl_1/audioProc.bit
index 3f057edb3d157acde7fadd7fbac5d086b4ec8051..9ed11b03628975eefa9fdd416c7e1fe600cbc74d 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc.bit and b/proj/AudioProc.runs/impl_1/audioProc.bit differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.tcl b/proj/AudioProc.runs/impl_1/audioProc.tcl
index aa70fdef1cc3a37641dd520f2f640a93a4121c5b..3fb7eed6f1fdd03257efa2f297dee2cd69deca9b 100644
--- a/proj/AudioProc.runs/impl_1/audioProc.tcl
+++ b/proj/AudioProc.runs/impl_1/audioProc.tcl
@@ -97,6 +97,7 @@ proc step_failed { step } {
 OPTRACE "impl_1" END { }
 }
 
+set_msg_config -id {Common 17-41} -limit 10000000
 
 OPTRACE "impl_1" START { ROLLUP_1 }
 OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
diff --git a/proj/AudioProc.runs/impl_1/audioProc.vdi b/proj/AudioProc.runs/impl_1/audioProc.vdi
index e6c81f8d81ebf34a608c1ce231b1de34f5a1d27a..5b78671ac44a64fdd311c7bdf3d1fa3467343c0c 100644
--- a/proj/AudioProc.runs/impl_1/audioProc.vdi
+++ b/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May  9 15:47:10 2025
-# Process ID: 2029775
+# Start of session at: Mon May 12 16:21:34 2025
+# Process ID: 78259
 # Current directory: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1
 # Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
 # Log file: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -13,16 +13,16 @@
 # Platform          :Ubuntu
 # Operating System  :Ubuntu 24.04.2 LTS
 # Processor Detail  :Intel(R) Xeon(R) CPU E5-1607 v4 @ 3.10GHz
-# CPU Frequency     :3092.852 MHz
+# CPU Frequency     :3092.499 MHz
 # CPU Physical cores:4
 # CPU Logical cores :4
 # Host memory       :16687 MB
 # Swap memory       :4294 MB
 # Total Virtual     :20982 MB
-# Available Virtual :9024 MB
+# Available Virtual :12515 MB
 #-----------------------------------------------------------
 source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1680.555 ; gain = 325.840 ; free physical = 1454 ; free virtual = 7989
+create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 1680.617 ; gain = 327.840 ; free physical = 1556 ; free virtual = 11335
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/repo'; Can't find the specified path.
 If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -33,7 +33,7 @@ Design is defaulting to constrset: constrs_1
 INFO: [Device 21-403] Loading part xc7a200tsbg484-1
 INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
 INFO: [Project 1-454] Reading design checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2098.805 ; gain = 0.000 ; free physical = 1037 ; free virtual = 7573
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2097.469 ; gain = 0.000 ; free physical = 1140 ; free virtual = 10919
 INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-479] Netlist was created with Vivado 2015.3
@@ -43,20 +43,20 @@ Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudian
 Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
 INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
 INFO: [Timing 38-2] Deriving generated clocks [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
-get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2746.297 ; gain = 544.930 ; free physical = 463 ; free virtual = 6998
+get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2743.961 ; gain = 551.961 ; free physical = 573 ; free virtual = 10351
 Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
 Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/constraints/NexysVideo_Master.xdc]
 Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/constraints/NexysVideo_Master.xdc]
 INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.dcp'
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2746.297 ; gain = 0.000 ; free physical = 460 ; free virtual = 6996
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.961 ; gain = 0.000 ; free physical = 572 ; free virtual = 10350
 INFO: [Project 1-111] Unisim Transformation Summary:
   A total of 2 instances were transformed.
   IOBUF => IOBUF (IBUF, OBUFT): 2 instances
 
 14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 link_design completed successfully
-link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 2746.297 ; gain = 1050.898 ; free physical = 460 ; free virtual = 6996
+link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 2743.961 ; gain = 1048.500 ; free physical = 572 ; free virtual = 10350
 Command: opt_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
@@ -67,113 +67,112 @@ INFO: [DRC 23-27] Running DRC with 4 threads
 INFO: [Project 1-461] DRC finished with 0 Errors
 INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2755.203 ; gain = 8.906 ; free physical = 458 ; free virtual = 6993
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2755.836 ; gain = 11.875 ; free physical = 544 ; free virtual = 10322
 
 Starting Cache Timing Information Task
 INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 27a691c2e
+Ending Cache Timing Information Task | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2766.109 ; gain = 10.906 ; free physical = 458 ; free virtual = 6993
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2764.742 ; gain = 8.906 ; free physical = 544 ; free virtual = 10322
 
 Starting Logic Optimization Task
 
 Phase 1 Initialization
 
 Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 27a691c2e
+Phase 1.1 Core Generation And Design Setup | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 27a691c2e
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 1 Initialization | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Phase 1 Initialization | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 2 Timer Update And Timing Data Collection
 
 Phase 2.1 Timer Update
-Phase 2.1 Timer Update | Checksum: 27a691c2e
+Phase 2.1 Timer Update | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 2.2 Timing Data Collection
-Phase 2.2 Timing Data Collection | Checksum: 27a691c2e
+Phase 2.2 Timing Data Collection | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 2 Timer Update And Timing Data Collection | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 3 Retarget
 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 27a691c2e
+Phase 3 Retarget | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Retarget | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Retarget | Checksum: 2b42ff704
 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
 INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 
 Phase 4 Constant propagation
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 27a691c2e
+Phase 4 Constant propagation | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Constant propagation | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Constant propagation | Checksum: 2b42ff704
 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
 
 Phase 5 Sweep
-Phase 5 Sweep | Checksum: 2f081e065
+Phase 5 Sweep | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Sweep | Checksum: 2f081e065
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Sweep | Checksum: 2f3b7e24b
 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
 
 Phase 6 BUFG optimization
-INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells
-Phase 6 BUFG optimization | Checksum: 254f45935
+Phase 6 BUFG optimization | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-BUFG optimization | Checksum: 254f45935
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells.
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+BUFG optimization | Checksum: 2f3b7e24b
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
 
 Phase 7 Shift Register Optimization
 INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 254f45935
+Phase 7 Shift Register Optimization | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Shift Register Optimization | Checksum: 254f45935
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Shift Register Optimization | Checksum: 2f3b7e24b
 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
 
 Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 27a0b14a7
+Phase 8 Post Processing Netlist | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Post Processing Netlist | Checksum: 27a0b14a7
+Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Post Processing Netlist | Checksum: 2f3b7e24b
 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
 
 Phase 9 Finalization
 
 Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2105fe3c5
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 9.2 Verifying Netlist Connectivity
 
 Starting Connectivity Check Task
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 2105fe3c5
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 9 Finalization | Checksum: 2105fe3c5
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Phase 9 Finalization | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 Opt_design Change Summary
 =========================
 
@@ -184,34 +183,34 @@ Opt_design Change Summary
 |  Retarget                     |               0  |               0  |                                              1  |
 |  Constant propagation         |               0  |               0  |                                              0  |
 |  Sweep                        |               0  |               1  |                                              0  |
-|  BUFG optimization            |               0  |               2  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
 |  Shift Register Optimization  |               0  |               0  |                                              0  |
 |  Post Processing Netlist      |               0  |               0  |                                              0  |
 -------------------------------------------------------------------------------------------------------------------------
 
 
-Ending Logic Optimization Task | Checksum: 2105fe3c5
+Ending Logic Optimization Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Starting Power Optimization Task
 INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 2105fe3c5
+Ending Power Optimization Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 2105fe3c5
+Ending Final Cleanup Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Ending Netlist Obfuscation Task | Checksum: 2105fe3c5
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
+Ending Netlist Obfuscation Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 INFO: [Common 17-83] Releasing license: Implementation
-34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 opt_design completed successfully
 INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
 Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
@@ -220,16 +219,16 @@ INFO: [DRC 23-27] Running DRC with 4 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
 report_drc completed successfully
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 275 ; free virtual = 6671
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 275 ; free virtual = 6671
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 275 ; free virtual = 6671
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6667
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6667
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6668
-Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6668
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 220 ; free virtual = 9999
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 220 ; free virtual = 9999
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
 Command: place_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -249,57 +248,57 @@ Starting Placer Task
 Phase 1 Placer Initialization
 
 Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 256 ; free virtual = 6653
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1971e65b5
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 228 ; free virtual = 10007
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 27ecc6cee
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 256 ; free virtual = 6653
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 256 ; free virtual = 6653
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 228 ; free virtual = 10006
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 228 ; free virtual = 10006
 
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
 INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d834e537
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 167eef5db
 
-Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 255 ; free virtual = 6652
+Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 24479b66e
+Phase 1.3 Build Placer Netlist Model | Checksum: 243fe7c31
 
-Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.74 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 254 ; free virtual = 6650
+Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.65 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 24479b66e
+Phase 1.4 Constrain Clocks/Macros | Checksum: 243fe7c31
 
-Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.75 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 254 ; free virtual = 6650
-Phase 1 Placer Initialization | Checksum: 24479b66e
+Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.66 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
+Phase 1 Placer Initialization | Checksum: 243fe7c31
 
-Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.76 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 254 ; free virtual = 6650
+Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 2 Global Placement
 
 Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1f0769a16
+Phase 2.1 Floorplanning | Checksum: 235583514
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.91 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 253 ; free virtual = 6649
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2d5cde647
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2509677d8
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 253 ; free virtual = 6649
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.83 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2d5cde647
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 2509677d8
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 253 ; free virtual = 6649
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.83 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Phase 2.4 Global Placement Core
 
 Phase 2.4.1 UpdateTiming Before Physical Synthesis
-Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 24e71af8c
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1ef3d9d04
 
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 349 ; free virtual = 6649
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3116.480 ; gain = 1.848 ; free physical = 207 ; free virtual = 9985
 
 Phase 2.4.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 96 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 93 LUT instances to create LUTNM shape
 INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
 INFO: [Physopt 32-1138] End 1 Pass. Optimized 44 nets or LUTs. Breaked 0 LUT, combined 44 existing LUTs and moved 0 existing LUT
 INFO: [Physopt 32-65] No nets found for high-fanout optimization.
@@ -312,7 +311,7 @@ INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was
 INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
 INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3117.781 ; gain = 0.000 ; free physical = 350 ; free virtual = 6650
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3117.383 ; gain = 0.000 ; free physical = 205 ; free virtual = 9984
 
 Summary of Physical Synthesis Optimizations
 ============================================
@@ -334,55 +333,55 @@ Summary of Physical Synthesis Optimizations
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 
 
-Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2d955f418
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1d76f29f6
 
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 350 ; free virtual = 6650
-Phase 2.4 Global Placement Core | Checksum: 24d73e065
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 205 ; free virtual = 9984
+Phase 2.4 Global Placement Core | Checksum: 1ce08bc3f
 
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 341 ; free virtual = 6641
-Phase 2 Global Placement | Checksum: 24d73e065
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 209 ; free virtual = 9987
+Phase 2 Global Placement | Checksum: 1ce08bc3f
 
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 341 ; free virtual = 6641
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 209 ; free virtual = 9987
 
 Phase 3 Detail Placement
 
 Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 23d657603
+Phase 3.1 Commit Multi Column Macros | Checksum: 118a6c22e
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 340 ; free virtual = 6641
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 209 ; free virtual = 9987
 
 Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22513e1c8
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 146facb8f
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 342 ; free virtual = 6642
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 208 ; free virtual = 9987
 
 Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 1ea1af04a
+Phase 3.3 Area Swap Optimization | Checksum: 1b29482ac
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 342 ; free virtual = 6642
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 208 ; free virtual = 9987
 
 Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 178715a17
+Phase 3.4 Pipeline Register Optimization | Checksum: 1f0d117d7
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 341 ; free virtual = 6642
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 208 ; free virtual = 9987
 
 Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 2d4f2065c
+Phase 3.5 Small Shape Detail Placement | Checksum: 2526c07bc
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9978
 
 Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1f22d608d
+Phase 3.6 Re-assign LUT pins | Checksum: 2624e5e42
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9979
 
 Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 146f8e4d1
+Phase 3.7 Pipeline Register Optimization | Checksum: 1a4d57885
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
-Phase 3 Detail Placement | Checksum: 146f8e4d1
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9979
+Phase 3 Detail Placement | Checksum: 1a4d57885
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9979
 
 Phase 4 Post Placement Optimization and Clean-Up
 
@@ -390,7 +389,7 @@ Phase 4.1 Post Commit Optimization
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 
 Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 236af2095
+Post Placement Optimization Initialization | Checksum: 195809db6
 
 Phase 4.1.1.1 BUFG Insertion
 
@@ -398,33 +397,33 @@ Starting Physical Synthesis Task
 
 Phase 1 Physical Synthesis Initialization
 INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.794 | TNS=0.000 |
-Phase 1 Physical Synthesis Initialization | Checksum: 2004c68b1
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.560 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 1178deb16
 
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 199 ; free virtual = 9978
 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1bfcb37d3
+Ending Physical Synthesis Task | Checksum: 236d54c7b
 
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 339 ; free virtual = 6640
-Phase 4.1.1.1 BUFG Insertion | Checksum: 236af2095
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 199 ; free virtual = 9978
+Phase 4.1.1.1 BUFG Insertion | Checksum: 195809db6
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.794. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 242e1e100
+INFO: [Place 30-746] Post Placement Timing Summary WNS=1.560. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Phase 4.1 Post Commit Optimization | Checksum: 242e1e100
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Phase 4.1 Post Commit Optimization | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 242e1e100
+Phase 4.2 Post Placement Cleanup | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.3 Placer Reporting
 
@@ -443,44 +442,44 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
 |       West|                1x1|                1x1|
 |___________|___________________|___________________|
 
-Phase 4.3.1 Print Estimated Congestion | Checksum: 242e1e100
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Phase 4.3 Placer Reporting | Checksum: 242e1e100
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Phase 4.3 Placer Reporting | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 339 ; free virtual = 6639
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 199 ; free virtual = 9978
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c155315a
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 31419600f
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Ending Placer Task | Checksum: c4fd0a1d
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Ending Placer Task | Checksum: 24f565a1d
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-69 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 place_design completed successfully
-place_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
 Running report generation with 3 threads.
 INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 322 ; free virtual = 6623
+report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 179 ; free virtual = 9958
 INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
 INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 321 ; free virtual = 6622
+report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 183 ; free virtual = 9962
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 322 ; free virtual = 6622
-Wrote PlaceDB: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 318 ; free virtual = 6620
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6617
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 183 ; free virtual = 9962
+Wrote PlaceDB: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 183 ; free virtual = 9963
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6617
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6618
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6618
-Write Physdb Complete: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6618
+Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9963
+Write Physdb Complete: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
 Command: route_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -495,122 +494,121 @@ Starting Routing Task
 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
 
 Phase 1 Build RT Design
-Checksum: PlaceDB: 17894a90 ConstDB: 0 ShapeSum: 1558d429 RouteDB: 981aeb64
-Post Restoration Checksum: NetGraph: a8773583 | NumContArr: fe331ce0 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 32bfc479d
+Checksum: PlaceDB: ba349357 ConstDB: 0 ShapeSum: fd06db62 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: f76f7af6 | NumContArr: ea613dbe | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 36722adee
 
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 3339.742 ; gain = 178.105 ; free physical = 245 ; free virtual = 6437
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:47 . Memory (MB): peak = 3340.250 ; gain = 177.043 ; free physical = 176 ; free virtual = 9757
 
 Phase 2 Router Initialization
 
 Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 32bfc479d
+Phase 2.1 Fix Topology Constraints | Checksum: 36722adee
 
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 3339.742 ; gain = 178.105 ; free physical = 295 ; free virtual = 6436
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:47 . Memory (MB): peak = 3340.250 ; gain = 177.043 ; free physical = 176 ; free virtual = 9757
 
 Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 32bfc479d
+Phase 2.2 Pre Route Cleanup | Checksum: 36722adee
 
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 3339.742 ; gain = 178.105 ; free physical = 295 ; free virtual = 6436
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:47 . Memory (MB): peak = 3340.250 ; gain = 177.043 ; free physical = 176 ; free virtual = 9757
  Number of Nodes with overlaps = 0
 
 Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 2d1d4910a
+Phase 2.3 Update Timing | Checksum: 29d3a4195
 
-Time (s): cpu = 00:00:57 ; elapsed = 00:00:51 . Memory (MB): peak = 3388.719 ; gain = 227.082 ; free physical = 283 ; free virtual = 6388
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.803  | TNS=0.000  | WHS=-0.144 | THS=-22.944|
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:48 . Memory (MB): peak = 3388.227 ; gain = 225.020 ; free physical = 220 ; free virtual = 9702
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.562  | TNS=0.000  | WHS=-0.148 | THS=-26.208|
 
 
 Router Utilization Summary
-  Global Vertical Routing Utilization    = 0.000182205 %
-  Global Horizontal Routing Utilization  = 0.000165235 %
+  Global Vertical Routing Utilization    = 0.000141715 %
+  Global Horizontal Routing Utilization  = 6.60939e-05 %
   Routable Net Status*
   *Does not include unroutable nets such as driverless and loadless.
   Run report_route_status for detailed report.
-  Number of Failed Nets               = 1211
+  Number of Failed Nets               = 1207
     (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 1201
+  Number of Unrouted Nets             = 1197
   Number of Partially Routed Nets     = 10
-  Number of Node Overlaps             = 11
+  Number of Node Overlaps             = 10
 
-Phase 2 Router Initialization | Checksum: 269f51fe2
+Phase 2 Router Initialization | Checksum: 30251a708
 
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:51 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
 
 Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 269f51fe2
+Phase 3 Global Routing | Checksum: 30251a708
 
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:51 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
 
 Phase 4 Initial Routing
 
 Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 2c245566f
+Phase 4.1 Initial Net Routing Pass | Checksum: 266713b99
 
-Time (s): cpu = 00:00:59 ; elapsed = 00:00:52 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
-Phase 4 Initial Routing | Checksum: 2c245566f
+Time (s): cpu = 00:00:59 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
+Phase 4 Initial Routing | Checksum: 266713b99
 
-Time (s): cpu = 00:00:59 ; elapsed = 00:00:52 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
+Time (s): cpu = 00:00:59 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
 
 Phase 5 Rip-up And Reroute
 
 Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 238
- Number of Nodes with overlaps = 126
- Number of Nodes with overlaps = 68
- Number of Nodes with overlaps = 32
- Number of Nodes with overlaps = 10
- Number of Nodes with overlaps = 6
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 156
+ Number of Nodes with overlaps = 46
+ Number of Nodes with overlaps = 22
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 4
+ Number of Nodes with overlaps = 1
  Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.534  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.473  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 
-Phase 5.1 Global Iteration 0 | Checksum: 2abe36016
+Phase 5.1 Global Iteration 0 | Checksum: 2bbc7cb6a
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6365
-Phase 5 Rip-up And Reroute | Checksum: 2abe36016
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Phase 5 Rip-up And Reroute | Checksum: 2bbc7cb6a
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 6 Delay and Skew Optimization
 
 Phase 6.1 Delay CleanUp
 
 Phase 6.1.1 Update Timing
-Phase 6.1.1 Update Timing | Checksum: 2efa28e2c
+Phase 6.1.1 Update Timing | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.567  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 
-Phase 6.1 Delay CleanUp | Checksum: 2efa28e2c
+Phase 6.1 Delay CleanUp | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 2efa28e2c
+Phase 6.2 Clock Skew Optimization | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6365
-Phase 6 Delay and Skew Optimization | Checksum: 2efa28e2c
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Phase 6 Delay and Skew Optimization | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 7 Post Hold Fix
 
 Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613  | TNS=0.000  | WHS=0.107  | THS=0.000  |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.567  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 
-Phase 7.1 Hold Fix Iter | Checksum: 2486ccefa
+Phase 7.1 Hold Fix Iter | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
-Phase 7 Post Hold Fix | Checksum: 2486ccefa
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Phase 7 Post Hold Fix | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 8 Route finalize
 
 Router Utilization Summary
-  Global Vertical Routing Utilization    = 0.0942403 %
-  Global Horizontal Routing Utilization  = 0.118209 %
+  Global Vertical Routing Utilization    = 0.0912643 %
+  Global Horizontal Routing Utilization  = 0.112888 %
   Routable Net Status*
   *Does not include unroutable nets such as driverless and loadless.
   Run report_route_status for detailed report.
@@ -620,50 +618,50 @@ Router Utilization Summary
   Number of Partially Routed Nets     = 0
   Number of Node Overlaps             = 0
 
-Phase 8 Route finalize | Checksum: 2486ccefa
+Phase 8 Route finalize | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 262 ; free virtual = 6366
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 9 Verifying routed nets
 
  Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2486ccefa
+Phase 9 Verifying routed nets | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 16786fc76
+Phase 10 Depositing Routes | Checksum: 26991fca5
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 16786fc76
+Phase 11 Post Process Routing | Checksum: 26991fca5
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.613  | TNS=0.000  | WHS=0.107  | THS=0.000  |
+INFO: [Route 35-57] Estimated Timing Summary | WNS=1.567  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 
 INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 16786fc76
+Phase 12 Post Router Timing | Checksum: 26991fca5
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
-Total Elapsed time in route_design: 55.27 secs
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Total Elapsed time in route_design: 50.86 secs
 
 Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: d2e3295b
+Phase 13 Post-Route Event Processing | Checksum: 1cf931110
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: d2e3295b
+Ending Routing Task | Checksum: 1cf931110
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Routing Is Done.
 INFO: [Common 17-83] Releasing license: Implementation
-88 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+87 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 route_design completed successfully
-route_design: Time (s): cpu = 00:01:04 ; elapsed = 00:00:56 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 259 ; free virtual = 6364
+route_design: Time (s): cpu = 00:01:03 ; elapsed = 00:00:52 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
 Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -693,23 +691,22 @@ Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summa
 Running Vector-less Activity Propagation...
 
 Finished Running Vector-less Activity Propagation
-108 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+107 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 report_power completed successfully
 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
 WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
 WARNING: [Device 21-2174] Failed to initialize Virtual grid.
-generate_parallel_reports: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3452.137 ; gain = 56.027 ; free physical = 351 ; free virtual = 6361
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 351 ; free virtual = 6361
-Wrote PlaceDB: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 352 ; free virtual = 6362
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 351 ; free virtual = 6361
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 206 ; free virtual = 9689
+Wrote PlaceDB: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 205 ; free virtual = 9690
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 205 ; free virtual = 9690
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 350 ; free virtual = 6361
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 350 ; free virtual = 6361
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 349 ; free virtual = 6361
-Write Physdb Complete: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.42 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 349 ; free virtual = 6361
+Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 205 ; free virtual = 9690
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 204 ; free virtual = 9689
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 204 ; free virtual = 9689
+Write Physdb Complete: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 204 ; free virtual = 9689
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
 Command: write_bitstream -force audioProc.bit -bin_file
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -736,8 +733,8 @@ WARNING: [DRC DPOP-1] PREG Output pipelining: DSP leftFir/firUnit_1/operativeUni
 WARNING: [DRC DPOP-1] PREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult output rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
 WARNING: [DRC DPOP-2] MREG Output pipelining: DSP leftFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
 WARNING: [DRC DPOP-2] MREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
-WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
 INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
 INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
 INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
@@ -751,7 +748,7 @@ Writing bitstream ./audioProc.bit...
 Writing bitstream ./audioProc.bin...
 INFO: [Vivado 12-1842] Bitgen Completed Successfully.
 INFO: [Common 17-83] Releasing license: Implementation
-119 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
+118 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
 write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 3773.680 ; gain = 321.543 ; free physical = 301 ; free virtual = 5990
-INFO: [Common 17-206] Exiting Vivado at Fri May  9 15:50:23 2025...
+write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 3771.219 ; gain = 319.574 ; free physical = 153 ; free virtual = 9353
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:24:32 2025...
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
index ff83f932e2fd1590b0e38e09f874d010618ca583..24dd815f5137c2302a383a3dbe28572aac2cad73 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ------------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:49:59 2025
+| Date         : Mon May 12 16:24:10 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
 | Design       : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx
index ed0d87de1debaa7953e3a3271d96dec69a949928..0e9f31756033962b2dbe06cae7730e7f4303dd9f 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
index 88f78458ba49d484e447461b9b1228189918b015..99a545d4c4dc7fb9d0f270e159cb0e05f7a0e083 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:50:01 2025
+| Date         : Mon May 12 16:24:11 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
 | Design       : audioProc
@@ -23,7 +23,8 @@ Table of Contents
 7. Device Cell Placement Summary for Global Clock g1
 8. Device Cell Placement Summary for Global Clock g2
 9. Device Cell Placement Summary for Global Clock g3
-10. Clock Region Cell Placement per Global Clock: Region X1Y2
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+11. Clock Region Cell Placement per Global Clock: Region X1Y2
 
 1. Clock Primitive Utilization
 ------------------------------
@@ -47,7 +48,7 @@ Table of Contents
 +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
 | Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock              | Driver Pin               | Net                               |
 +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
-| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |                 1 |         773 |               0 |       10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1               |
+| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |                 2 |         773 |               0 |       10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1               |
 | g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y2 | n/a          |                 1 |         120 |               0 |       20.000 | clk_out4_clk_wiz_0 | clk_1/inst/clkout4_buf/O | clk_1/inst/clk_out4               |
 | g2        | src2      | BUFG/O          | None       | BUFGCTRL_X0Y3 | n/a          |                 1 |           1 |               0 |       10.000 | clkfbout_clk_wiz_0 | clk_1/inst/clkf_buf/O    | clk_1/inst/clkfbout_buf_clk_wiz_0 |
 | g3        | src3      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |                 1 |           0 |               1 |       83.333 | clk_out3_clk_wiz_0 | clk_1/inst/clkout3_buf/O | clk_1/inst/clk_out3               |
@@ -82,9 +83,9 @@ Table of Contents
 | X0Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  2700 |    0 |   800 |    0 |    60 |    0 |    30 |    0 |    60 |
 | X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  2500 |    0 |   800 |    0 |    40 |    0 |    20 |    0 |    40 |
 | X0Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4200 |    0 |  1400 |    0 |   100 |    0 |    50 |    0 |   100 |
-| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
+| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   56 |  4000 |   22 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
 | X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3600 |    0 |  1400 |    0 |   100 |    0 |    50 |    0 |   100 |
-| X1Y2              |    4 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  893 |  4000 |  343 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
+| X1Y2              |    4 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  837 |  4000 |  310 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
 | X0Y3              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3600 |    0 |  1400 |    0 |   100 |    0 |    50 |    0 |   100 |
 | X1Y3              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
 | X0Y4              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     1 |    0 |    50 |    0 |    50 |    0 |  2550 |    0 |   750 |    0 |    50 |    0 |    25 |    0 |    60 |
@@ -127,8 +128,8 @@ All Modules
 +----+----+------+-----------------------+
 | Y4 |  0 |    0 |                     - |
 | Y3 |  0 |    0 |                     - |
-| Y2 |  0 |  773 |                     0 |
-| Y1 |  0 |    0 |                     - |
+| Y2 |  0 |  717 |                     0 |
+| Y1 |  0 |   56 |                     0 |
 | Y0 |  0 |    0 |                     - |
 +----+----+------+-----------------------+
 
@@ -208,13 +209,26 @@ All Modules
 +----+----+----+-----------------------+
 
 
-10. Clock Region Cell Placement per Global Clock: Region X1Y2
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------------+
+| g0        | n/a   | BUFG/O          | None       |          56 |               0 | 56 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_1/inst/clk_out1 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+11. Clock Region Cell Placement per Global Clock: Region X1Y2
 -------------------------------------------------------------
 
 +-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
 | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                               |
 +-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
-| g0        | n/a   | BUFG/O          | None       |         773 |               0 | 773 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_1/inst/clk_out1               |
+| g0        | n/a   | BUFG/O          | None       |         717 |               0 | 717 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_1/inst/clk_out1               |
 | g1        | n/a   | BUFG/O          | None       |         120 |               0 | 120 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_1/inst/clk_out4               |
 | g2        | n/a   | BUFG/O          | None       |           1 |               0 |   0 |           0 |    0 |   0 |  0 |    1 |   0 |       0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
 | g3        | n/a   | BUFG/O          | None       |           0 |               1 |   0 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_1/inst/clk_out3               |
@@ -248,5 +262,5 @@ resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] -add {CLOCKREGION_X1Y2:C
 #startgroup
 create_pblock {CLKAG_clk_1/inst/clk_out1}
 add_cells_to_pblock [get_pblocks  {CLKAG_clk_1/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out1"}]]]
-resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
 #endgroup
diff --git a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
index a70fc260db815857cb6f9aa1533abecbb2f1b2a0..c89c087886950409d989ee0b659708f9ad1ea630 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:48:57 2025
+| Date         : Mon May 12 16:23:13 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
 | Design       : audioProc
@@ -58,53 +58,53 @@ Table of Contents
 +--------------+-----------------------+------------------------+-----------------+--------------+
 | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
 +--------------+-----------------------+------------------------+-----------------+--------------+
-| No           | No                    | No                     |              34 |           19 |
-| No           | No                    | Yes                    |              10 |            2 |
+| No           | No                    | No                     |              34 |           17 |
+| No           | No                    | Yes                    |              10 |            3 |
 | No           | Yes                   | No                     |              44 |           14 |
-| Yes          | No                    | No                     |              67 |           23 |
-| Yes          | No                    | Yes                    |             624 |          156 |
-| Yes          | Yes                   | No                     |             124 |           36 |
+| Yes          | No                    | No                     |              67 |           25 |
+| Yes          | No                    | Yes                    |             624 |          155 |
+| Yes          | Yes                   | No                     |             124 |           33 |
 +--------------+-----------------------+------------------------+-----------------+--------------+
 
 
 4. Detailed Control Set Information
 -----------------------------------
 
-+------------------------------------------------+--------------------------------------------------------------+---------------------------------------------------+------------------+----------------+--------------+
-|                  Clock Signal                  |                         Enable Signal                        |                  Set/Reset Signal                 | Slice Load Count | Bel Load Count | Bels / Slice |
-+------------------------------------------------+--------------------------------------------------------------+---------------------------------------------------+------------------+----------------+--------------+
-|  clk_1/inst/clk_out1                           | dbuttons/IV[2]_i_1_n_0                                       |                                                   |                1 |              1 |         1.00 |
-|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/E[0]                         | audio_inout/SR[0]                                 |                2 |              4 |         2.00 |
-|  clk_1/inst/clk_out1                           | lrclkcnt[3]_i_2_n_0                                          | lrclkcnt[3]_i_1_n_0                               |                2 |              4 |         2.00 |
-|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0    |                                                   |                2 |              4 |         2.00 |
-|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0 | audio_inout/SR[0]                                 |                1 |              4 |         4.00 |
-|  clk_1/inst/clk_out4                           | rstn_IBUF                                                    | initialize_audio/data_i[5]_i_1_n_0                |                2 |              4 |         2.00 |
-|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0  | audio_inout/SR[0]                                 |                1 |              4 |         4.00 |
-|  clk_1/inst/clk_out1                           |                                                              | audio_inout/Cnt_Bclk[4]_i_1_n_0                   |                2 |              5 |         2.50 |
-|  leftFir/firUnit_1/controlUnit_1/SR_nextState  |                                                              |                                                   |                2 |              5 |         2.50 |
-|  rightFir/firUnit_1/controlUnit_1/SR_nextState |                                                              |                                                   |                2 |              5 |         2.50 |
-|  clk_1/inst/clk_out1                           | audio_inout/BCLK_Fall_int                                    | audio_inout/SR[0]                                 |                2 |              5 |         2.50 |
-|  clk_1/inst/clk_out1                           |                                                              |                                                   |                3 |              6 |         2.00 |
-|  clk_1/inst/clk_out4                           | rstn_IBUF                                                    |                                                   |                2 |              6 |         3.00 |
-|  clk_1/inst/clk_out4                           |                                                              | initialize_audio/twi_controller/busFreeCnt0       |                3 |              7 |         2.33 |
-|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/state_reg[3][0]              | audio_inout/SR[0]                                 |                3 |              7 |         2.33 |
-|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0            | initialize_audio/twi_controller/sclCnt[6]_i_1_n_0 |                3 |              7 |         2.33 |
-|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/dataByte[7]_i_1_n_0          |                                                   |                3 |              8 |         2.67 |
-|  clk_1/inst/clk_out1                           |                                                              | audio_inout/SR[0]                                 |                2 |             10 |         5.00 |
-|  clk_1/inst/clk_out1                           | dbuttons/cnt2                                                | dbuttons/cnt2[12]_i_1_n_0                         |                4 |             13 |         3.25 |
-|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/controlUnit_1/Q[2]                         | audio_inout/SR[0]                                 |                4 |             16 |         4.00 |
-|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/controlUnit_1/Q[2]                        | audio_inout/SR[0]                                 |                4 |             16 |         4.00 |
-|  clk_1/inst/clk_out4                           |                                                              |                                                   |               12 |             18 |         1.50 |
-|  clk_1/inst/clk_out4                           | initialize_audio/initWord[30]_i_1_n_0                        |                                                   |                5 |             23 |         4.60 |
-|  clk_1/inst/clk_out1                           | audio_inout/D_R_O_int[23]_i_1_n_0                            | audio_inout/SR[0]                                 |                5 |             24 |         4.80 |
-|  clk_1/inst/clk_out1                           | audio_inout/D_L_O_int                                        | audio_inout/SR[0]                                 |                6 |             24 |         4.00 |
-|  clk_1/inst/clk_out1                           | audio_inout/Data_Out_int[31]_i_1_n_0                         |                                                   |               10 |             25 |         2.50 |
-|  clk_1/inst/clk_out4                           |                                                              | initialize_audio/delaycnt0                        |                9 |             32 |         3.56 |
-|  clk_1/inst/clk_out1                           | audio_inout/p_4_in                                           | audio_inout/Data_In_int[31]_i_1_n_0               |                7 |             32 |         4.57 |
-|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/operativeUnit_1/SR_sum[35]_i_1_n_0        | audio_inout/SR[0]                                 |                9 |             36 |         4.00 |
-|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/operativeUnit_1/SR_sum[35]_i_1_n_0         | audio_inout/SR[0]                                 |               13 |             36 |         2.77 |
-|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/controlUnit_1/Q[0]                         | audio_inout/SR[0]                                 |               59 |            256 |         4.34 |
-|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/controlUnit_1/Q[0]                        | audio_inout/SR[0]                                 |               65 |            256 |         3.94 |
-+------------------------------------------------+--------------------------------------------------------------+---------------------------------------------------+------------------+----------------+--------------+
++------------------------------------------------+-----------------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+|                  Clock Signal                  |                          Enable Signal                          |               Set/Reset Signal              | Slice Load Count | Bel Load Count | Bels / Slice |
++------------------------------------------------+-----------------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+|  clk_1/inst/clk_out1                           | dbuttons/IV[2]_i_1_n_0                                          |                                             |                1 |              1 |         1.00 |
+|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0     | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                1 |              4 |         4.00 |
+|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0       |                                             |                2 |              4 |         2.00 |
+|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/E[0]                            | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                2 |              4 |         2.00 |
+|  clk_1/inst/clk_out4                           | rstn_IBUF                                                       | initialize_audio/data_i[5]_i_1_n_0          |                2 |              4 |         2.00 |
+|  clk_1/inst/clk_out1                           | lrclkcnt[3]_i_2_n_0                                             | lrclkcnt[3]_i_1_n_0                         |                2 |              4 |         2.00 |
+|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1__0_n_0 | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                2 |              4 |         2.00 |
+|  clk_1/inst/clk_out1                           |                                                                 | audio_inout/Cnt_Bclk[4]_i_1_n_0             |                2 |              5 |         2.50 |
+|  rightFir/firUnit_1/controlUnit_1/SR_nextState |                                                                 |                                             |                2 |              5 |         2.50 |
+|  clk_1/inst/clk_out1                           | audio_inout/BCLK_Fall_int                                       | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                2 |              5 |         2.50 |
+|  leftFir/firUnit_1/controlUnit_1/SR_nextState  |                                                                 |                                             |                2 |              5 |         2.50 |
+|  clk_1/inst/clk_out1                           |                                                                 |                                             |                3 |              6 |         2.00 |
+|  clk_1/inst/clk_out4                           | rstn_IBUF                                                       |                                             |                2 |              6 |         3.00 |
+|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/state_reg[3][0]                 | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                3 |              7 |         2.33 |
+|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0               | initialize_audio/twi_controller/sclCnt0     |                3 |              7 |         2.33 |
+|  clk_1/inst/clk_out4                           |                                                                 | initialize_audio/twi_controller/busFreeCnt0 |                3 |              7 |         2.33 |
+|  clk_1/inst/clk_out4                           | initialize_audio/twi_controller/dataByte[7]_i_1_n_0             |                                             |                3 |              8 |         2.67 |
+|  clk_1/inst/clk_out1                           |                                                                 | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                3 |             10 |         3.33 |
+|  clk_1/inst/clk_out1                           | dbuttons/cnt2                                                   | dbuttons/cnt2[12]_i_1_n_0                   |                4 |             13 |         3.25 |
+|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/controlUnit_1/Q[2]                           | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                4 |             16 |         4.00 |
+|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/controlUnit_1/Q[2]                            | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                4 |             16 |         4.00 |
+|  clk_1/inst/clk_out4                           |                                                                 |                                             |               10 |             18 |         1.80 |
+|  clk_1/inst/clk_out4                           | initialize_audio/initWord[30]_i_1_n_0                           |                                             |                6 |             23 |         3.83 |
+|  clk_1/inst/clk_out1                           | audio_inout/D_R_O_int[23]_i_1_n_0                               | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                5 |             24 |         4.80 |
+|  clk_1/inst/clk_out1                           | audio_inout/D_L_O_int                                           | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                5 |             24 |         4.80 |
+|  clk_1/inst/clk_out1                           | audio_inout/Data_Out_int[31]_i_1_n_0                            |                                             |               11 |             25 |         2.27 |
+|  clk_1/inst/clk_out4                           |                                                                 | initialize_audio/delaycnt0                  |                9 |             32 |         3.56 |
+|  clk_1/inst/clk_out1                           | audio_inout/p_4_in                                              | audio_inout/Data_In_int[31]_i_1_n_0         |                5 |             32 |         6.40 |
+|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/controlUnit_1/E[0]                            | rightFir/firUnit_1/operativeUnit_1/AR[0]    |                9 |             36 |         4.00 |
+|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/controlUnit_1/E[0]                           | rightFir/firUnit_1/operativeUnit_1/AR[0]    |               10 |             36 |         3.60 |
+|  clk_1/inst/clk_out1                           | leftFir/firUnit_1/controlUnit_1/Q[0]                            | rightFir/firUnit_1/operativeUnit_1/AR[0]    |               68 |            256 |         3.76 |
+|  clk_1/inst/clk_out1                           | rightFir/firUnit_1/controlUnit_1/Q[0]                           | rightFir/firUnit_1/operativeUnit_1/AR[0]    |               57 |            256 |         4.49 |
++------------------------------------------------+-----------------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
 
 
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
index 150e87d9f76ecbf2b05a7cc1e572ec37ce89affc..9a12e42abd1948af9593a9b893a00079095e132c 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:48:44 2025
+| Date         : Mon May 12 16:23:05 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
 | Design       : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx
index 272d1197018cd04bb9ee4f3d35246d179bad3d3a..2567447e84b61170260033b0d23e2b260f5777b3 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
index 32ea74fbd9700a4e17ee449190bcf05a30775856..31db07c4e2d8a52c804a472445dda6ad1f895812 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:49:57 2025
+| Date         : Mon May 12 16:24:08 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
 | Design       : audioProc
@@ -102,12 +102,12 @@ Related violations: <none>
 
 PDRC-153#1 Warning
 Gated clock check  
-Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
 Related violations: <none>
 
 PDRC-153#2 Warning
 Gated clock check  
-Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
 Related violations: <none>
 
 
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx
index 08c9b5d27b624947b73cc95a477237ad4b99bf41..bf45a8e63bb35e7a0c24b319d76f3c1e5c765f00 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
index 0fc2f19a72eefc42b0fdf56baf9002645fbc5cb1..07865166e076e4331107e155a79ddec2dc637bc4 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version              : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date                      : Fri May  9 15:48:58 2025
+| Date                      : Mon May 12 16:23:14 2025
 | Host                      : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command                   : report_io -file audioProc_io_placed.rpt
 | Design                    : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
index 17cde266421da3526455d616358f28823eb1e3c0..bd2415d2f8f4bb484264f260de44db48bf6246f7 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 -----------------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:49:59 2025
+| Date         : Mon May 12 16:24:10 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
 | Design       : audioProc
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx
index b9b9451440f43d5ba7cd64f0662f9bef25c503f6..218420724001b445ce09ad92a0afb61c2fd1345a 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp
index 48d550c45ce3ac2d9f7f2f4cf7930704f3dca251..97f82b66351db675faf108a69d3a9b38c34d3939 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp and b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp
index 1485d5d2077422aeb612ae124f1e67554fd6e191..de7d39a62f4c7820322a45ad9f591f0b5f8b1aee 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp and b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
index fc49f95b591cb30ed8e66584f9b204548484c3f1..08ddb39eb5c137862e2c33c557d069c8226cdfde 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 -------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version     : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date             : Fri May  9 15:50:00 2025
+| Date             : Mon May 12 16:24:11 2025
 | Host             : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command          : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
 | Design           : audioProc
@@ -33,7 +33,7 @@ Table of Contents
 | Total On-Chip Power (W)  | 0.251        |
 | Design Power Budget (W)  | Unspecified* |
 | Power Budget Margin (W)  | NA           |
-| Dynamic (W)              | 0.099        |
+| Dynamic (W)              | 0.100        |
 | Device Static (W)        | 0.151        |
 | Effective TJA (C/W)      | 3.3          |
 | Max Ambient (C)          | 84.2         |
@@ -52,14 +52,14 @@ Table of Contents
 +----------------+-----------+----------+-----------+-----------------+
 | On-Chip        | Power (W) | Used     | Available | Utilization (%) |
 +----------------+-----------+----------+-----------+-----------------+
-| Clocks         |     0.003 |        7 |       --- |             --- |
-| Slice Logic    |     0.001 |     1617 |       --- |             --- |
-|   LUT as Logic |    <0.001 |      531 |    133800 |            0.40 |
+| Clocks         |     0.004 |        7 |       --- |             --- |
+| Slice Logic    |    <0.001 |     1615 |       --- |             --- |
+|   LUT as Logic |    <0.001 |      527 |    133800 |            0.39 |
 |   CARRY4       |    <0.001 |       20 |     33450 |            0.06 |
 |   Register     |    <0.001 |      903 |    267600 |            0.34 |
 |   F7/F8 Muxes  |    <0.001 |       96 |    133800 |            0.07 |
-|   Others       |     0.000 |       23 |       --- |             --- |
-| Signals        |     0.001 |     1213 |       --- |             --- |
+|   Others       |     0.000 |       25 |       --- |             --- |
+| Signals        |     0.001 |     1209 |       --- |             --- |
 | MMCM           |     0.085 |        1 |        10 |           10.00 |
 | DSPs           |     0.002 |        2 |       740 |            0.27 |
 | I/O            |     0.007 |       22 |       285 |            7.72 |
@@ -74,7 +74,7 @@ Table of Contents
 +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
 | Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
 +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Vccint    |       1.000 |     0.039 |       0.008 |      0.031 |       NA    | Unspecified | NA         |
+| Vccint    |       1.000 |     0.039 |       0.009 |      0.031 |       NA    | Unspecified | NA         |
 | Vccaux    |       1.800 |     0.078 |       0.047 |      0.031 |       NA    | Unspecified | NA         |
 | Vcco33    |       3.300 |     0.006 |       0.001 |      0.005 |       NA    | Unspecified | NA         |
 | Vcco25    |       2.500 |     0.006 |       0.001 |      0.005 |       NA    | Unspecified | NA         |
@@ -147,15 +147,15 @@ Table of Contents
 +-----------------------+-----------+
 | Name                  | Power (W) |
 +-----------------------+-----------+
-| audioProc             |     0.099 |
+| audioProc             |     0.100 |
 |   clk_1               |     0.086 |
 |     inst              |     0.086 |
-|   leftFir             |     0.002 |
-|     firUnit_1         |     0.002 |
-|       operativeUnit_1 |     0.002 |
-|   rightFir            |     0.002 |
-|     firUnit_1         |     0.002 |
-|       operativeUnit_1 |     0.002 |
+|   leftFir             |     0.003 |
+|     firUnit_1         |     0.003 |
+|       operativeUnit_1 |     0.003 |
+|   rightFir            |     0.003 |
+|     firUnit_1         |     0.003 |
+|       operativeUnit_1 |     0.003 |
 +-----------------------+-----------+
 
 
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx
index 2e38a2fc0fa8b612077a4e95e0b9386e723a3d82..28bd014286ea521ba85b7b0685502a351621106f 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb
index 939f3d598693d12429ca71be3f1fd941c4405e62..a471017b474646c3a3413b0ece5816387eb0b1ad 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb and b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb
index 3ce7d52e579049b70af0eb58705abebcd5156caa..84f2f7af0dd05a952812ff546dd06b47c829e1ac 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb and b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
index 4e101bf919a718d0984fa8a100b74b992b5590e1..8e80ffc07d3ac9f507b67cddc17e570a0a570dc0 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
@@ -1,11 +1,11 @@
 Design Route Status
                                                :      # nets :
    ------------------------------------------- : ----------- :
-   # of logical nets.......................... :        1781 :
+   # of logical nets.......................... :        1777 :
        # of nets not needing routing.......... :         557 :
            # of internally routed nets........ :         557 :
-       # of routable nets..................... :        1224 :
-           # of fully routed nets............. :        1224 :
+       # of routable nets..................... :        1220 :
+           # of fully routed nets............. :        1220 :
        # of nets with routing errors.......... :           0 :
    ------------------------------------------- : ----------- :
 
diff --git a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp
index 54aba98e44660d9af3e80207e1c63f0a34ea793a..278f75080542490b512acb5a412e7def6d806d65 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp and b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb
index 2575ef04138d5f83cf1bfb17c0fd7c1ec3a0cb7c..2976f6c60933c3f01b0de78588e0ee309bf15f10 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
index 843ab0e28ef0f5bbb69c58fceb0eb0e4be1671c1..427e37656434e72e7b6630244f6a0ad3b14a0697 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:49:59 2025
+| Date         : Mon May 12 16:24:10 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
 | Design       : audioProc
@@ -163,7 +163,7 @@ Table of Contents
 
     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
-      0.617        0.000                      0                 1788        0.109        0.000                      0                 1788        3.000        0.000                       0                   903  
+      1.571        0.000                      0                 1788        0.030        0.000                      0                 1788        3.000        0.000                       0                   903  
 
 
 All user specified timing constraints are met.
@@ -191,9 +191,9 @@ CLK100MHZ             {0.000 5.000}      10.000          100.000
 Clock                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
 -----                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
 CLK100MHZ                                                                                                                                                               3.000        0.000                       0                     1  
-  clk_out1_clk_wiz_0        0.617        0.000                      0                 1567        0.134        0.000                      0                 1567        4.500        0.000                       0                   775  
+  clk_out1_clk_wiz_0        1.571        0.000                      0                 1567        0.030        0.000                      0                 1567        4.500        0.000                       0                   775  
   clk_out3_clk_wiz_0                                                                                                                                                   81.178        0.000                       0                     2  
-  clk_out4_clk_wiz_0       14.589        0.000                      0                  221        0.109        0.000                      0                  221        9.500        0.000                       0                   122  
+  clk_out4_clk_wiz_0       14.586        0.000                      0                  221        0.155        0.000                      0                  221        9.500        0.000                       0                   122  
   clkfbout_clk_wiz_0                                                                                                                                                    7.845        0.000                       0                     3  
 
 
@@ -252,28 +252,28 @@ High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000
 From Clock:  clk_out1_clk_wiz_0
   To Clock:  clk_out1_clk_wiz_0
 
-Setup :            0  Failing Endpoints,  Worst Slack        0.617ns,  Total Violation        0.000ns
-Hold  :            0  Failing Endpoints,  Worst Slack        0.134ns,  Total Violation        0.000ns
+Setup :            0  Failing Endpoints,  Worst Slack        1.571ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
 PW    :            0  Failing Endpoints,  Worst Slack        4.500ns,  Total Violation        0.000ns
 ---------------------------------------------------------------------------------------------------
 
 
 Max Delay Paths
 --------------------------------------------------------------------------------------
-Slack (MET) :             0.617ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.571ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.295ns  (logic 6.059ns (65.188%)  route 3.236ns (34.812%))
-  Logic Levels:           7  (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
+  Data Path Delay:        8.350ns  (logic 5.148ns (61.656%)  route 3.202ns (38.344%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
     Destination Clock Delay (DCD):    -1.657ns = ( 8.343 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -291,30 +291,23 @@ Slack (MET) :             0.617ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.117     7.982 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.982    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
-    SLICE_X152Y107       CARRY4 (Prop_carry4_CI_O[1])
-                                                      0.323     8.305 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[1]
-                         net (fo=1, routed)           0.000     8.305    rightFir/firUnit_1/operativeUnit_1/p_0_in[13]
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[14])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[14]
+                         net (fo=1, routed)           0.784     7.162    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[14]
+    SLICE_X145Y103       LUT2 (Prop_lut2_I0_O)        0.124     7.286 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[14]_i_1/O
+                         net (fo=1, routed)           0.000     7.286    leftFir/firUnit_1/operativeUnit_1/p_1_in[14]
+    SLICE_X145Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -327,31 +320,31 @@ Slack (MET) :             0.617ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.635     8.343    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/C
-                         clock pessimism              0.554     8.896    
-                         clock uncertainty           -0.084     8.813    
-    SLICE_X152Y107       FDCE (Setup_fdce_C_D)        0.109     8.922    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]
+                         net (fo=773, routed)         1.635     8.343    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/C
+                         clock pessimism              0.569     8.911    
+                         clock uncertainty           -0.084     8.828    
+    SLICE_X145Y103       FDCE (Setup_fdce_C_D)        0.029     8.857    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]
   -------------------------------------------------------------------
-                         required time                          8.922    
-                         arrival time                          -8.305    
+                         required time                          8.857    
+                         arrival time                          -7.286    
   -------------------------------------------------------------------
-                         slack                                  0.617    
+                         slack                                  1.571    
 
-Slack (MET) :             0.625ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.576ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[33]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.287ns  (logic 6.051ns (65.158%)  route 3.236ns (34.842%))
-  Logic Levels:           7  (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
+  Data Path Delay:        8.346ns  (logic 5.148ns (61.682%)  route 3.198ns (38.318%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
     Destination Clock Delay (DCD):    -1.657ns = ( 8.343 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -369,30 +362,23 @@ Slack (MET) :             0.625ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.117     7.982 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.982    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
-    SLICE_X152Y107       CARRY4 (Prop_carry4_CI_O[3])
-                                                      0.315     8.297 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[3]
-                         net (fo=1, routed)           0.000     8.297    rightFir/firUnit_1/operativeUnit_1/p_0_in[15]
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[33])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[33]
+                         net (fo=1, routed)           0.780     7.158    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[33]
+    SLICE_X145Y103       LUT2 (Prop_lut2_I0_O)        0.124     7.282 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[33]_i_1/O
+                         net (fo=1, routed)           0.000     7.282    leftFir/firUnit_1/operativeUnit_1/p_1_in[33]
+    SLICE_X145Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[33]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -405,31 +391,31 @@ Slack (MET) :             0.625ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.635     8.343    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/C
-                         clock pessimism              0.554     8.896    
-                         clock uncertainty           -0.084     8.813    
-    SLICE_X152Y107       FDCE (Setup_fdce_C_D)        0.109     8.922    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]
+                         net (fo=773, routed)         1.635     8.343    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[33]/C
+                         clock pessimism              0.569     8.911    
+                         clock uncertainty           -0.084     8.828    
+    SLICE_X145Y103       FDCE (Setup_fdce_C_D)        0.031     8.859    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[33]
   -------------------------------------------------------------------
-                         required time                          8.922    
-                         arrival time                          -8.297    
+                         required time                          8.859    
+                         arrival time                          -7.282    
   -------------------------------------------------------------------
-                         slack                                  0.625    
+                         slack                                  1.576    
 
-Slack (MET) :             0.701ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.589ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.211ns  (logic 5.975ns (64.871%)  route 3.236ns (35.129%))
-  Logic Levels:           7  (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
+  Data Path Delay:        8.334ns  (logic 5.148ns (61.774%)  route 3.186ns (38.226%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
     Destination Clock Delay (DCD):    -1.657ns = ( 8.343 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -447,30 +433,23 @@ Slack (MET) :             0.701ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.117     7.982 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.982    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
-    SLICE_X152Y107       CARRY4 (Prop_carry4_CI_O[2])
-                                                      0.239     8.221 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[2]
-                         net (fo=1, routed)           0.000     8.221    rightFir/firUnit_1/operativeUnit_1/p_0_in[14]
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[15])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[15]
+                         net (fo=1, routed)           0.768     7.146    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[15]
+    SLICE_X145Y103       LUT2 (Prop_lut2_I0_O)        0.124     7.270 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[15]_i_1/O
+                         net (fo=1, routed)           0.000     7.270    leftFir/firUnit_1/operativeUnit_1/p_1_in[15]
+    SLICE_X145Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -483,31 +462,31 @@ Slack (MET) :             0.701ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.635     8.343    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]/C
-                         clock pessimism              0.554     8.896    
-                         clock uncertainty           -0.084     8.813    
-    SLICE_X152Y107       FDCE (Setup_fdce_C_D)        0.109     8.922    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[14]
+                         net (fo=773, routed)         1.635     8.343    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]/C
+                         clock pessimism              0.569     8.911    
+                         clock uncertainty           -0.084     8.828    
+    SLICE_X145Y103       FDCE (Setup_fdce_C_D)        0.031     8.859    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]
   -------------------------------------------------------------------
-                         required time                          8.922    
-                         arrival time                          -8.221    
+                         required time                          8.859    
+                         arrival time                          -7.270    
   -------------------------------------------------------------------
-                         slack                                  0.701    
+                         slack                                  1.589    
 
-Slack (MET) :             0.721ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.601ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[20]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.191ns  (logic 5.955ns (64.794%)  route 3.236ns (35.206%))
-  Logic Levels:           7  (CARRY4=3 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.657ns = ( 8.343 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+  Data Path Delay:        8.320ns  (logic 5.148ns (61.875%)  route 3.172ns (38.125%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -525,30 +504,23 @@ Slack (MET) :             0.721ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.117     7.982 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.982    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
-    SLICE_X152Y107       CARRY4 (Prop_carry4_CI_O[0])
-                                                      0.219     8.201 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[0]
-                         net (fo=1, routed)           0.000     8.201    rightFir/firUnit_1/operativeUnit_1/p_0_in[12]
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
+                         net (fo=1, routed)           0.754     7.132    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[20]
+    SLICE_X145Y100       LUT2 (Prop_lut2_I0_O)        0.124     7.256 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[20]_i_1/O
+                         net (fo=1, routed)           0.000     7.256    leftFir/firUnit_1/operativeUnit_1/p_1_in[20]
+    SLICE_X145Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[20]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -561,31 +533,31 @@ Slack (MET) :             0.721ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.635     8.343    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]/C
-                         clock pessimism              0.554     8.896    
-                         clock uncertainty           -0.084     8.813    
-    SLICE_X152Y107       FDCE (Setup_fdce_C_D)        0.109     8.922    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[12]
+                         net (fo=773, routed)         1.636     8.344    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[20]/C
+                         clock pessimism              0.569     8.912    
+                         clock uncertainty           -0.084     8.829    
+    SLICE_X145Y100       FDCE (Setup_fdce_C_D)        0.029     8.858    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[20]
   -------------------------------------------------------------------
-                         required time                          8.922    
-                         arrival time                          -8.201    
+                         required time                          8.858    
+                         arrival time                          -7.256    
   -------------------------------------------------------------------
-                         slack                                  0.721    
+                         slack                                  1.601    
 
-Slack (MET) :             0.735ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.601ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[24]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.178ns  (logic 5.942ns (64.745%)  route 3.236ns (35.255%))
-  Logic Levels:           6  (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
+  Data Path Delay:        8.320ns  (logic 5.148ns (61.875%)  route 3.172ns (38.125%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
     Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -603,27 +575,23 @@ Slack (MET) :             0.735ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_O[1])
-                                                      0.323     8.188 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[1]
-                         net (fo=1, routed)           0.000     8.188    rightFir/firUnit_1/operativeUnit_1/p_0_in[9]
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[24])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[24]
+                         net (fo=1, routed)           0.754     7.132    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[24]
+    SLICE_X145Y101       LUT2 (Prop_lut2_I0_O)        0.124     7.256 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[24]_i_1/O
+                         net (fo=1, routed)           0.000     7.256    leftFir/firUnit_1/operativeUnit_1/p_1_in[24]
+    SLICE_X145Y101       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[24]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -636,31 +604,31 @@ Slack (MET) :             0.735ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.636     8.344    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]/C
-                         clock pessimism              0.554     8.897    
-                         clock uncertainty           -0.084     8.814    
-    SLICE_X152Y106       FDCE (Setup_fdce_C_D)        0.109     8.923    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[9]
+                         net (fo=773, routed)         1.636     8.344    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y101       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[24]/C
+                         clock pessimism              0.569     8.912    
+                         clock uncertainty           -0.084     8.829    
+    SLICE_X145Y101       FDCE (Setup_fdce_C_D)        0.029     8.858    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[24]
   -------------------------------------------------------------------
-                         required time                          8.923    
-                         arrival time                          -8.188    
+                         required time                          8.858    
+                         arrival time                          -7.256    
   -------------------------------------------------------------------
-                         slack                                  0.735    
+                         slack                                  1.601    
 
-Slack (MET) :             0.743ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.601ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[28]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.170ns  (logic 5.934ns (64.714%)  route 3.236ns (35.286%))
-  Logic Levels:           6  (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
+  Data Path Delay:        8.320ns  (logic 5.148ns (61.875%)  route 3.172ns (38.125%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
     Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -678,27 +646,23 @@ Slack (MET) :             0.743ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_O[3])
-                                                      0.315     8.180 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[3]
-                         net (fo=1, routed)           0.000     8.180    rightFir/firUnit_1/operativeUnit_1/p_0_in[11]
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[28])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[28]
+                         net (fo=1, routed)           0.754     7.132    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[28]
+    SLICE_X145Y102       LUT2 (Prop_lut2_I0_O)        0.124     7.256 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[28]_i_1/O
+                         net (fo=1, routed)           0.000     7.256    leftFir/firUnit_1/operativeUnit_1/p_1_in[28]
+    SLICE_X145Y102       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[28]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -711,30 +675,30 @@ Slack (MET) :             0.743ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.636     8.344    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]/C
-                         clock pessimism              0.554     8.897    
-                         clock uncertainty           -0.084     8.814    
-    SLICE_X152Y106       FDCE (Setup_fdce_C_D)        0.109     8.923    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]
+                         net (fo=773, routed)         1.636     8.344    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y102       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[28]/C
+                         clock pessimism              0.569     8.912    
+                         clock uncertainty           -0.084     8.829    
+    SLICE_X145Y102       FDCE (Setup_fdce_C_D)        0.029     8.858    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[28]
   -------------------------------------------------------------------
-                         required time                          8.923    
-                         arrival time                          -8.180    
+                         required time                          8.858    
+                         arrival time                          -7.256    
   -------------------------------------------------------------------
-                         slack                                  0.743    
+                         slack                                  1.601    
 
-Slack (MET) :             0.769ns  (required time - arrival time)
+Slack (MET) :             1.607ns  (required time - arrival time)
   Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.185ns  (logic 6.198ns (67.481%)  route 2.987ns (32.519%))
-  Logic Levels:           8  (CARRY4=4 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.659ns = ( 8.341 - 10.000 ) 
-    Source Clock Delay      (SCD):    -1.066ns
+  Data Path Delay:        8.317ns  (logic 5.148ns (61.894%)  route 3.169ns (38.106%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
+    Source Clock Delay      (SCD):    -1.064ns
     Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -753,33 +717,23 @@ Slack (MET) :             0.769ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.753    -1.066    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X145Y110       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X145Y110       FDCE (Prop_fdce_C_Q)         0.456    -0.610 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.538     0.928    leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X137Y104       LUT6 (Prop_lut6_I2_O)        0.124     1.052 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122/O
-                         net (fo=1, routed)           0.000     1.052    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122_n_0
-    SLICE_X137Y104       MUXF7 (Prop_muxf7_I1_O)      0.245     1.297 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59/O
-                         net (fo=1, routed)           0.000     1.297    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59_n_0
-    SLICE_X137Y104       MUXF8 (Prop_muxf8_I0_O)      0.104     1.401 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_28/O
-                         net (fo=1, routed)           0.656     2.057    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[0]
-    DSP48_X7Y42          DSP48E1 (Prop_dsp48e1_A[0]_P[16])
-                                                      4.033     6.090 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[16]
-                         net (fo=2, routed)           0.793     6.883    leftFir/firUnit_1/operativeUnit_1/L[16]
-    SLICE_X145Y106       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.674     7.557 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.557    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
-    SLICE_X145Y107       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.114     7.671 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.671    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X145Y108       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.114     7.785 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.785    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
-    SLICE_X145Y109       CARRY4 (Prop_carry4_CI_O[1])
-                                                      0.334     8.119 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[1]
-                         net (fo=1, routed)           0.000     8.119    leftFir/firUnit_1/operativeUnit_1/p_0_in[13]
-    SLICE_X145Y109       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[9])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[9]
+                         net (fo=1, routed)           0.752     7.130    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[9]
+    SLICE_X145Y102       LUT2 (Prop_lut2_I0_O)        0.124     7.254 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[9]_i_1/O
+                         net (fo=1, routed)           0.000     7.254    leftFir/firUnit_1/operativeUnit_1/p_1_in[9]
+    SLICE_X145Y102       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -792,30 +746,30 @@ Slack (MET) :             0.769ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.633     8.341    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X145Y109       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]/C
-                         clock pessimism              0.569     8.909    
-                         clock uncertainty           -0.084     8.826    
-    SLICE_X145Y109       FDCE (Setup_fdce_C_D)        0.062     8.888    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[13]
+                         net (fo=773, routed)         1.636     8.344    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X145Y102       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]/C
+                         clock pessimism              0.569     8.912    
+                         clock uncertainty           -0.084     8.829    
+    SLICE_X145Y102       FDCE (Setup_fdce_C_D)        0.032     8.861    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]
   -------------------------------------------------------------------
-                         required time                          8.888    
-                         arrival time                          -8.119    
+                         required time                          8.861    
+                         arrival time                          -7.254    
   -------------------------------------------------------------------
-                         slack                                  0.769    
+                         slack                                  1.607    
 
-Slack (MET) :             0.790ns  (required time - arrival time)
+Slack (MET) :             1.612ns  (required time - arrival time)
   Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[0]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.164ns  (logic 6.177ns (67.406%)  route 2.987ns (32.594%))
-  Logic Levels:           8  (CARRY4=4 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.659ns = ( 8.341 - 10.000 ) 
-    Source Clock Delay      (SCD):    -1.066ns
+  Data Path Delay:        8.360ns  (logic 5.148ns (61.582%)  route 3.212ns (38.418%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
+    Source Clock Delay      (SCD):    -1.064ns
     Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -834,33 +788,23 @@ Slack (MET) :             0.790ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.753    -1.066    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X145Y110       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X145Y110       FDCE (Prop_fdce_C_Q)         0.456    -0.610 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.538     0.928    leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X137Y104       LUT6 (Prop_lut6_I2_O)        0.124     1.052 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122/O
-                         net (fo=1, routed)           0.000     1.052    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_122_n_0
-    SLICE_X137Y104       MUXF7 (Prop_muxf7_I1_O)      0.245     1.297 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59/O
-                         net (fo=1, routed)           0.000     1.297    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_59_n_0
-    SLICE_X137Y104       MUXF8 (Prop_muxf8_I0_O)      0.104     1.401 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_28/O
-                         net (fo=1, routed)           0.656     2.057    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[0]
-    DSP48_X7Y42          DSP48E1 (Prop_dsp48e1_A[0]_P[16])
-                                                      4.033     6.090 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[16]
-                         net (fo=2, routed)           0.793     6.883    leftFir/firUnit_1/operativeUnit_1/L[16]
-    SLICE_X145Y106       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.674     7.557 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.557    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[3]_i_1_n_0
-    SLICE_X145Y107       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.114     7.671 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.671    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X145Y108       CARRY4 (Prop_carry4_CI_CO[3])
-                                                      0.114     7.785 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.785    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1_n_0
-    SLICE_X145Y109       CARRY4 (Prop_carry4_CI_O[3])
-                                                      0.313     8.098 r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]_i_1/O[3]
-                         net (fo=1, routed)           0.000     8.098    leftFir/firUnit_1/operativeUnit_1/p_0_in[15]
-    SLICE_X145Y109       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[0])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[0]
+                         net (fo=1, routed)           0.794     7.172    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[0]
+    SLICE_X144Y100       LUT2 (Prop_lut2_I0_O)        0.124     7.296 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[0]_i_1/O
+                         net (fo=1, routed)           0.000     7.296    leftFir/firUnit_1/operativeUnit_1/p_1_in[0]
+    SLICE_X144Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[0]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -873,31 +817,31 @@ Slack (MET) :             0.790ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.633     8.341    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X145Y109       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]/C
-                         clock pessimism              0.569     8.909    
-                         clock uncertainty           -0.084     8.826    
-    SLICE_X145Y109       FDCE (Setup_fdce_C_D)        0.062     8.888    leftFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[15]
+                         net (fo=773, routed)         1.636     8.344    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[0]/C
+                         clock pessimism              0.569     8.912    
+                         clock uncertainty           -0.084     8.829    
+    SLICE_X144Y100       FDCE (Setup_fdce_C_D)        0.079     8.908    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[0]
   -------------------------------------------------------------------
-                         required time                          8.888    
-                         arrival time                          -8.098    
+                         required time                          8.908    
+                         arrival time                          -7.296    
   -------------------------------------------------------------------
-                         slack                                  0.790    
+                         slack                                  1.612    
 
-Slack (MET) :             0.819ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.614ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[8]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.094ns  (logic 5.858ns (64.419%)  route 3.236ns (35.581%))
-  Logic Levels:           6  (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
+  Data Path Delay:        8.358ns  (logic 5.148ns (61.594%)  route 3.210ns (38.406%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
     Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -915,27 +859,23 @@ Slack (MET) :             0.819ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_O[2])
-                                                      0.239     8.104 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[2]
-                         net (fo=1, routed)           0.000     8.104    rightFir/firUnit_1/operativeUnit_1/p_0_in[10]
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[8])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[8]
+                         net (fo=1, routed)           0.792     7.170    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[8]
+    SLICE_X144Y102       LUT2 (Prop_lut2_I0_O)        0.124     7.294 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[8]_i_1/O
+                         net (fo=1, routed)           0.000     7.294    leftFir/firUnit_1/operativeUnit_1/p_1_in[8]
+    SLICE_X144Y102       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[8]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -948,31 +888,31 @@ Slack (MET) :             0.819ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.636     8.344    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]/C
-                         clock pessimism              0.554     8.897    
-                         clock uncertainty           -0.084     8.814    
-    SLICE_X152Y106       FDCE (Setup_fdce_C_D)        0.109     8.923    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[10]
+                         net (fo=773, routed)         1.636     8.344    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y102       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[8]/C
+                         clock pessimism              0.569     8.912    
+                         clock uncertainty           -0.084     8.829    
+    SLICE_X144Y102       FDCE (Setup_fdce_C_D)        0.079     8.908    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[8]
   -------------------------------------------------------------------
-                         required time                          8.923    
-                         arrival time                          -8.104    
+                         required time                          8.908    
+                         arrival time                          -7.294    
   -------------------------------------------------------------------
-                         slack                                  0.819    
+                         slack                                  1.614    
 
-Slack (MET) :             0.839ns  (required time - arrival time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+Slack (MET) :             1.617ns  (required time - arrival time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[32]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            10.000ns  (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        9.074ns  (logic 5.838ns (64.340%)  route 3.236ns (35.660%))
-  Logic Levels:           6  (CARRY4=2 DSP48E1=1 LUT6=1 MUXF7=1 MUXF8=1)
-  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.656ns = ( 8.344 - 10.000 ) 
-    Source Clock Delay      (SCD):    -0.990ns
-    Clock Pessimism Removal (CPR):    0.554ns
+  Data Path Delay:        8.354ns  (logic 5.148ns (61.623%)  route 3.206ns (38.377%))
+  Logic Levels:           5  (DSP48E1=1 LUT2=1 LUT6=1 MUXF7=1 MUXF8=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.657ns = ( 8.343 - 10.000 ) 
+    Source Clock Delay      (SCD):    -1.064ns
+    Clock Pessimism Removal (CPR):    0.569ns
   Clock Uncertainty:      0.084ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
     Discrete Jitter          (DJ):    0.151ns
@@ -990,27 +930,23 @@ Slack (MET) :             0.839ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.829    -0.990    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X156Y108       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y108       FDCE (Prop_fdce_C_Q)         0.456    -0.534 r  rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
-                         net (fo=79, routed)          1.549     1.015    rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
-    SLICE_X149Y103       LUT6 (Prop_lut6_I2_O)        0.124     1.139 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
-                         net (fo=1, routed)           0.000     1.139    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
-    SLICE_X149Y103       MUXF7 (Prop_muxf7_I1_O)      0.245     1.384 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
-                         net (fo=1, routed)           0.000     1.384    rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
-    SLICE_X149Y103       MUXF8 (Prop_muxf8_I0_O)      0.104     1.488 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
-                         net (fo=15, routed)          0.761     2.249    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
-    DSP48_X8Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[20])
-                                                      4.033     6.282 r  rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[20]
-                         net (fo=2, routed)           0.925     7.208    rightFir/firUnit_1/operativeUnit_1/L[20]
-    SLICE_X152Y105       CARRY4 (Prop_carry4_S[1]_CO[3])
-                                                      0.657     7.865 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1/CO[3]
-                         net (fo=1, routed)           0.000     7.865    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[7]_i_1_n_0
-    SLICE_X152Y106       CARRY4 (Prop_carry4_CI_O[0])
-                                                      0.219     8.084 r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[11]_i_1/O[0]
-                         net (fo=1, routed)           0.000     8.084    rightFir/firUnit_1/operativeUnit_1/p_0_in[8]
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]/D
+                         net (fo=773, routed)         1.755    -1.064    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X144Y105       FDCE (Prop_fdce_C_Q)         0.518    -0.546 r  leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+                         net (fo=81, routed)          1.278     0.733    leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+    SLICE_X147Y109       LUT6 (Prop_lut6_I2_O)        0.124     0.857 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62/O
+                         net (fo=1, routed)           0.000     0.857    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_62_n_0
+    SLICE_X147Y109       MUXF7 (Prop_muxf7_I1_O)      0.245     1.102 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29/O
+                         net (fo=1, routed)           0.000     1.102    leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_29_n_0
+    SLICE_X147Y109       MUXF8 (Prop_muxf8_I0_O)      0.104     1.206 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult_i_13/O
+                         net (fo=15, routed)          1.139     2.345    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[15]
+    DSP48_X7Y40          DSP48E1 (Prop_dsp48e1_A[23]_P[32])
+                                                      4.033     6.378 r  leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[32]
+                         net (fo=1, routed)           0.788     7.166    leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[32]
+    SLICE_X144Y103       LUT2 (Prop_lut2_I0_O)        0.124     7.290 r  leftFir/firUnit_1/operativeUnit_1/SR_sum[32]_i_1/O
+                         net (fo=1, routed)           0.000     7.290    leftFir/firUnit_1/operativeUnit_1/p_1_in[32]
+    SLICE_X144Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[32]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1023,16 +959,16 @@ Slack (MET) :             0.839ns  (required time - arrival time)
                                                      -7.674     4.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           1.723     6.616    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     6.707 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         1.636     8.344    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X152Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]/C
-                         clock pessimism              0.554     8.897    
-                         clock uncertainty           -0.084     8.814    
-    SLICE_X152Y106       FDCE (Setup_fdce_C_D)        0.109     8.923    rightFir/firUnit_1/operativeUnit_1/SR_filteredSample_reg[8]
+                         net (fo=773, routed)         1.635     8.343    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X144Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[32]/C
+                         clock pessimism              0.569     8.911    
+                         clock uncertainty           -0.084     8.828    
+    SLICE_X144Y103       FDCE (Setup_fdce_C_D)        0.079     8.907    leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[32]
   -------------------------------------------------------------------
-                         required time                          8.923    
-                         arrival time                          -8.084    
+                         required time                          8.907    
+                         arrival time                          -7.290    
   -------------------------------------------------------------------
-                         slack                                  0.839    
+                         slack                                  1.617    
 
 
 
@@ -1040,20 +976,20 @@ Slack (MET) :             0.839ns  (required time - arrival time)
 
 Min Delay Paths
 --------------------------------------------------------------------------------------
-Slack (MET) :             0.134ns  (arrival time - required time)
-  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+Slack (MET) :             0.030ns  (arrival time - required time)
+  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][3]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][3]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.209ns  (logic 0.141ns (67.433%)  route 0.068ns (32.567%))
+  Data Path Delay:        0.362ns  (logic 0.128ns (35.373%)  route 0.234ns (64.627%))
   Logic Levels:           0  
-  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.925ns
-    Source Clock Delay      (SCD):    -0.683ns
-    Clock Pessimism Removal (CPR):    -0.242ns
+  Clock Path Skew:        0.338ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.823ns
+    Source Clock Delay      (SCD):    -0.652ns
+    Clock Pessimism Removal (CPR):    -0.509ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1067,12 +1003,12 @@ Slack (MET) :             0.134ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.617    -0.683    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X143Y110       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+                         net (fo=773, routed)         0.648    -0.652    rightFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X156Y100       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][3]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X143Y110       FDCE (Prop_fdce_C_Q)         0.141    -0.542 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/Q
-                         net (fo=2, routed)           0.068    -0.474    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[14]
-    SLICE_X143Y110       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+    SLICE_X156Y100       FDCE (Prop_fdce_C_Q)         0.128    -0.524 r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][3]/Q
+                         net (fo=2, routed)           0.234    -0.290    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_3[3]
+    SLICE_X157Y99        FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][3]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1085,30 +1021,30 @@ Slack (MET) :             0.134ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.889    -0.925    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X143Y110       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/C
-                         clock pessimism              0.242    -0.683    
-    SLICE_X143Y110       FDCE (Hold_fdce_C_D)         0.075    -0.608    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]
+                         net (fo=773, routed)         0.991    -0.823    rightFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X157Y99        FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][3]/C
+                         clock pessimism              0.509    -0.314    
+    SLICE_X157Y99        FDCE (Hold_fdce_C_D)        -0.006    -0.320    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][3]
   -------------------------------------------------------------------
-                         required time                          0.608    
-                         arrival time                          -0.474    
+                         required time                          0.320    
+                         arrival time                          -0.290    
   -------------------------------------------------------------------
-                         slack                                  0.134    
+                         slack                                  0.030    
 
-Slack (MET) :             0.142ns  (arrival time - required time)
-  Source:                 audio_inout/Data_Out_int_reg[9]/C
-                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            audio_inout/Data_Out_int_reg[10]/D
-                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
+Slack (MET) :             0.055ns  (arrival time - required time)
+  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/C
+                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]/D
+                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.300ns  (logic 0.186ns (62.061%)  route 0.114ns (37.939%))
-  Logic Levels:           1  (LUT6=1)
-  Clock Path Skew:        0.037ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.925ns
-    Source Clock Delay      (SCD):    -0.682ns
-    Clock Pessimism Removal (CPR):    -0.280ns
+  Data Path Delay:        0.331ns  (logic 0.141ns (42.582%)  route 0.190ns (57.418%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.201ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.893ns
+    Source Clock Delay      (SCD):    -0.585ns
+    Clock Pessimism Removal (CPR):    -0.509ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1122,14 +1058,12 @@ Slack (MET) :             0.142ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.618    -0.682    audio_inout/clk_out1
-    SLICE_X155Y112       FDRE                                         r  audio_inout/Data_Out_int_reg[9]/C
+                         net (fo=773, routed)         0.714    -0.585    rightFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X157Y99        FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X155Y112       FDRE (Prop_fdre_C_Q)         0.141    -0.541 r  audio_inout/Data_Out_int_reg[9]/Q
-                         net (fo=1, routed)           0.114    -0.427    audio_inout/Data_Out_int_reg_n_0_[9]
-    SLICE_X152Y112       LUT6 (Prop_lut6_I4_O)        0.045    -0.382 r  audio_inout/Data_Out_int[10]_i_1/O
-                         net (fo=1, routed)           0.000    -0.382    audio_inout/Data_Out_int[10]_i_1_n_0
-    SLICE_X152Y112       FDRE                                         r  audio_inout/Data_Out_int_reg[10]/D
+    SLICE_X157Y99        FDCE (Prop_fdce_C_Q)         0.141    -0.444 r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/Q
+                         net (fo=2, routed)           0.190    -0.254    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10]_11[3]
+    SLICE_X156Y100       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1142,30 +1076,30 @@ Slack (MET) :             0.142ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.889    -0.925    audio_inout/clk_out1
-    SLICE_X152Y112       FDRE                                         r  audio_inout/Data_Out_int_reg[10]/C
-                         clock pessimism              0.280    -0.645    
-    SLICE_X152Y112       FDRE (Hold_fdre_C_D)         0.121    -0.524    audio_inout/Data_Out_int_reg[10]
+                         net (fo=773, routed)         0.921    -0.893    rightFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X156Y100       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]/C
+                         clock pessimism              0.509    -0.384    
+    SLICE_X156Y100       FDCE (Hold_fdce_C_D)         0.075    -0.309    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]
   -------------------------------------------------------------------
-                         required time                          0.524    
-                         arrival time                          -0.382    
+                         required time                          0.309    
+                         arrival time                          -0.254    
   -------------------------------------------------------------------
-                         slack                                  0.142    
+                         slack                                  0.055    
 
-Slack (MET) :             0.143ns  (arrival time - required time)
-  Source:                 audio_inout/Data_Out_int_reg[23]/C
+Slack (MET) :             0.109ns  (arrival time - required time)
+  Source:                 audio_inout/Data_Out_int_reg[20]/C
                             (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            audio_inout/Data_Out_int_reg[24]/D
+  Destination:            audio_inout/Data_Out_int_reg[21]/D
                             (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.301ns  (logic 0.186ns (61.698%)  route 0.115ns (38.302%))
+  Data Path Delay:        0.242ns  (logic 0.186ns (76.827%)  route 0.056ns (23.173%))
   Logic Levels:           1  (LUT6=1)
-  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
     Destination Clock Delay (DCD):    -0.922ns
     Source Clock Delay      (SCD):    -0.680ns
-    Clock Pessimism Removal (CPR):    -0.280ns
+    Clock Pessimism Removal (CPR):    -0.255ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1180,13 +1114,13 @@ Slack (MET) :             0.143ns  (arrival time - required time)
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
                          net (fo=773, routed)         0.620    -0.680    audio_inout/clk_out1
-    SLICE_X153Y107       FDRE                                         r  audio_inout/Data_Out_int_reg[23]/C
+    SLICE_X151Y103       FDRE                                         r  audio_inout/Data_Out_int_reg[20]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X153Y107       FDRE (Prop_fdre_C_Q)         0.141    -0.539 r  audio_inout/Data_Out_int_reg[23]/Q
-                         net (fo=1, routed)           0.115    -0.423    audio_inout/Data_Out_int_reg_n_0_[23]
-    SLICE_X154Y108       LUT6 (Prop_lut6_I3_O)        0.045    -0.378 r  audio_inout/Data_Out_int[24]_i_1/O
-                         net (fo=1, routed)           0.000    -0.378    audio_inout/Data_Out_int[24]_i_1_n_0
-    SLICE_X154Y108       FDRE                                         r  audio_inout/Data_Out_int_reg[24]/D
+    SLICE_X151Y103       FDRE (Prop_fdre_C_Q)         0.141    -0.539 r  audio_inout/Data_Out_int_reg[20]/Q
+                         net (fo=1, routed)           0.056    -0.483    audio_inout/Data_Out_int_reg_n_0_[20]
+    SLICE_X150Y103       LUT6 (Prop_lut6_I1_O)        0.045    -0.438 r  audio_inout/Data_Out_int[21]_i_1/O
+                         net (fo=1, routed)           0.000    -0.438    audio_inout/Data_Out_int[21]_i_1_n_0
+    SLICE_X150Y103       FDRE                                         r  audio_inout/Data_Out_int_reg[21]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1200,29 +1134,29 @@ Slack (MET) :             0.143ns  (arrival time - required time)
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
                          net (fo=773, routed)         0.892    -0.922    audio_inout/clk_out1
-    SLICE_X154Y108       FDRE                                         r  audio_inout/Data_Out_int_reg[24]/C
-                         clock pessimism              0.280    -0.642    
-    SLICE_X154Y108       FDRE (Hold_fdre_C_D)         0.120    -0.522    audio_inout/Data_Out_int_reg[24]
+    SLICE_X150Y103       FDRE                                         r  audio_inout/Data_Out_int_reg[21]/C
+                         clock pessimism              0.255    -0.667    
+    SLICE_X150Y103       FDRE (Hold_fdre_C_D)         0.120    -0.547    audio_inout/Data_Out_int_reg[21]
   -------------------------------------------------------------------
-                         required time                          0.522    
-                         arrival time                          -0.378    
+                         required time                          0.547    
+                         arrival time                          -0.438    
   -------------------------------------------------------------------
-                         slack                                  0.143    
+                         slack                                  0.109    
 
-Slack (MET) :             0.159ns  (arrival time - required time)
-  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/C
-                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]/D
+Slack (MET) :             0.117ns  (arrival time - required time)
+  Source:                 audio_inout/D_R_O_int_reg[15]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.253ns  (logic 0.141ns (55.700%)  route 0.112ns (44.300%))
-  Logic Levels:           0  
-  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.948ns
-    Source Clock Delay      (SCD):    -0.705ns
-    Clock Pessimism Removal (CPR):    -0.259ns
+  Data Path Delay:        0.251ns  (logic 0.186ns (74.042%)  route 0.065ns (25.958%))
+  Logic Levels:           1  (LUT2=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.921ns
+    Source Clock Delay      (SCD):    -0.679ns
+    Clock Pessimism Removal (CPR):    -0.255ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1236,12 +1170,14 @@ Slack (MET) :             0.159ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.595    -0.705    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X138Y106       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/C
+                         net (fo=773, routed)         0.621    -0.679    audio_inout/clk_out1
+    SLICE_X155Y104       FDRE                                         r  audio_inout/D_R_O_int_reg[15]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X138Y106       FDCE (Prop_fdce_C_Q)         0.141    -0.564 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/Q
-                         net (fo=2, routed)           0.112    -0.452    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8]_15[7]
-    SLICE_X137Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]/D
+    SLICE_X155Y104       FDRE (Prop_fdre_C_Q)         0.141    -0.538 r  audio_inout/D_R_O_int_reg[15]/Q
+                         net (fo=2, routed)           0.065    -0.473    audio_inout/D_R_O_int_reg[22]_0[3]
+    SLICE_X154Y104       LUT2 (Prop_lut2_I0_O)        0.045    -0.428 r  audio_inout/SR_shiftRegister[0][7]_i_1/O
+                         net (fo=1, routed)           0.000    -0.428    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][15]_0[7]
+    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1254,30 +1190,30 @@ Slack (MET) :             0.159ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.866    -0.948    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X137Y105       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]/C
-                         clock pessimism              0.259    -0.689    
-    SLICE_X137Y105       FDCE (Hold_fdce_C_D)         0.078    -0.611    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][7]
+                         net (fo=773, routed)         0.893    -0.921    rightFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/C
+                         clock pessimism              0.255    -0.666    
+    SLICE_X154Y104       FDCE (Hold_fdce_C_D)         0.121    -0.545    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]
   -------------------------------------------------------------------
-                         required time                          0.611    
-                         arrival time                          -0.452    
+                         required time                          0.545    
+                         arrival time                          -0.428    
   -------------------------------------------------------------------
-                         slack                                  0.159    
+                         slack                                  0.117    
 
-Slack (MET) :             0.160ns  (arrival time - required time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][1]/C
-                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]/D
+Slack (MET) :             0.117ns  (arrival time - required time)
+  Source:                 audio_inout/D_R_O_int_reg[16]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][8]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.268ns  (logic 0.141ns (52.702%)  route 0.127ns (47.298%))
-  Logic Levels:           0  
-  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.894ns
-    Source Clock Delay      (SCD):    -0.652ns
-    Clock Pessimism Removal (CPR):    -0.280ns
+  Data Path Delay:        0.251ns  (logic 0.186ns (74.042%)  route 0.065ns (25.958%))
+  Logic Levels:           1  (LUT5=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.921ns
+    Source Clock Delay      (SCD):    -0.679ns
+    Clock Pessimism Removal (CPR):    -0.255ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1291,12 +1227,14 @@ Slack (MET) :             0.160ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.648    -0.652    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X161Y103       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][1]/C
+                         net (fo=773, routed)         0.621    -0.679    audio_inout/clk_out1
+    SLICE_X155Y104       FDRE                                         r  audio_inout/D_R_O_int_reg[16]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X161Y103       FDCE (Prop_fdce_C_Q)         0.141    -0.511 r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][1]/Q
-                         net (fo=2, routed)           0.127    -0.384    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11]_3[1]
-    SLICE_X159Y103       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]/D
+    SLICE_X155Y104       FDRE (Prop_fdre_C_Q)         0.141    -0.538 r  audio_inout/D_R_O_int_reg[16]/Q
+                         net (fo=2, routed)           0.065    -0.473    audio_inout/in_audioR[16]
+    SLICE_X154Y104       LUT5 (Prop_lut5_I0_O)        0.045    -0.428 r  audio_inout/SR_shiftRegister[0][8]_i_1/O
+                         net (fo=1, routed)           0.000    -0.428    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][15]_0[8]
+    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][8]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1309,30 +1247,30 @@ Slack (MET) :             0.160ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.920    -0.894    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X159Y103       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]/C
-                         clock pessimism              0.280    -0.614    
-    SLICE_X159Y103       FDCE (Hold_fdce_C_D)         0.070    -0.544    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][1]
+                         net (fo=773, routed)         0.893    -0.921    rightFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][8]/C
+                         clock pessimism              0.255    -0.666    
+    SLICE_X154Y104       FDCE (Hold_fdce_C_D)         0.121    -0.545    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][8]
   -------------------------------------------------------------------
-                         required time                          0.544    
-                         arrival time                          -0.384    
+                         required time                          0.545    
+                         arrival time                          -0.428    
   -------------------------------------------------------------------
-                         slack                                  0.160    
+                         slack                                  0.117    
 
-Slack (MET) :             0.168ns  (arrival time - required time)
-  Source:                 audio_inout/D_L_O_int_reg[1]/C
+Slack (MET) :             0.118ns  (arrival time - required time)
+  Source:                 audio_inout/Data_In_int_reg[26]/C
                             (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            audio_inout/Data_Out_int_reg[8]/D
+  Destination:            audio_inout/D_L_O_int_reg[18]/D
                             (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.297ns  (logic 0.186ns (62.622%)  route 0.111ns (37.378%))
-  Logic Levels:           1  (LUT6=1)
-  Clock Path Skew:        0.037ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.925ns
-    Source Clock Delay      (SCD):    -0.682ns
-    Clock Pessimism Removal (CPR):    -0.280ns
+  Data Path Delay:        0.207ns  (logic 0.141ns (68.017%)  route 0.066ns (31.983%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.922ns
+    Source Clock Delay      (SCD):    -0.680ns
+    Clock Pessimism Removal (CPR):    -0.255ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1346,14 +1284,12 @@ Slack (MET) :             0.168ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.618    -0.682    audio_inout/clk_out1
-    SLICE_X153Y112       FDRE                                         r  audio_inout/D_L_O_int_reg[1]/C
+                         net (fo=773, routed)         0.620    -0.680    audio_inout/clk_out1
+    SLICE_X149Y105       FDRE                                         r  audio_inout/Data_In_int_reg[26]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X153Y112       FDRE (Prop_fdre_C_Q)         0.141    -0.541 r  audio_inout/D_L_O_int_reg[1]/Q
-                         net (fo=1, routed)           0.111    -0.430    audio_inout/in_audioL[1]
-    SLICE_X155Y112       LUT6 (Prop_lut6_I1_O)        0.045    -0.385 r  audio_inout/Data_Out_int[8]_i_1/O
-                         net (fo=1, routed)           0.000    -0.385    audio_inout/Data_Out_int[8]_i_1_n_0
-    SLICE_X155Y112       FDRE                                         r  audio_inout/Data_Out_int_reg[8]/D
+    SLICE_X149Y105       FDRE (Prop_fdre_C_Q)         0.141    -0.539 r  audio_inout/Data_In_int_reg[26]/Q
+                         net (fo=3, routed)           0.066    -0.472    audio_inout/p_0_in__0[18]
+    SLICE_X148Y105       FDRE                                         r  audio_inout/D_L_O_int_reg[18]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1366,29 +1302,29 @@ Slack (MET) :             0.168ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.889    -0.925    audio_inout/clk_out1
-    SLICE_X155Y112       FDRE                                         r  audio_inout/Data_Out_int_reg[8]/C
-                         clock pessimism              0.280    -0.645    
-    SLICE_X155Y112       FDRE (Hold_fdre_C_D)         0.092    -0.553    audio_inout/Data_Out_int_reg[8]
+                         net (fo=773, routed)         0.892    -0.922    audio_inout/clk_out1
+    SLICE_X148Y105       FDRE                                         r  audio_inout/D_L_O_int_reg[18]/C
+                         clock pessimism              0.255    -0.667    
+    SLICE_X148Y105       FDRE (Hold_fdre_C_D)         0.076    -0.591    audio_inout/D_L_O_int_reg[18]
   -------------------------------------------------------------------
-                         required time                          0.553    
-                         arrival time                          -0.385    
+                         required time                          0.591    
+                         arrival time                          -0.472    
   -------------------------------------------------------------------
-                         slack                                  0.168    
+                         slack                                  0.118    
 
-Slack (MET) :             0.172ns  (arrival time - required time)
-  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][4]/C
+Slack (MET) :             0.133ns  (arrival time - required time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][3]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][3]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.232ns  (logic 0.164ns (70.680%)  route 0.068ns (29.320%))
+  Data Path Delay:        0.208ns  (logic 0.141ns (67.788%)  route 0.067ns (32.212%))
   Logic Levels:           0  
   Clock Path Skew:        0.000ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.923ns
-    Source Clock Delay      (SCD):    -0.681ns
+    Destination Clock Delay (DCD):    -0.921ns
+    Source Clock Delay      (SCD):    -0.679ns
     Clock Pessimism Removal (CPR):    -0.242ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
@@ -1403,12 +1339,12 @@ Slack (MET) :             0.172ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.619    -0.681    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X148Y107       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][4]/C
+                         net (fo=773, routed)         0.621    -0.679    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X147Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][3]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X148Y107       FDCE (Prop_fdce_C_Q)         0.164    -0.517 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][4]/Q
-                         net (fo=2, routed)           0.068    -0.449    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[4]
-    SLICE_X148Y107       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]/D
+    SLICE_X147Y100       FDCE (Prop_fdce_C_Q)         0.141    -0.538 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][3]/Q
+                         net (fo=2, routed)           0.067    -0.471    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[3]
+    SLICE_X147Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][3]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1421,29 +1357,29 @@ Slack (MET) :             0.172ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.891    -0.923    leftFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X148Y107       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]/C
-                         clock pessimism              0.242    -0.681    
-    SLICE_X148Y107       FDCE (Hold_fdce_C_D)         0.060    -0.621    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][4]
+                         net (fo=773, routed)         0.893    -0.921    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X147Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][3]/C
+                         clock pessimism              0.242    -0.679    
+    SLICE_X147Y100       FDCE (Hold_fdce_C_D)         0.075    -0.604    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][3]
   -------------------------------------------------------------------
-                         required time                          0.621    
-                         arrival time                          -0.449    
+                         required time                          0.604    
+                         arrival time                          -0.471    
   -------------------------------------------------------------------
-                         slack                                  0.172    
+                         slack                                  0.133    
 
-Slack (MET) :             0.172ns  (arrival time - required time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][11]/C
+Slack (MET) :             0.133ns  (arrival time - required time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][7]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.232ns  (logic 0.164ns (70.680%)  route 0.068ns (29.320%))
+  Data Path Delay:        0.208ns  (logic 0.141ns (67.788%)  route 0.067ns (32.212%))
   Logic Levels:           0  
   Clock Path Skew:        0.000ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.921ns
-    Source Clock Delay      (SCD):    -0.679ns
+    Destination Clock Delay (DCD):    -0.924ns
+    Source Clock Delay      (SCD):    -0.682ns
     Clock Pessimism Removal (CPR):    -0.242ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
@@ -1458,12 +1394,12 @@ Slack (MET) :             0.172ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.621    -0.679    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][11]/C
+                         net (fo=773, routed)         0.618    -0.682    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X141Y104       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X154Y104       FDCE (Prop_fdce_C_Q)         0.164    -0.515 r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][11]/Q
-                         net (fo=2, routed)           0.068    -0.447    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[11]
-    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]/D
+    SLICE_X141Y104       FDCE (Prop_fdce_C_Q)         0.141    -0.541 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/Q
+                         net (fo=2, routed)           0.067    -0.474    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[7]
+    SLICE_X141Y104       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][7]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1476,30 +1412,30 @@ Slack (MET) :             0.172ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.893    -0.921    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X154Y104       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]/C
-                         clock pessimism              0.242    -0.679    
-    SLICE_X154Y104       FDCE (Hold_fdce_C_D)         0.060    -0.619    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][11]
+                         net (fo=773, routed)         0.890    -0.924    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X141Y104       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][7]/C
+                         clock pessimism              0.242    -0.682    
+    SLICE_X141Y104       FDCE (Hold_fdce_C_D)         0.075    -0.607    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][7]
   -------------------------------------------------------------------
-                         required time                          0.619    
-                         arrival time                          -0.447    
+                         required time                          0.607    
+                         arrival time                          -0.474    
   -------------------------------------------------------------------
-                         slack                                  0.172    
+                         slack                                  0.133    
 
-Slack (MET) :             0.173ns  (arrival time - required time)
-  Source:                 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+Slack (MET) :             0.134ns  (arrival time - required time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]/C
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][0]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.265ns  (logic 0.141ns (53.133%)  route 0.124ns (46.867%))
+  Data Path Delay:        0.209ns  (logic 0.141ns (67.433%)  route 0.068ns (32.567%))
   Logic Levels:           0  
-  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.921ns
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.922ns
     Source Clock Delay      (SCD):    -0.680ns
-    Clock Pessimism Removal (CPR):    -0.258ns
+    Clock Pessimism Removal (CPR):    -0.242ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1513,12 +1449,12 @@ Slack (MET) :             0.173ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.620    -0.680    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X155Y107       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/C
+                         net (fo=773, routed)         0.620    -0.680    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X149Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X155Y107       FDCE (Prop_fdce_C_Q)         0.141    -0.539 r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][14]/Q
-                         net (fo=2, routed)           0.124    -0.414    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[14]
-    SLICE_X154Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/D
+    SLICE_X149Y103       FDCE (Prop_fdce_C_Q)         0.141    -0.539 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][0]/Q
+                         net (fo=2, routed)           0.068    -0.471    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_1[0]
+    SLICE_X149Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][0]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1531,30 +1467,30 @@ Slack (MET) :             0.173ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.893    -0.921    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X154Y106       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]/C
-                         clock pessimism              0.258    -0.663    
-    SLICE_X154Y106       FDCE (Hold_fdce_C_D)         0.075    -0.588    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][14]
+                         net (fo=773, routed)         0.892    -0.922    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X149Y103       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][0]/C
+                         clock pessimism              0.242    -0.680    
+    SLICE_X149Y103       FDCE (Hold_fdce_C_D)         0.075    -0.605    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][0]
   -------------------------------------------------------------------
-                         required time                          0.588    
-                         arrival time                          -0.414    
+                         required time                          0.605    
+                         arrival time                          -0.471    
   -------------------------------------------------------------------
-                         slack                                  0.173    
+                         slack                                  0.134    
 
-Slack (MET) :             0.175ns  (arrival time - required time)
-  Source:                 audio_inout/D_R_O_int_reg[15]/C
-                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
-  Destination:            rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/D
+Slack (MET) :             0.142ns  (arrival time - required time)
+  Source:                 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]/C
+                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][3]/D
                             (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@5.000ns period=10.000ns})
   Path Group:             clk_out1_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.305ns  (logic 0.186ns (60.913%)  route 0.119ns (39.087%))
-  Logic Levels:           1  (LUT2=1)
-  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
+  Data Path Delay:        0.405ns  (logic 0.164ns (40.485%)  route 0.241ns (59.515%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.200ns (DCD - SCD - CPR)
     Destination Clock Delay (DCD):    -0.921ns
-    Source Clock Delay      (SCD):    -0.679ns
-    Clock Pessimism Removal (CPR):    -0.280ns
+    Source Clock Delay      (SCD):    -0.612ns
+    Clock Pessimism Removal (CPR):    -0.509ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -1568,14 +1504,12 @@ Slack (MET) :             0.175ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.621    -0.679    audio_inout/clk_out1
-    SLICE_X153Y106       FDRE                                         r  audio_inout/D_R_O_int_reg[15]/C
+                         net (fo=773, routed)         0.687    -0.612    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X146Y99        FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X153Y106       FDRE (Prop_fdre_C_Q)         0.141    -0.538 r  audio_inout/D_R_O_int_reg[15]/Q
-                         net (fo=2, routed)           0.119    -0.418    audio_inout/D_R_O_int_reg[22]_0[3]
-    SLICE_X155Y105       LUT2 (Prop_lut2_I0_O)        0.045    -0.373 r  audio_inout/I_inputSample_IBUF[7]_inst_i_1/O
-                         net (fo=1, routed)           0.000    -0.373    rightFir/firUnit_1/operativeUnit_1/I_inputSample[7]
-    SLICE_X155Y105       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/D
+    SLICE_X146Y99        FDCE (Prop_fdce_C_Q)         0.164    -0.448 r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]/Q
+                         net (fo=2, routed)           0.241    -0.207    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14]_15[3]
+    SLICE_X146Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][3]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out1_clk_wiz_0 rise edge)
@@ -1588,15 +1522,15 @@ Slack (MET) :             0.175ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT0
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out1_clk_wiz_0
     BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout1_buf/O
-                         net (fo=773, routed)         0.893    -0.921    rightFir/firUnit_1/operativeUnit_1/clk_out1
-    SLICE_X155Y105       FDCE                                         r  rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]/C
-                         clock pessimism              0.280    -0.641    
-    SLICE_X155Y105       FDCE (Hold_fdce_C_D)         0.092    -0.549    rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][7]
+                         net (fo=773, routed)         0.893    -0.921    leftFir/firUnit_1/operativeUnit_1/clk_out1
+    SLICE_X146Y100       FDCE                                         r  leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][3]/C
+                         clock pessimism              0.509    -0.412    
+    SLICE_X146Y100       FDCE (Hold_fdce_C_D)         0.063    -0.349    leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][3]
   -------------------------------------------------------------------
-                         required time                          0.549    
-                         arrival time                          -0.373    
+                         required time                          0.349    
+                         arrival time                          -0.207    
   -------------------------------------------------------------------
-                         slack                                  0.175    
+                         slack                                  0.142    
 
 
 
@@ -1612,35 +1546,35 @@ Sources:            { clk_1/inst/mmcm_adv_inst/CLKOUT0 }
 Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
 Min Period        n/a     BUFG/I              n/a            2.155         10.000      7.845      BUFGCTRL_X0Y1    clk_1/inst/clkout1_buf/I
 Min Period        n/a     MMCME2_ADV/CLKOUT0  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  clk_1/inst/mmcm_adv_inst/CLKOUT0
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X151Y112   lrclkD1_reg/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X151Y112   lrclkD2_reg/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y111   lrclkcnt_reg[0]/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y111   lrclkcnt_reg[1]/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X151Y111   lrclkcnt_reg[2]/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X151Y111   lrclkcnt_reg[3]/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X151Y112   pulse48kHz_reg/C
-Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X152Y115   audio_inout/BCLK_int_reg/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y99    lrclkD1_reg/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y99    lrclkD2_reg/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X149Y98    lrclkcnt_reg[0]/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X149Y98    lrclkcnt_reg[1]/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y98    lrclkcnt_reg[2]/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y98    lrclkcnt_reg[3]/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X150Y99    pulse48kHz_reg/C
+Min Period        n/a     FDRE/C              n/a            1.000         10.000      9.000      SLICE_X157Y108   audio_inout/BCLK_int_reg/C
 Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       10.000      203.360    MMCME2_ADV_X1Y2  clk_1/inst/mmcm_adv_inst/CLKOUT0
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD1_reg/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD1_reg/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD2_reg/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD2_reg/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[0]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[0]/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[1]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[1]/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y111   lrclkcnt_reg[2]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y111   lrclkcnt_reg[2]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD1_reg/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD1_reg/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD2_reg/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y112   lrclkD2_reg/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[0]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[0]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[1]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y111   lrclkcnt_reg[1]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y111   lrclkcnt_reg[2]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X151Y111   lrclkcnt_reg[2]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD1_reg/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD1_reg/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD2_reg/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD2_reg/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[0]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[0]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[1]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[1]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y98    lrclkcnt_reg[2]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y98    lrclkcnt_reg[2]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD1_reg/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD1_reg/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD2_reg/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y99    lrclkD2_reg/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[0]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[0]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[1]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X149Y98    lrclkcnt_reg[1]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y98    lrclkcnt_reg[2]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         5.000       4.500      SLICE_X150Y98    lrclkcnt_reg[2]/C
 
 
 
@@ -1672,27 +1606,27 @@ Max Period  n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       83.333
 From Clock:  clk_out4_clk_wiz_0
   To Clock:  clk_out4_clk_wiz_0
 
-Setup :            0  Failing Endpoints,  Worst Slack       14.589ns,  Total Violation        0.000ns
-Hold  :            0  Failing Endpoints,  Worst Slack        0.109ns,  Total Violation        0.000ns
+Setup :            0  Failing Endpoints,  Worst Slack       14.586ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.155ns,  Total Violation        0.000ns
 PW    :            0  Failing Endpoints,  Worst Slack        9.500ns,  Total Violation        0.000ns
 ---------------------------------------------------------------------------------------------------
 
 
 Max Delay Paths
 --------------------------------------------------------------------------------------
-Slack (MET) :             14.589ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
+Slack (MET) :             14.586ns  (required time - arrival time)
+  Source:                 initialize_audio/twi_controller/dScl_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        5.080ns  (logic 1.151ns (22.659%)  route 3.929ns (77.341%))
-  Logic Levels:           4  (LUT2=1 LUT4=1 LUT6=2)
-  Clock Path Skew:        -0.032ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.588ns = ( 18.412 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        5.109ns  (logic 1.250ns (24.467%)  route 3.859ns (75.533%))
+  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.596ns = ( 18.404 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.001ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -1711,20 +1645,20 @@ Slack (MET) :             14.589ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          0.782     2.285    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X159Y117       LUT4 (Prop_lut4_I3_O)        0.120     2.405 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
-                         net (fo=1, routed)           0.812     3.217    initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
-    SLICE_X159Y118       LUT6 (Prop_lut6_I0_O)        0.327     3.544 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
-                         net (fo=4, routed)           0.533     4.077    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
-    SLICE_X159Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
+                         net (fo=120, routed)         1.818    -1.001    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y121       FDRE                                         r  initialize_audio/twi_controller/dScl_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X162Y121       FDRE (Prop_fdre_C_Q)         0.518    -0.483 r  initialize_audio/twi_controller/dScl_reg/Q
+                         net (fo=6, routed)           1.271     0.788    initialize_audio/twi_controller/dScl
+    SLICE_X160Y122       LUT3 (Prop_lut3_I0_O)        0.152     0.940 f  initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+                         net (fo=6, routed)           0.592     1.533    initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+    SLICE_X160Y123       LUT5 (Prop_lut5_I4_O)        0.332     1.865 r  initialize_audio/twi_controller/ERR_O_i_2/O
+                         net (fo=3, routed)           0.498     2.363    initialize_audio/twi_controller/ERR_O_i_2_n_0
+    SLICE_X160Y121       LUT6 (Prop_lut6_I0_O)        0.124     2.487 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+                         net (fo=1, routed)           0.956     3.443    initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+    SLICE_X159Y124       LUT6 (Prop_lut6_I1_O)        0.124     3.567 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+                         net (fo=4, routed)           0.541     4.108    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+    SLICE_X158Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -1737,30 +1671,30 @@ Slack (MET) :             14.589ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.704    18.412    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
-                         clock pessimism              0.554    18.965    
-                         clock uncertainty           -0.094    18.871    
-    SLICE_X159Y116       FDRE (Setup_fdre_C_CE)      -0.205    18.666    initialize_audio/twi_controller/FSM_gray_state_reg[1]
+                         net (fo=120, routed)         1.696    18.404    initialize_audio/twi_controller/clk_out4
+    SLICE_X158Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[2]/C
+                         clock pessimism              0.554    18.957    
+                         clock uncertainty           -0.094    18.863    
+    SLICE_X158Y123       FDRE (Setup_fdre_C_CE)      -0.169    18.694    initialize_audio/twi_controller/FSM_gray_state_reg[2]
   -------------------------------------------------------------------
-                         required time                         18.666    
-                         arrival time                          -4.077    
+                         required time                         18.694    
+                         arrival time                          -4.108    
   -------------------------------------------------------------------
-                         slack                                 14.589    
+                         slack                                 14.586    
 
-Slack (MET) :             14.589ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) :             14.586ns  (required time - arrival time)
+  Source:                 initialize_audio/twi_controller/dScl_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        5.080ns  (logic 1.151ns (22.659%)  route 3.929ns (77.341%))
-  Logic Levels:           4  (LUT2=1 LUT4=1 LUT6=2)
-  Clock Path Skew:        -0.032ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.588ns = ( 18.412 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        5.109ns  (logic 1.250ns (24.467%)  route 3.859ns (75.533%))
+  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.596ns = ( 18.404 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.001ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -1779,20 +1713,20 @@ Slack (MET) :             14.589ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          0.782     2.285    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X159Y117       LUT4 (Prop_lut4_I3_O)        0.120     2.405 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
-                         net (fo=1, routed)           0.812     3.217    initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
-    SLICE_X159Y118       LUT6 (Prop_lut6_I0_O)        0.327     3.544 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
-                         net (fo=4, routed)           0.533     4.077    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
-    SLICE_X159Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
+                         net (fo=120, routed)         1.818    -1.001    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y121       FDRE                                         r  initialize_audio/twi_controller/dScl_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X162Y121       FDRE (Prop_fdre_C_Q)         0.518    -0.483 r  initialize_audio/twi_controller/dScl_reg/Q
+                         net (fo=6, routed)           1.271     0.788    initialize_audio/twi_controller/dScl
+    SLICE_X160Y122       LUT3 (Prop_lut3_I0_O)        0.152     0.940 f  initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+                         net (fo=6, routed)           0.592     1.533    initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+    SLICE_X160Y123       LUT5 (Prop_lut5_I4_O)        0.332     1.865 r  initialize_audio/twi_controller/ERR_O_i_2/O
+                         net (fo=3, routed)           0.498     2.363    initialize_audio/twi_controller/ERR_O_i_2_n_0
+    SLICE_X160Y121       LUT6 (Prop_lut6_I0_O)        0.124     2.487 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+                         net (fo=1, routed)           0.956     3.443    initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+    SLICE_X159Y124       LUT6 (Prop_lut6_I1_O)        0.124     3.567 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+                         net (fo=4, routed)           0.541     4.108    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+    SLICE_X158Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -1805,30 +1739,30 @@ Slack (MET) :             14.589ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.704    18.412    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[3]/C
-                         clock pessimism              0.554    18.965    
-                         clock uncertainty           -0.094    18.871    
-    SLICE_X159Y116       FDRE (Setup_fdre_C_CE)      -0.205    18.666    initialize_audio/twi_controller/FSM_gray_state_reg[3]
+                         net (fo=120, routed)         1.696    18.404    initialize_audio/twi_controller/clk_out4
+    SLICE_X158Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[3]/C
+                         clock pessimism              0.554    18.957    
+                         clock uncertainty           -0.094    18.863    
+    SLICE_X158Y123       FDRE (Setup_fdre_C_CE)      -0.169    18.694    initialize_audio/twi_controller/FSM_gray_state_reg[3]
   -------------------------------------------------------------------
-                         required time                         18.666    
-                         arrival time                          -4.077    
+                         required time                         18.694    
+                         arrival time                          -4.108    
   -------------------------------------------------------------------
-                         slack                                 14.589    
+                         slack                                 14.586    
 
-Slack (MET) :             14.619ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) :             14.748ns  (required time - arrival time)
+  Source:                 initialize_audio/twi_controller/dScl_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        5.052ns  (logic 1.151ns (22.783%)  route 3.901ns (77.217%))
-  Logic Levels:           4  (LUT2=1 LUT4=1 LUT6=2)
-  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.586ns = ( 18.414 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        4.911ns  (logic 1.250ns (25.455%)  route 3.661ns (74.545%))
+  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.596ns = ( 18.404 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.001ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -1847,20 +1781,20 @@ Slack (MET) :             14.619ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          0.782     2.285    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X159Y117       LUT4 (Prop_lut4_I3_O)        0.120     2.405 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
-                         net (fo=1, routed)           0.812     3.217    initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
-    SLICE_X159Y118       LUT6 (Prop_lut6_I0_O)        0.327     3.544 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
-                         net (fo=4, routed)           0.506     4.049    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
-    SLICE_X160Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
+                         net (fo=120, routed)         1.818    -1.001    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y121       FDRE                                         r  initialize_audio/twi_controller/dScl_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X162Y121       FDRE (Prop_fdre_C_Q)         0.518    -0.483 r  initialize_audio/twi_controller/dScl_reg/Q
+                         net (fo=6, routed)           1.271     0.788    initialize_audio/twi_controller/dScl
+    SLICE_X160Y122       LUT3 (Prop_lut3_I0_O)        0.152     0.940 f  initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+                         net (fo=6, routed)           0.592     1.533    initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+    SLICE_X160Y123       LUT5 (Prop_lut5_I4_O)        0.332     1.865 r  initialize_audio/twi_controller/ERR_O_i_2/O
+                         net (fo=3, routed)           0.498     2.363    initialize_audio/twi_controller/ERR_O_i_2_n_0
+    SLICE_X160Y121       LUT6 (Prop_lut6_I0_O)        0.124     2.487 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+                         net (fo=1, routed)           0.956     3.443    initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+    SLICE_X159Y124       LUT6 (Prop_lut6_I1_O)        0.124     3.567 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+                         net (fo=4, routed)           0.343     3.910    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+    SLICE_X159Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[0]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -1873,30 +1807,30 @@ Slack (MET) :             14.619ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.706    18.414    initialize_audio/twi_controller/clk_out4
-    SLICE_X160Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
-                         clock pessimism              0.554    18.967    
-                         clock uncertainty           -0.094    18.873    
-    SLICE_X160Y116       FDRE (Setup_fdre_C_CE)      -0.205    18.668    initialize_audio/twi_controller/FSM_gray_state_reg[0]
+                         net (fo=120, routed)         1.696    18.404    initialize_audio/twi_controller/clk_out4
+    SLICE_X159Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+                         clock pessimism              0.554    18.957    
+                         clock uncertainty           -0.094    18.863    
+    SLICE_X159Y123       FDRE (Setup_fdre_C_CE)      -0.205    18.658    initialize_audio/twi_controller/FSM_gray_state_reg[0]
   -------------------------------------------------------------------
-                         required time                         18.668    
-                         arrival time                          -4.049    
+                         required time                         18.658    
+                         arrival time                          -3.910    
   -------------------------------------------------------------------
-                         slack                                 14.619    
+                         slack                                 14.748    
 
-Slack (MET) :             14.619ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
+Slack (MET) :             14.748ns  (required time - arrival time)
+  Source:                 initialize_audio/twi_controller/dScl_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        5.052ns  (logic 1.151ns (22.783%)  route 3.901ns (77.217%))
-  Logic Levels:           4  (LUT2=1 LUT4=1 LUT6=2)
-  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.586ns = ( 18.414 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        4.911ns  (logic 1.250ns (25.455%)  route 3.661ns (74.545%))
+  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.596ns = ( 18.404 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.001ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -1915,20 +1849,20 @@ Slack (MET) :             14.619ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          0.782     2.285    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X159Y117       LUT4 (Prop_lut4_I3_O)        0.120     2.405 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_3/O
-                         net (fo=1, routed)           0.812     3.217    initialize_audio/twi_controller/FSM_gray_state[3]_i_3_n_0
-    SLICE_X159Y118       LUT6 (Prop_lut6_I0_O)        0.327     3.544 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
-                         net (fo=4, routed)           0.506     4.049    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
-    SLICE_X160Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
+                         net (fo=120, routed)         1.818    -1.001    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y121       FDRE                                         r  initialize_audio/twi_controller/dScl_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X162Y121       FDRE (Prop_fdre_C_Q)         0.518    -0.483 r  initialize_audio/twi_controller/dScl_reg/Q
+                         net (fo=6, routed)           1.271     0.788    initialize_audio/twi_controller/dScl
+    SLICE_X160Y122       LUT3 (Prop_lut3_I0_O)        0.152     0.940 f  initialize_audio/twi_controller/FSM_gray_state[3]_i_9/O
+                         net (fo=6, routed)           0.592     1.533    initialize_audio/twi_controller/FSM_gray_state[3]_i_9_n_0
+    SLICE_X160Y123       LUT5 (Prop_lut5_I4_O)        0.332     1.865 r  initialize_audio/twi_controller/ERR_O_i_2/O
+                         net (fo=3, routed)           0.498     2.363    initialize_audio/twi_controller/ERR_O_i_2_n_0
+    SLICE_X160Y121       LUT6 (Prop_lut6_I0_O)        0.124     2.487 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+                         net (fo=1, routed)           0.956     3.443    initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+    SLICE_X159Y124       LUT6 (Prop_lut6_I1_O)        0.124     3.567 r  initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+                         net (fo=4, routed)           0.343     3.910    initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+    SLICE_X159Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -1941,30 +1875,30 @@ Slack (MET) :             14.619ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.706    18.414    initialize_audio/twi_controller/clk_out4
-    SLICE_X160Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[2]/C
-                         clock pessimism              0.554    18.967    
-                         clock uncertainty           -0.094    18.873    
-    SLICE_X160Y116       FDRE (Setup_fdre_C_CE)      -0.205    18.668    initialize_audio/twi_controller/FSM_gray_state_reg[2]
+                         net (fo=120, routed)         1.696    18.404    initialize_audio/twi_controller/clk_out4
+    SLICE_X159Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
+                         clock pessimism              0.554    18.957    
+                         clock uncertainty           -0.094    18.863    
+    SLICE_X159Y123       FDRE (Setup_fdre_C_CE)      -0.205    18.658    initialize_audio/twi_controller/FSM_gray_state_reg[1]
   -------------------------------------------------------------------
-                         required time                         18.668    
-                         arrival time                          -4.049    
+                         required time                         18.658    
+                         arrival time                          -3.910    
   -------------------------------------------------------------------
-                         slack                                 14.619    
+                         slack                                 14.748    
 
-Slack (MET) :             14.696ns  (required time - arrival time)
-  Source:                 initialize_audio/delaycnt_reg[4]/C
-                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/state_reg[1]/CE
+Slack (MET) :             14.817ns  (required time - arrival time)
+  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
                             (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/dataByte_reg[7]/CE
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        4.965ns  (logic 0.952ns (19.176%)  route 4.013ns (80.824%))
-  Logic Levels:           4  (LUT4=2 LUT5=1 LUT6=1)
-  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.584ns = ( 18.416 - 20.000 ) 
-    Source Clock Delay      (SCD):    -0.991ns
+  Data Path Delay:        4.853ns  (logic 1.014ns (20.896%)  route 3.839ns (79.104%))
+  Logic Levels:           4  (LUT2=2 LUT6=2)
+  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.591ns = ( 18.409 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.007ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -1983,20 +1917,20 @@ Slack (MET) :             14.696ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.828    -0.991    initialize_audio/clk_out4
-    SLICE_X156Y109       FDRE                                         r  initialize_audio/delaycnt_reg[4]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y109       FDRE (Prop_fdre_C_Q)         0.456    -0.535 f  initialize_audio/delaycnt_reg[4]/Q
-                         net (fo=3, routed)           0.833     0.298    initialize_audio/delaycnt_reg_n_0_[4]
-    SLICE_X157Y110       LUT4 (Prop_lut4_I0_O)        0.124     0.422 f  initialize_audio/initA[6]_i_13/O
-                         net (fo=1, routed)           0.877     1.299    initialize_audio/initA[6]_i_13_n_0
-    SLICE_X157Y110       LUT5 (Prop_lut5_I4_O)        0.124     1.423 r  initialize_audio/initA[6]_i_9/O
-                         net (fo=1, routed)           0.781     2.204    initialize_audio/initA[6]_i_9_n_0
-    SLICE_X157Y113       LUT4 (Prop_lut4_I1_O)        0.124     2.328 r  initialize_audio/initA[6]_i_4/O
-                         net (fo=4, routed)           0.805     3.133    initialize_audio/twi_controller/initEn_reg
-    SLICE_X158Y113       LUT6 (Prop_lut6_I1_O)        0.124     3.257 r  initialize_audio/twi_controller/state[3]_i_1/O
-                         net (fo=4, routed)           0.717     3.974    initialize_audio/twi_controller_n_6
-    SLICE_X160Y113       FDSE                                         r  initialize_audio/state_reg[1]/CE
+                         net (fo=120, routed)         1.812    -1.007    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y125       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X162Y125       FDSE (Prop_fdse_C_Q)         0.518    -0.489 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
+                         net (fo=7, routed)           0.820     0.331    initialize_audio/twi_controller/sclCnt[0]
+    SLICE_X160Y125       LUT6 (Prop_lut6_I2_O)        0.124     0.455 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
+                         net (fo=2, routed)           0.506     0.961    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
+    SLICE_X161Y125       LUT2 (Prop_lut2_I1_O)        0.124     1.085 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
+                         net (fo=13, routed)          1.021     2.106    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+    SLICE_X160Y122       LUT6 (Prop_lut6_I3_O)        0.124     2.230 r  initialize_audio/twi_controller/dataByte[7]_i_3/O
+                         net (fo=4, routed)           0.877     3.107    initialize_audio/twi_controller/dataByte0
+    SLICE_X161Y121       LUT2 (Prop_lut2_I0_O)        0.124     3.231 r  initialize_audio/twi_controller/dataByte[7]_i_1/O
+                         net (fo=8, routed)           0.614     3.846    initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+    SLICE_X161Y121       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[7]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2009,30 +1943,30 @@ Slack (MET) :             14.696ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.708    18.416    initialize_audio/clk_out4
-    SLICE_X160Y113       FDSE                                         r  initialize_audio/state_reg[1]/C
-                         clock pessimism              0.554    18.969    
-                         clock uncertainty           -0.094    18.875    
-    SLICE_X160Y113       FDSE (Setup_fdse_C_CE)      -0.205    18.670    initialize_audio/state_reg[1]
+                         net (fo=120, routed)         1.701    18.409    initialize_audio/twi_controller/clk_out4
+    SLICE_X161Y121       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[7]/C
+                         clock pessimism              0.554    18.962    
+                         clock uncertainty           -0.094    18.868    
+    SLICE_X161Y121       FDRE (Setup_fdre_C_CE)      -0.205    18.663    initialize_audio/twi_controller/dataByte_reg[7]
   -------------------------------------------------------------------
-                         required time                         18.670    
-                         arrival time                          -3.974    
+                         required time                         18.663    
+                         arrival time                          -3.846    
   -------------------------------------------------------------------
-                         slack                                 14.696    
+                         slack                                 14.817    
 
-Slack (MET) :             14.712ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/dataByte_reg[1]/CE
+Slack (MET) :             14.883ns  (required time - arrival time)
+  Source:                 initialize_audio/delaycnt_reg[28]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/initA_reg[0]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        4.960ns  (logic 0.952ns (19.193%)  route 4.008ns (80.807%))
-  Logic Levels:           4  (LUT2=2 LUT6=2)
-  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.585ns = ( 18.415 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        4.791ns  (logic 0.952ns (19.872%)  route 3.839ns (80.128%))
+  Logic Levels:           4  (LUT4=2 LUT5=2)
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.587ns = ( 18.413 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.007ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -2051,20 +1985,20 @@ Slack (MET) :             14.712ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          1.002     2.505    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X158Y117       LUT6 (Prop_lut6_I3_O)        0.124     2.629 r  initialize_audio/twi_controller/dataByte[7]_i_3/O
-                         net (fo=4, routed)           0.478     3.107    initialize_audio/twi_controller/dataByte0
-    SLICE_X158Y117       LUT2 (Prop_lut2_I0_O)        0.124     3.231 r  initialize_audio/twi_controller/dataByte[7]_i_1/O
-                         net (fo=8, routed)           0.727     3.957    initialize_audio/twi_controller/dataByte[7]_i_1_n_0
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[1]/CE
+                         net (fo=120, routed)         1.812    -1.007    initialize_audio/clk_out4
+    SLICE_X157Y123       FDRE                                         r  initialize_audio/delaycnt_reg[28]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X157Y123       FDRE (Prop_fdre_C_Q)         0.456    -0.551 f  initialize_audio/delaycnt_reg[28]/Q
+                         net (fo=3, routed)           0.961     0.410    initialize_audio/delaycnt_reg_n_0_[28]
+    SLICE_X156Y122       LUT4 (Prop_lut4_I0_O)        0.124     0.534 f  initialize_audio/initA[6]_i_15/O
+                         net (fo=1, routed)           0.646     1.180    initialize_audio/initA[6]_i_15_n_0
+    SLICE_X156Y121       LUT5 (Prop_lut5_I4_O)        0.124     1.304 f  initialize_audio/initA[6]_i_11/O
+                         net (fo=1, routed)           0.574     1.879    initialize_audio/initA[6]_i_11_n_0
+    SLICE_X156Y120       LUT4 (Prop_lut4_I3_O)        0.124     2.003 r  initialize_audio/initA[6]_i_4/O
+                         net (fo=4, routed)           0.839     2.842    initialize_audio/twi_controller/initEn_reg
+    SLICE_X158Y119       LUT5 (Prop_lut5_I1_O)        0.124     2.966 r  initialize_audio/twi_controller/initA[6]_i_2/O
+                         net (fo=7, routed)           0.818     3.784    initialize_audio/twi_controller_n_8
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[0]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2077,30 +2011,30 @@ Slack (MET) :             14.712ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.707    18.415    initialize_audio/twi_controller/clk_out4
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[1]/C
-                         clock pessimism              0.554    18.968    
-                         clock uncertainty           -0.094    18.874    
-    SLICE_X161Y115       FDRE (Setup_fdre_C_CE)      -0.205    18.669    initialize_audio/twi_controller/dataByte_reg[1]
+                         net (fo=120, routed)         1.705    18.413    initialize_audio/clk_out4
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[0]/C
+                         clock pessimism              0.554    18.966    
+                         clock uncertainty           -0.094    18.872    
+    SLICE_X161Y117       FDRE (Setup_fdre_C_CE)      -0.205    18.667    initialize_audio/initA_reg[0]
   -------------------------------------------------------------------
-                         required time                         18.669    
-                         arrival time                          -3.957    
+                         required time                         18.667    
+                         arrival time                          -3.784    
   -------------------------------------------------------------------
-                         slack                                 14.712    
+                         slack                                 14.883    
 
-Slack (MET) :             14.712ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/dataByte_reg[6]/CE
+Slack (MET) :             14.883ns  (required time - arrival time)
+  Source:                 initialize_audio/delaycnt_reg[28]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/initA_reg[2]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        4.960ns  (logic 0.952ns (19.193%)  route 4.008ns (80.807%))
-  Logic Levels:           4  (LUT2=2 LUT6=2)
-  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.585ns = ( 18.415 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        4.791ns  (logic 0.952ns (19.872%)  route 3.839ns (80.128%))
+  Logic Levels:           4  (LUT4=2 LUT5=2)
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.587ns = ( 18.413 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.007ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -2119,20 +2053,20 @@ Slack (MET) :             14.712ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          1.002     2.505    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X158Y117       LUT6 (Prop_lut6_I3_O)        0.124     2.629 r  initialize_audio/twi_controller/dataByte[7]_i_3/O
-                         net (fo=4, routed)           0.478     3.107    initialize_audio/twi_controller/dataByte0
-    SLICE_X158Y117       LUT2 (Prop_lut2_I0_O)        0.124     3.231 r  initialize_audio/twi_controller/dataByte[7]_i_1/O
-                         net (fo=8, routed)           0.727     3.957    initialize_audio/twi_controller/dataByte[7]_i_1_n_0
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[6]/CE
+                         net (fo=120, routed)         1.812    -1.007    initialize_audio/clk_out4
+    SLICE_X157Y123       FDRE                                         r  initialize_audio/delaycnt_reg[28]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X157Y123       FDRE (Prop_fdre_C_Q)         0.456    -0.551 f  initialize_audio/delaycnt_reg[28]/Q
+                         net (fo=3, routed)           0.961     0.410    initialize_audio/delaycnt_reg_n_0_[28]
+    SLICE_X156Y122       LUT4 (Prop_lut4_I0_O)        0.124     0.534 f  initialize_audio/initA[6]_i_15/O
+                         net (fo=1, routed)           0.646     1.180    initialize_audio/initA[6]_i_15_n_0
+    SLICE_X156Y121       LUT5 (Prop_lut5_I4_O)        0.124     1.304 f  initialize_audio/initA[6]_i_11/O
+                         net (fo=1, routed)           0.574     1.879    initialize_audio/initA[6]_i_11_n_0
+    SLICE_X156Y120       LUT4 (Prop_lut4_I3_O)        0.124     2.003 r  initialize_audio/initA[6]_i_4/O
+                         net (fo=4, routed)           0.839     2.842    initialize_audio/twi_controller/initEn_reg
+    SLICE_X158Y119       LUT5 (Prop_lut5_I1_O)        0.124     2.966 r  initialize_audio/twi_controller/initA[6]_i_2/O
+                         net (fo=7, routed)           0.818     3.784    initialize_audio/twi_controller_n_8
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[2]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2145,30 +2079,30 @@ Slack (MET) :             14.712ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.707    18.415    initialize_audio/twi_controller/clk_out4
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[6]/C
-                         clock pessimism              0.554    18.968    
-                         clock uncertainty           -0.094    18.874    
-    SLICE_X161Y115       FDRE (Setup_fdre_C_CE)      -0.205    18.669    initialize_audio/twi_controller/dataByte_reg[6]
+                         net (fo=120, routed)         1.705    18.413    initialize_audio/clk_out4
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[2]/C
+                         clock pessimism              0.554    18.966    
+                         clock uncertainty           -0.094    18.872    
+    SLICE_X161Y117       FDRE (Setup_fdre_C_CE)      -0.205    18.667    initialize_audio/initA_reg[2]
   -------------------------------------------------------------------
-                         required time                         18.669    
-                         arrival time                          -3.957    
+                         required time                         18.667    
+                         arrival time                          -3.784    
   -------------------------------------------------------------------
-                         slack                                 14.712    
+                         slack                                 14.883    
 
-Slack (MET) :             14.712ns  (required time - arrival time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/dataByte_reg[7]/CE
+Slack (MET) :             14.883ns  (required time - arrival time)
+  Source:                 initialize_audio/delaycnt_reg[28]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/initA_reg[3]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        4.960ns  (logic 0.952ns (19.193%)  route 4.008ns (80.807%))
-  Logic Levels:           4  (LUT2=2 LUT6=2)
-  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.585ns = ( 18.415 - 20.000 ) 
-    Source Clock Delay      (SCD):    -1.003ns
+  Data Path Delay:        4.791ns  (logic 0.952ns (19.872%)  route 3.839ns (80.128%))
+  Logic Levels:           4  (LUT4=2 LUT5=2)
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.587ns = ( 18.413 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.007ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -2187,20 +2121,20 @@ Slack (MET) :             14.712ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.816    -1.003    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.456    -0.547 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
-                         net (fo=7, routed)           0.741     0.194    initialize_audio/twi_controller/sclCnt[0]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.124     0.318 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
-                         net (fo=2, routed)           1.061     1.379    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
-    SLICE_X158Y121       LUT2 (Prop_lut2_I1_O)        0.124     1.503 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
-                         net (fo=15, routed)          1.002     2.505    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
-    SLICE_X158Y117       LUT6 (Prop_lut6_I3_O)        0.124     2.629 r  initialize_audio/twi_controller/dataByte[7]_i_3/O
-                         net (fo=4, routed)           0.478     3.107    initialize_audio/twi_controller/dataByte0
-    SLICE_X158Y117       LUT2 (Prop_lut2_I0_O)        0.124     3.231 r  initialize_audio/twi_controller/dataByte[7]_i_1/O
-                         net (fo=8, routed)           0.727     3.957    initialize_audio/twi_controller/dataByte[7]_i_1_n_0
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[7]/CE
+                         net (fo=120, routed)         1.812    -1.007    initialize_audio/clk_out4
+    SLICE_X157Y123       FDRE                                         r  initialize_audio/delaycnt_reg[28]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X157Y123       FDRE (Prop_fdre_C_Q)         0.456    -0.551 f  initialize_audio/delaycnt_reg[28]/Q
+                         net (fo=3, routed)           0.961     0.410    initialize_audio/delaycnt_reg_n_0_[28]
+    SLICE_X156Y122       LUT4 (Prop_lut4_I0_O)        0.124     0.534 f  initialize_audio/initA[6]_i_15/O
+                         net (fo=1, routed)           0.646     1.180    initialize_audio/initA[6]_i_15_n_0
+    SLICE_X156Y121       LUT5 (Prop_lut5_I4_O)        0.124     1.304 f  initialize_audio/initA[6]_i_11/O
+                         net (fo=1, routed)           0.574     1.879    initialize_audio/initA[6]_i_11_n_0
+    SLICE_X156Y120       LUT4 (Prop_lut4_I3_O)        0.124     2.003 r  initialize_audio/initA[6]_i_4/O
+                         net (fo=4, routed)           0.839     2.842    initialize_audio/twi_controller/initEn_reg
+    SLICE_X158Y119       LUT5 (Prop_lut5_I1_O)        0.124     2.966 r  initialize_audio/twi_controller/initA[6]_i_2/O
+                         net (fo=7, routed)           0.818     3.784    initialize_audio/twi_controller_n_8
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[3]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2213,30 +2147,30 @@ Slack (MET) :             14.712ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.707    18.415    initialize_audio/twi_controller/clk_out4
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[7]/C
-                         clock pessimism              0.554    18.968    
-                         clock uncertainty           -0.094    18.874    
-    SLICE_X161Y115       FDRE (Setup_fdre_C_CE)      -0.205    18.669    initialize_audio/twi_controller/dataByte_reg[7]
+                         net (fo=120, routed)         1.705    18.413    initialize_audio/clk_out4
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[3]/C
+                         clock pessimism              0.554    18.966    
+                         clock uncertainty           -0.094    18.872    
+    SLICE_X161Y117       FDRE (Setup_fdre_C_CE)      -0.205    18.667    initialize_audio/initA_reg[3]
   -------------------------------------------------------------------
-                         required time                         18.669    
-                         arrival time                          -3.957    
+                         required time                         18.667    
+                         arrival time                          -3.784    
   -------------------------------------------------------------------
-                         slack                                 14.712    
+                         slack                                 14.883    
 
-Slack (MET) :             14.772ns  (required time - arrival time)
-  Source:                 initialize_audio/delaycnt_reg[4]/C
+Slack (MET) :             14.883ns  (required time - arrival time)
+  Source:                 initialize_audio/delaycnt_reg[28]/C
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/initA_reg[0]/CE
+  Destination:            initialize_audio/initA_reg[4]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        4.891ns  (logic 0.952ns (19.463%)  route 3.939ns (80.537%))
+  Data Path Delay:        4.791ns  (logic 0.952ns (19.872%)  route 3.839ns (80.128%))
   Logic Levels:           4  (LUT4=2 LUT5=2)
-  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.582ns = ( 18.418 - 20.000 ) 
-    Source Clock Delay      (SCD):    -0.991ns
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.587ns = ( 18.413 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.007ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -2255,20 +2189,20 @@ Slack (MET) :             14.772ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.828    -0.991    initialize_audio/clk_out4
-    SLICE_X156Y109       FDRE                                         r  initialize_audio/delaycnt_reg[4]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y109       FDRE (Prop_fdre_C_Q)         0.456    -0.535 f  initialize_audio/delaycnt_reg[4]/Q
-                         net (fo=3, routed)           0.833     0.298    initialize_audio/delaycnt_reg_n_0_[4]
-    SLICE_X157Y110       LUT4 (Prop_lut4_I0_O)        0.124     0.422 f  initialize_audio/initA[6]_i_13/O
-                         net (fo=1, routed)           0.877     1.299    initialize_audio/initA[6]_i_13_n_0
-    SLICE_X157Y110       LUT5 (Prop_lut5_I4_O)        0.124     1.423 r  initialize_audio/initA[6]_i_9/O
-                         net (fo=1, routed)           0.781     2.204    initialize_audio/initA[6]_i_9_n_0
-    SLICE_X157Y113       LUT4 (Prop_lut4_I1_O)        0.124     2.328 r  initialize_audio/initA[6]_i_4/O
-                         net (fo=4, routed)           0.822     3.150    initialize_audio/twi_controller/initEn_reg
-    SLICE_X158Y113       LUT5 (Prop_lut5_I1_O)        0.124     3.274 r  initialize_audio/twi_controller/initA[6]_i_2/O
-                         net (fo=7, routed)           0.627     3.900    initialize_audio/twi_controller_n_8
-    SLICE_X160Y111       FDRE                                         r  initialize_audio/initA_reg[0]/CE
+                         net (fo=120, routed)         1.812    -1.007    initialize_audio/clk_out4
+    SLICE_X157Y123       FDRE                                         r  initialize_audio/delaycnt_reg[28]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X157Y123       FDRE (Prop_fdre_C_Q)         0.456    -0.551 f  initialize_audio/delaycnt_reg[28]/Q
+                         net (fo=3, routed)           0.961     0.410    initialize_audio/delaycnt_reg_n_0_[28]
+    SLICE_X156Y122       LUT4 (Prop_lut4_I0_O)        0.124     0.534 f  initialize_audio/initA[6]_i_15/O
+                         net (fo=1, routed)           0.646     1.180    initialize_audio/initA[6]_i_15_n_0
+    SLICE_X156Y121       LUT5 (Prop_lut5_I4_O)        0.124     1.304 f  initialize_audio/initA[6]_i_11/O
+                         net (fo=1, routed)           0.574     1.879    initialize_audio/initA[6]_i_11_n_0
+    SLICE_X156Y120       LUT4 (Prop_lut4_I3_O)        0.124     2.003 r  initialize_audio/initA[6]_i_4/O
+                         net (fo=4, routed)           0.839     2.842    initialize_audio/twi_controller/initEn_reg
+    SLICE_X158Y119       LUT5 (Prop_lut5_I1_O)        0.124     2.966 r  initialize_audio/twi_controller/initA[6]_i_2/O
+                         net (fo=7, routed)           0.818     3.784    initialize_audio/twi_controller_n_8
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[4]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2281,30 +2215,30 @@ Slack (MET) :             14.772ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.710    18.418    initialize_audio/clk_out4
-    SLICE_X160Y111       FDRE                                         r  initialize_audio/initA_reg[0]/C
-                         clock pessimism              0.554    18.971    
-                         clock uncertainty           -0.094    18.877    
-    SLICE_X160Y111       FDRE (Setup_fdre_C_CE)      -0.205    18.672    initialize_audio/initA_reg[0]
+                         net (fo=120, routed)         1.705    18.413    initialize_audio/clk_out4
+    SLICE_X161Y117       FDRE                                         r  initialize_audio/initA_reg[4]/C
+                         clock pessimism              0.554    18.966    
+                         clock uncertainty           -0.094    18.872    
+    SLICE_X161Y117       FDRE (Setup_fdre_C_CE)      -0.205    18.667    initialize_audio/initA_reg[4]
   -------------------------------------------------------------------
-                         required time                         18.672    
-                         arrival time                          -3.900    
+                         required time                         18.667    
+                         arrival time                          -3.784    
   -------------------------------------------------------------------
-                         slack                                 14.772    
+                         slack                                 14.883    
 
-Slack (MET) :             14.772ns  (required time - arrival time)
-  Source:                 initialize_audio/delaycnt_reg[4]/C
-                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/initA_reg[2]/CE
+Slack (MET) :             14.994ns  (required time - arrival time)
+  Source:                 initialize_audio/twi_controller/sclCnt_reg[0]/C
+                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/dataByte_reg[4]/CE
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Setup (Max at Slow Process Corner)
   Requirement:            20.000ns  (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        4.891ns  (logic 0.952ns (19.463%)  route 3.939ns (80.537%))
-  Logic Levels:           4  (LUT4=2 LUT5=2)
-  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
-    Destination Clock Delay (DCD):    -1.582ns = ( 18.418 - 20.000 ) 
-    Source Clock Delay      (SCD):    -0.991ns
+  Data Path Delay:        4.713ns  (logic 1.014ns (21.516%)  route 3.699ns (78.484%))
+  Logic Levels:           4  (LUT2=2 LUT6=2)
+  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    -1.590ns = ( 18.410 - 20.000 ) 
+    Source Clock Delay      (SCD):    -1.007ns
     Clock Pessimism Removal (CPR):    0.554ns
   Clock Uncertainty:      0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter     (TSJ):    0.071ns
@@ -2323,20 +2257,20 @@ Slack (MET) :             14.772ns  (required time - arrival time)
                                                      -7.432    -4.724 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.808    -2.915    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.096    -2.819 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.828    -0.991    initialize_audio/clk_out4
-    SLICE_X156Y109       FDRE                                         r  initialize_audio/delaycnt_reg[4]/C
-  -------------------------------------------------------------------    -------------------
-    SLICE_X156Y109       FDRE (Prop_fdre_C_Q)         0.456    -0.535 f  initialize_audio/delaycnt_reg[4]/Q
-                         net (fo=3, routed)           0.833     0.298    initialize_audio/delaycnt_reg_n_0_[4]
-    SLICE_X157Y110       LUT4 (Prop_lut4_I0_O)        0.124     0.422 f  initialize_audio/initA[6]_i_13/O
-                         net (fo=1, routed)           0.877     1.299    initialize_audio/initA[6]_i_13_n_0
-    SLICE_X157Y110       LUT5 (Prop_lut5_I4_O)        0.124     1.423 r  initialize_audio/initA[6]_i_9/O
-                         net (fo=1, routed)           0.781     2.204    initialize_audio/initA[6]_i_9_n_0
-    SLICE_X157Y113       LUT4 (Prop_lut4_I1_O)        0.124     2.328 r  initialize_audio/initA[6]_i_4/O
-                         net (fo=4, routed)           0.822     3.150    initialize_audio/twi_controller/initEn_reg
-    SLICE_X158Y113       LUT5 (Prop_lut5_I1_O)        0.124     3.274 r  initialize_audio/twi_controller/initA[6]_i_2/O
-                         net (fo=7, routed)           0.627     3.900    initialize_audio/twi_controller_n_8
-    SLICE_X160Y111       FDRE                                         r  initialize_audio/initA_reg[2]/CE
+                         net (fo=120, routed)         1.812    -1.007    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y125       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X162Y125       FDSE (Prop_fdse_C_Q)         0.518    -0.489 f  initialize_audio/twi_controller/sclCnt_reg[0]/Q
+                         net (fo=7, routed)           0.820     0.331    initialize_audio/twi_controller/sclCnt[0]
+    SLICE_X160Y125       LUT6 (Prop_lut6_I2_O)        0.124     0.455 f  initialize_audio/twi_controller/sclCnt[6]_i_5/O
+                         net (fo=2, routed)           0.506     0.961    initialize_audio/twi_controller/sclCnt[6]_i_5_n_0
+    SLICE_X161Y125       LUT2 (Prop_lut2_I1_O)        0.124     1.085 r  initialize_audio/twi_controller/sclCnt[6]_i_4/O
+                         net (fo=13, routed)          1.021     2.106    initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+    SLICE_X160Y122       LUT6 (Prop_lut6_I3_O)        0.124     2.230 r  initialize_audio/twi_controller/dataByte[7]_i_3/O
+                         net (fo=4, routed)           0.877     3.107    initialize_audio/twi_controller/dataByte0
+    SLICE_X161Y121       LUT2 (Prop_lut2_I0_O)        0.124     3.231 r  initialize_audio/twi_controller/dataByte[7]_i_1/O
+                         net (fo=8, routed)           0.475     3.706    initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+    SLICE_X162Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[4]/CE
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2349,16 +2283,16 @@ Slack (MET) :             14.772ns  (required time - arrival time)
                                                      -7.674    14.893 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           1.723    16.616    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.091    16.707 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         1.710    18.418    initialize_audio/clk_out4
-    SLICE_X160Y111       FDRE                                         r  initialize_audio/initA_reg[2]/C
-                         clock pessimism              0.554    18.971    
-                         clock uncertainty           -0.094    18.877    
-    SLICE_X160Y111       FDRE (Setup_fdre_C_CE)      -0.205    18.672    initialize_audio/initA_reg[2]
+                         net (fo=120, routed)         1.702    18.410    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[4]/C
+                         clock pessimism              0.554    18.963    
+                         clock uncertainty           -0.094    18.869    
+    SLICE_X162Y120       FDRE (Setup_fdre_C_CE)      -0.169    18.700    initialize_audio/twi_controller/dataByte_reg[4]
   -------------------------------------------------------------------
-                         required time                         18.672    
-                         arrival time                          -3.900    
+                         required time                         18.700    
+                         arrival time                          -3.706    
   -------------------------------------------------------------------
-                         slack                                 14.772    
+                         slack                                 14.994    
 
 
 
@@ -2366,20 +2300,20 @@ Slack (MET) :             14.772ns  (required time - arrival time)
 
 Min Delay Paths
 --------------------------------------------------------------------------------------
-Slack (MET) :             0.109ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/dataByte_reg[4]/C
+Slack (MET) :             0.155ns  (arrival time - required time)
+  Source:                 initialize_audio/data_i_reg[6]/C
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/dataByte_reg[5]/D
+  Destination:            initialize_audio/twi_controller/dataByte_reg[6]/D
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.242ns  (logic 0.186ns (76.827%)  route 0.056ns (23.173%))
+  Data Path Delay:        0.290ns  (logic 0.186ns (64.194%)  route 0.104ns (35.806%))
   Logic Levels:           1  (LUT4=1)
-  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.900ns
-    Source Clock Delay      (SCD):    -0.657ns
-    Clock Pessimism Removal (CPR):    -0.256ns
+  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.904ns
+    Source Clock Delay      (SCD):    -0.661ns
+    Clock Pessimism Removal (CPR):    -0.257ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2393,14 +2327,14 @@ Slack (MET) :             0.109ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.643    -0.657    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[4]/C
+                         net (fo=120, routed)         0.639    -0.661    initialize_audio/clk_out4
+    SLICE_X160Y120       FDRE                                         r  initialize_audio/data_i_reg[6]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X159Y115       FDRE (Prop_fdre_C_Q)         0.141    -0.516 r  initialize_audio/twi_controller/dataByte_reg[4]/Q
-                         net (fo=1, routed)           0.056    -0.460    initialize_audio/twi_controller/dataByte[4]
-    SLICE_X158Y115       LUT4 (Prop_lut4_I0_O)        0.045    -0.415 r  initialize_audio/twi_controller/dataByte[5]_i_1/O
-                         net (fo=1, routed)           0.000    -0.415    initialize_audio/twi_controller/p_1_in[5]
-    SLICE_X158Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[5]/D
+    SLICE_X160Y120       FDRE (Prop_fdre_C_Q)         0.141    -0.520 r  initialize_audio/data_i_reg[6]/Q
+                         net (fo=1, routed)           0.104    -0.416    initialize_audio/twi_controller/Q[2]
+    SLICE_X162Y120       LUT4 (Prop_lut4_I2_O)        0.045    -0.371 r  initialize_audio/twi_controller/dataByte[6]_i_1/O
+                         net (fo=1, routed)           0.000    -0.371    initialize_audio/twi_controller/p_1_in[6]
+    SLICE_X162Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[6]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2413,30 +2347,30 @@ Slack (MET) :             0.109ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.914    -0.900    initialize_audio/twi_controller/clk_out4
-    SLICE_X158Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[5]/C
-                         clock pessimism              0.256    -0.644    
-    SLICE_X158Y115       FDRE (Hold_fdre_C_D)         0.120    -0.524    initialize_audio/twi_controller/dataByte_reg[5]
+                         net (fo=120, routed)         0.910    -0.904    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[6]/C
+                         clock pessimism              0.257    -0.647    
+    SLICE_X162Y120       FDRE (Hold_fdre_C_D)         0.121    -0.526    initialize_audio/twi_controller/dataByte_reg[6]
   -------------------------------------------------------------------
-                         required time                          0.524    
-                         arrival time                          -0.415    
+                         required time                          0.526    
+                         arrival time                          -0.371    
   -------------------------------------------------------------------
-                         slack                                  0.109    
+                         slack                                  0.155    
 
-Slack (MET) :             0.178ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[2]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/sclCnt_reg[4]/D
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) :             0.175ns  (arrival time - required time)
+  Source:                 initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.283ns  (logic 0.186ns (65.639%)  route 0.097ns (34.361%))
-  Logic Levels:           1  (LUT5=1)
+  Data Path Delay:        0.308ns  (logic 0.186ns (60.296%)  route 0.122ns (39.704%))
+  Logic Levels:           1  (LUT6=1)
   Clock Path Skew:        0.013ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.906ns
-    Source Clock Delay      (SCD):    -0.663ns
-    Clock Pessimism Removal (CPR):    -0.256ns
+    Destination Clock Delay (DCD):    -0.909ns
+    Source Clock Delay      (SCD):    -0.665ns
+    Clock Pessimism Removal (CPR):    -0.257ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2450,14 +2384,14 @@ Slack (MET) :             0.178ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.637    -0.663    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[2]/C
+                         net (fo=120, routed)         0.635    -0.665    initialize_audio/twi_controller/clk_out4
+    SLICE_X159Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.141    -0.522 r  initialize_audio/twi_controller/sclCnt_reg[2]/Q
-                         net (fo=5, routed)           0.097    -0.424    initialize_audio/twi_controller/sclCnt[2]
-    SLICE_X157Y128       LUT5 (Prop_lut5_I1_O)        0.045    -0.379 r  initialize_audio/twi_controller/sclCnt[4]_i_1/O
-                         net (fo=1, routed)           0.000    -0.379    initialize_audio/twi_controller/sclCnt[4]_i_1_n_0
-    SLICE_X157Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[4]/D
+    SLICE_X159Y123       FDRE (Prop_fdre_C_Q)         0.141    -0.524 r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/Q
+                         net (fo=25, routed)          0.122    -0.401    initialize_audio/twi_controller/state[1]
+    SLICE_X158Y123       LUT6 (Prop_lut6_I3_O)        0.045    -0.356 r  initialize_audio/twi_controller/FSM_gray_state[2]_i_1/O
+                         net (fo=1, routed)           0.000    -0.356    initialize_audio/twi_controller/FSM_gray_state[2]_i_1_n_0
+    SLICE_X158Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[2]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2470,30 +2404,30 @@ Slack (MET) :             0.178ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.908    -0.906    initialize_audio/twi_controller/clk_out4
-    SLICE_X157Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[4]/C
-                         clock pessimism              0.256    -0.650    
-    SLICE_X157Y128       FDSE (Hold_fdse_C_D)         0.092    -0.558    initialize_audio/twi_controller/sclCnt_reg[4]
+                         net (fo=120, routed)         0.905    -0.909    initialize_audio/twi_controller/clk_out4
+    SLICE_X158Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[2]/C
+                         clock pessimism              0.257    -0.652    
+    SLICE_X158Y123       FDRE (Hold_fdre_C_D)         0.120    -0.532    initialize_audio/twi_controller/FSM_gray_state_reg[2]
   -------------------------------------------------------------------
-                         required time                          0.558    
-                         arrival time                          -0.379    
+                         required time                          0.532    
+                         arrival time                          -0.356    
   -------------------------------------------------------------------
-                         slack                                  0.178    
+                         slack                                  0.175    
 
-Slack (MET) :             0.180ns  (arrival time - required time)
+Slack (MET) :             0.184ns  (arrival time - required time)
   Source:                 initialize_audio/twi_controller/sclCnt_reg[2]/C
                             (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/sclCnt_reg[3]/D
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/sclCnt_reg[5]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.284ns  (logic 0.186ns (65.408%)  route 0.098ns (34.592%))
-  Logic Levels:           1  (LUT4=1)
+  Data Path Delay:        0.289ns  (logic 0.186ns (64.416%)  route 0.103ns (35.584%))
+  Logic Levels:           1  (LUT6=1)
   Clock Path Skew:        0.013ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.906ns
-    Source Clock Delay      (SCD):    -0.663ns
-    Clock Pessimism Removal (CPR):    -0.256ns
+    Destination Clock Delay (DCD):    -0.909ns
+    Source Clock Delay      (SCD):    -0.665ns
+    Clock Pessimism Removal (CPR):    -0.257ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2507,14 +2441,14 @@ Slack (MET) :             0.180ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.637    -0.663    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[2]/C
+                         net (fo=120, routed)         0.635    -0.665    initialize_audio/twi_controller/clk_out4
+    SLICE_X161Y125       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[2]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.141    -0.522 r  initialize_audio/twi_controller/sclCnt_reg[2]/Q
-                         net (fo=5, routed)           0.098    -0.423    initialize_audio/twi_controller/sclCnt[2]
-    SLICE_X157Y128       LUT4 (Prop_lut4_I0_O)        0.045    -0.378 r  initialize_audio/twi_controller/sclCnt[3]_i_1/O
-                         net (fo=1, routed)           0.000    -0.378    initialize_audio/twi_controller/sclCnt01_in[3]
-    SLICE_X157Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[3]/D
+    SLICE_X161Y125       FDSE (Prop_fdse_C_Q)         0.141    -0.524 r  initialize_audio/twi_controller/sclCnt_reg[2]/Q
+                         net (fo=5, routed)           0.103    -0.421    initialize_audio/twi_controller/sclCnt[2]
+    SLICE_X160Y125       LUT6 (Prop_lut6_I1_O)        0.045    -0.376 r  initialize_audio/twi_controller/sclCnt[5]_i_1/O
+                         net (fo=1, routed)           0.000    -0.376    initialize_audio/twi_controller/sclCnt01_in[5]
+    SLICE_X160Y125       FDRE                                         r  initialize_audio/twi_controller/sclCnt_reg[5]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2527,30 +2461,30 @@ Slack (MET) :             0.180ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.908    -0.906    initialize_audio/twi_controller/clk_out4
-    SLICE_X157Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[3]/C
-                         clock pessimism              0.256    -0.650    
-    SLICE_X157Y128       FDSE (Hold_fdse_C_D)         0.091    -0.559    initialize_audio/twi_controller/sclCnt_reg[3]
+                         net (fo=120, routed)         0.905    -0.909    initialize_audio/twi_controller/clk_out4
+    SLICE_X160Y125       FDRE                                         r  initialize_audio/twi_controller/sclCnt_reg[5]/C
+                         clock pessimism              0.257    -0.652    
+    SLICE_X160Y125       FDRE (Hold_fdre_C_D)         0.092    -0.560    initialize_audio/twi_controller/sclCnt_reg[5]
   -------------------------------------------------------------------
-                         required time                          0.559    
-                         arrival time                          -0.378    
+                         required time                          0.560    
+                         arrival time                          -0.376    
   -------------------------------------------------------------------
-                         slack                                  0.180    
+                         slack                                  0.184    
 
 Slack (MET) :             0.187ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/sclCnt_reg[1]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/sclCnt_reg[5]/D
+  Source:                 initialize_audio/data_i_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/twi_controller/dataByte_reg[4]/D
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.292ns  (logic 0.186ns (63.646%)  route 0.106ns (36.354%))
-  Logic Levels:           1  (LUT6=1)
+  Data Path Delay:        0.320ns  (logic 0.186ns (58.127%)  route 0.134ns (41.873%))
+  Logic Levels:           1  (LUT4=1)
   Clock Path Skew:        0.013ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.906ns
-    Source Clock Delay      (SCD):    -0.663ns
-    Clock Pessimism Removal (CPR):    -0.256ns
+    Destination Clock Delay (DCD):    -0.904ns
+    Source Clock Delay      (SCD):    -0.660ns
+    Clock Pessimism Removal (CPR):    -0.257ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2564,14 +2498,14 @@ Slack (MET) :             0.187ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.637    -0.663    initialize_audio/twi_controller/clk_out4
-    SLICE_X156Y128       FDSE                                         r  initialize_audio/twi_controller/sclCnt_reg[1]/C
+                         net (fo=120, routed)         0.640    -0.660    initialize_audio/clk_out4
+    SLICE_X160Y119       FDRE                                         r  initialize_audio/data_i_reg[4]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X156Y128       FDSE (Prop_fdse_C_Q)         0.141    -0.522 r  initialize_audio/twi_controller/sclCnt_reg[1]/Q
-                         net (fo=6, routed)           0.106    -0.416    initialize_audio/twi_controller/sclCnt[1]
-    SLICE_X157Y128       LUT6 (Prop_lut6_I2_O)        0.045    -0.371 r  initialize_audio/twi_controller/sclCnt[5]_i_1/O
-                         net (fo=1, routed)           0.000    -0.371    initialize_audio/twi_controller/sclCnt01_in[5]
-    SLICE_X157Y128       FDRE                                         r  initialize_audio/twi_controller/sclCnt_reg[5]/D
+    SLICE_X160Y119       FDRE (Prop_fdre_C_Q)         0.141    -0.519 r  initialize_audio/data_i_reg[4]/Q
+                         net (fo=1, routed)           0.134    -0.385    initialize_audio/twi_controller/Q[1]
+    SLICE_X162Y120       LUT4 (Prop_lut4_I2_O)        0.045    -0.340 r  initialize_audio/twi_controller/dataByte[4]_i_1/O
+                         net (fo=1, routed)           0.000    -0.340    initialize_audio/twi_controller/p_1_in[4]
+    SLICE_X162Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[4]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2584,29 +2518,29 @@ Slack (MET) :             0.187ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.908    -0.906    initialize_audio/twi_controller/clk_out4
-    SLICE_X157Y128       FDRE                                         r  initialize_audio/twi_controller/sclCnt_reg[5]/C
-                         clock pessimism              0.256    -0.650    
-    SLICE_X157Y128       FDRE (Hold_fdre_C_D)         0.092    -0.558    initialize_audio/twi_controller/sclCnt_reg[5]
+                         net (fo=120, routed)         0.910    -0.904    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[4]/C
+                         clock pessimism              0.257    -0.647    
+    SLICE_X162Y120       FDRE (Hold_fdre_C_D)         0.120    -0.527    initialize_audio/twi_controller/dataByte_reg[4]
   -------------------------------------------------------------------
-                         required time                          0.558    
-                         arrival time                          -0.371    
+                         required time                          0.527    
+                         arrival time                          -0.340    
   -------------------------------------------------------------------
                          slack                                  0.187    
 
-Slack (MET) :             0.189ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/dataByte_reg[0]/C
+Slack (MET) :             0.201ns  (arrival time - required time)
+  Source:                 initialize_audio/initWord_reg[10]/C
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/dataByte_reg[1]/D
+  Destination:            initialize_audio/data_i_reg[2]/D
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.318ns  (logic 0.186ns (58.415%)  route 0.132ns (41.585%))
-  Logic Levels:           1  (LUT4=1)
-  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.899ns
-    Source Clock Delay      (SCD):    -0.657ns
+  Data Path Delay:        0.328ns  (logic 0.186ns (56.773%)  route 0.142ns (43.227%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.903ns
+    Source Clock Delay      (SCD):    -0.659ns
     Clock Pessimism Removal (CPR):    -0.280ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
@@ -2621,14 +2555,14 @@ Slack (MET) :             0.189ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.643    -0.657    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[0]/C
+                         net (fo=120, routed)         0.641    -0.659    initialize_audio/clk_out4
+    SLICE_X161Y118       FDRE                                         r  initialize_audio/initWord_reg[10]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X159Y115       FDRE (Prop_fdre_C_Q)         0.141    -0.516 r  initialize_audio/twi_controller/dataByte_reg[0]/Q
-                         net (fo=3, routed)           0.132    -0.383    initialize_audio/twi_controller/dataByte_reg_n_0_[0]
-    SLICE_X161Y115       LUT4 (Prop_lut4_I0_O)        0.045    -0.338 r  initialize_audio/twi_controller/dataByte[1]_i_1/O
-                         net (fo=1, routed)           0.000    -0.338    initialize_audio/twi_controller/p_1_in[1]
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[1]/D
+    SLICE_X161Y118       FDRE (Prop_fdre_C_Q)         0.141    -0.518 r  initialize_audio/initWord_reg[10]/Q
+                         net (fo=1, routed)           0.142    -0.376    initialize_audio/data2[2]
+    SLICE_X159Y118       LUT6 (Prop_lut6_I3_O)        0.045    -0.331 r  initialize_audio/data_i[2]_i_1/O
+                         net (fo=1, routed)           0.000    -0.331    initialize_audio/data_i[2]_i_1_n_0
+    SLICE_X159Y118       FDRE                                         r  initialize_audio/data_i_reg[2]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2641,29 +2575,29 @@ Slack (MET) :             0.189ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.915    -0.899    initialize_audio/twi_controller/clk_out4
-    SLICE_X161Y115       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[1]/C
-                         clock pessimism              0.280    -0.619    
-    SLICE_X161Y115       FDRE (Hold_fdre_C_D)         0.091    -0.528    initialize_audio/twi_controller/dataByte_reg[1]
+                         net (fo=120, routed)         0.911    -0.903    initialize_audio/clk_out4
+    SLICE_X159Y118       FDRE                                         r  initialize_audio/data_i_reg[2]/C
+                         clock pessimism              0.280    -0.623    
+    SLICE_X159Y118       FDRE (Hold_fdre_C_D)         0.091    -0.532    initialize_audio/data_i_reg[2]
   -------------------------------------------------------------------
-                         required time                          0.528    
-                         arrival time                          -0.338    
+                         required time                          0.532    
+                         arrival time                          -0.331    
   -------------------------------------------------------------------
-                         slack                                  0.189    
+                         slack                                  0.201    
 
-Slack (MET) :             0.198ns  (arrival time - required time)
-  Source:                 initialize_audio/initWord_reg[30]/C
+Slack (MET) :             0.213ns  (arrival time - required time)
+  Source:                 initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/data_i_reg[6]/D
+  Destination:            initialize_audio/twi_controller/subState_reg[0]/D
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.304ns  (logic 0.209ns (68.711%)  route 0.095ns (31.289%))
+  Data Path Delay:        0.349ns  (logic 0.186ns (53.358%)  route 0.163ns (46.642%))
   Logic Levels:           1  (LUT6=1)
   Clock Path Skew:        0.015ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.898ns
-    Source Clock Delay      (SCD):    -0.656ns
+    Destination Clock Delay (DCD):    -0.907ns
+    Source Clock Delay      (SCD):    -0.665ns
     Clock Pessimism Removal (CPR):    -0.257ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
@@ -2678,14 +2612,14 @@ Slack (MET) :             0.198ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.644    -0.656    initialize_audio/clk_out4
-    SLICE_X162Y114       FDRE                                         r  initialize_audio/initWord_reg[30]/C
+                         net (fo=120, routed)         0.635    -0.665    initialize_audio/twi_controller/clk_out4
+    SLICE_X159Y123       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X162Y114       FDRE (Prop_fdre_C_Q)         0.164    -0.492 r  initialize_audio/initWord_reg[30]/Q
-                         net (fo=1, routed)           0.095    -0.397    initialize_audio/data0[6]
-    SLICE_X161Y114       LUT6 (Prop_lut6_I2_O)        0.045    -0.352 r  initialize_audio/data_i[6]_i_1/O
-                         net (fo=1, routed)           0.000    -0.352    initialize_audio/data_i[6]_i_1_n_0
-    SLICE_X161Y114       FDRE                                         r  initialize_audio/data_i_reg[6]/D
+    SLICE_X159Y123       FDRE (Prop_fdre_C_Q)         0.141    -0.524 r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/Q
+                         net (fo=25, routed)          0.163    -0.361    initialize_audio/twi_controller/state[1]
+    SLICE_X158Y122       LUT6 (Prop_lut6_I2_O)        0.045    -0.316 r  initialize_audio/twi_controller/subState[0]_i_1/O
+                         net (fo=1, routed)           0.000    -0.316    initialize_audio/twi_controller/subState[0]_i_1_n_0
+    SLICE_X158Y122       FDRE                                         r  initialize_audio/twi_controller/subState_reg[0]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2698,30 +2632,30 @@ Slack (MET) :             0.198ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.916    -0.898    initialize_audio/clk_out4
-    SLICE_X161Y114       FDRE                                         r  initialize_audio/data_i_reg[6]/C
-                         clock pessimism              0.257    -0.641    
-    SLICE_X161Y114       FDRE (Hold_fdre_C_D)         0.091    -0.550    initialize_audio/data_i_reg[6]
+                         net (fo=120, routed)         0.907    -0.907    initialize_audio/twi_controller/clk_out4
+    SLICE_X158Y122       FDRE                                         r  initialize_audio/twi_controller/subState_reg[0]/C
+                         clock pessimism              0.257    -0.650    
+    SLICE_X158Y122       FDRE (Hold_fdre_C_D)         0.121    -0.529    initialize_audio/twi_controller/subState_reg[0]
   -------------------------------------------------------------------
-                         required time                          0.550    
-                         arrival time                          -0.352    
+                         required time                          0.529    
+                         arrival time                          -0.316    
   -------------------------------------------------------------------
-                         slack                                  0.198    
+                         slack                                  0.213    
 
-Slack (MET) :             0.199ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+Slack (MET) :             0.213ns  (arrival time - required time)
+  Source:                 initialize_audio/twi_controller/busFreeCnt_reg[5]/C
                             (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+  Destination:            initialize_audio/twi_controller/busFreeCnt_reg[5]/D
                             (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.304ns  (logic 0.209ns (68.859%)  route 0.095ns (31.141%))
-  Logic Levels:           1  (LUT5=1)
-  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.907ns
-    Source Clock Delay      (SCD):    -0.663ns
-    Clock Pessimism Removal (CPR):    -0.257ns
+  Data Path Delay:        0.334ns  (logic 0.209ns (62.484%)  route 0.125ns (37.516%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.908ns
+    Source Clock Delay      (SCD):    -0.664ns
+    Clock Pessimism Removal (CPR):    -0.244ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2735,14 +2669,14 @@ Slack (MET) :             0.199ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.637    -0.663    initialize_audio/twi_controller/clk_out4
-    SLICE_X158Y127       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+                         net (fo=120, routed)         0.636    -0.664    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y123       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[5]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X158Y127       FDSE (Prop_fdse_C_Q)         0.164    -0.499 r  initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
-                         net (fo=5, routed)           0.095    -0.404    initialize_audio/twi_controller/sel0[2]
-    SLICE_X159Y127       LUT5 (Prop_lut5_I3_O)        0.045    -0.359 r  initialize_audio/twi_controller/busFreeCnt[4]_i_1/O
-                         net (fo=1, routed)           0.000    -0.359    initialize_audio/twi_controller/busFreeCnt00_in[4]
-    SLICE_X159Y127       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+    SLICE_X162Y123       FDSE (Prop_fdse_C_Q)         0.164    -0.500 r  initialize_audio/twi_controller/busFreeCnt_reg[5]/Q
+                         net (fo=2, routed)           0.125    -0.374    initialize_audio/twi_controller/sel0[5]
+    SLICE_X162Y123       LUT6 (Prop_lut6_I5_O)        0.045    -0.329 r  initialize_audio/twi_controller/busFreeCnt[5]_i_1/O
+                         net (fo=1, routed)           0.000    -0.329    initialize_audio/twi_controller/busFreeCnt00_in[5]
+    SLICE_X162Y123       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[5]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2755,30 +2689,30 @@ Slack (MET) :             0.199ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.907    -0.907    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y127       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[4]/C
-                         clock pessimism              0.257    -0.650    
-    SLICE_X159Y127       FDSE (Hold_fdse_C_D)         0.092    -0.558    initialize_audio/twi_controller/busFreeCnt_reg[4]
+                         net (fo=120, routed)         0.906    -0.908    initialize_audio/twi_controller/clk_out4
+    SLICE_X162Y123       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[5]/C
+                         clock pessimism              0.244    -0.664    
+    SLICE_X162Y123       FDSE (Hold_fdse_C_D)         0.121    -0.543    initialize_audio/twi_controller/busFreeCnt_reg[5]
   -------------------------------------------------------------------
-                         required time                          0.558    
-                         arrival time                          -0.359    
+                         required time                          0.543    
+                         arrival time                          -0.329    
   -------------------------------------------------------------------
-                         slack                                  0.199    
+                         slack                                  0.213    
 
-Slack (MET) :             0.201ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/busFreeCnt_reg[2]/C
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/busFreeCnt_reg[3]/D
-                            (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+Slack (MET) :             0.214ns  (arrival time - required time)
+  Source:                 initialize_audio/initWord_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
+  Destination:            initialize_audio/data_i_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.305ns  (logic 0.209ns (68.633%)  route 0.096ns (31.367%))
-  Logic Levels:           1  (LUT4=1)
-  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.907ns
-    Source Clock Delay      (SCD):    -0.663ns
-    Clock Pessimism Removal (CPR):    -0.257ns
+  Data Path Delay:        0.341ns  (logic 0.186ns (54.476%)  route 0.155ns (45.524%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.904ns
+    Source Clock Delay      (SCD):    -0.660ns
+    Clock Pessimism Removal (CPR):    -0.280ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2792,14 +2726,14 @@ Slack (MET) :             0.201ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.637    -0.663    initialize_audio/twi_controller/clk_out4
-    SLICE_X158Y127       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+                         net (fo=120, routed)         0.640    -0.660    initialize_audio/clk_out4
+    SLICE_X163Y119       FDRE                                         r  initialize_audio/initWord_reg[8]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X158Y127       FDSE (Prop_fdse_C_Q)         0.164    -0.499 r  initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
-                         net (fo=5, routed)           0.096    -0.403    initialize_audio/twi_controller/sel0[2]
-    SLICE_X159Y127       LUT4 (Prop_lut4_I0_O)        0.045    -0.358 r  initialize_audio/twi_controller/busFreeCnt[3]_i_1/O
-                         net (fo=1, routed)           0.000    -0.358    initialize_audio/twi_controller/busFreeCnt00_in[3]
-    SLICE_X159Y127       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[3]/D
+    SLICE_X163Y119       FDRE (Prop_fdre_C_Q)         0.141    -0.519 r  initialize_audio/initWord_reg[8]/Q
+                         net (fo=1, routed)           0.155    -0.363    initialize_audio/data2[0]
+    SLICE_X159Y119       LUT6 (Prop_lut6_I3_O)        0.045    -0.318 r  initialize_audio/data_i[0]_i_1/O
+                         net (fo=1, routed)           0.000    -0.318    initialize_audio/data_i[0]_i_1_n_0
+    SLICE_X159Y119       FDRE                                         r  initialize_audio/data_i_reg[0]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2812,30 +2746,30 @@ Slack (MET) :             0.201ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.907    -0.907    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y127       FDSE                                         r  initialize_audio/twi_controller/busFreeCnt_reg[3]/C
-                         clock pessimism              0.257    -0.650    
-    SLICE_X159Y127       FDSE (Hold_fdse_C_D)         0.091    -0.559    initialize_audio/twi_controller/busFreeCnt_reg[3]
+                         net (fo=120, routed)         0.910    -0.904    initialize_audio/clk_out4
+    SLICE_X159Y119       FDRE                                         r  initialize_audio/data_i_reg[0]/C
+                         clock pessimism              0.280    -0.624    
+    SLICE_X159Y119       FDRE (Hold_fdre_C_D)         0.091    -0.533    initialize_audio/data_i_reg[0]
   -------------------------------------------------------------------
-                         required time                          0.559    
-                         arrival time                          -0.358    
+                         required time                          0.533    
+                         arrival time                          -0.318    
   -------------------------------------------------------------------
-                         slack                                  0.201    
+                         slack                                  0.214    
 
-Slack (MET) :             0.207ns  (arrival time - required time)
-  Source:                 initialize_audio/initWord_reg[17]/C
+Slack (MET) :             0.218ns  (arrival time - required time)
+  Source:                 initialize_audio/initWord_reg[15]/C
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/data_i_reg[1]/D
+  Destination:            initialize_audio/data_i_reg[7]/D
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.314ns  (logic 0.209ns (66.656%)  route 0.105ns (33.344%))
+  Data Path Delay:        0.323ns  (logic 0.186ns (57.594%)  route 0.137ns (42.406%))
   Logic Levels:           1  (LUT6=1)
-  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.898ns
-    Source Clock Delay      (SCD):    -0.656ns
-    Clock Pessimism Removal (CPR):    -0.257ns
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.903ns
+    Source Clock Delay      (SCD):    -0.660ns
+    Clock Pessimism Removal (CPR):    -0.256ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2849,14 +2783,14 @@ Slack (MET) :             0.207ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.644    -0.656    initialize_audio/clk_out4
-    SLICE_X162Y113       FDRE                                         r  initialize_audio/initWord_reg[17]/C
+                         net (fo=120, routed)         0.640    -0.660    initialize_audio/clk_out4
+    SLICE_X161Y119       FDRE                                         r  initialize_audio/initWord_reg[15]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X162Y113       FDRE (Prop_fdre_C_Q)         0.164    -0.492 r  initialize_audio/initWord_reg[17]/Q
-                         net (fo=2, routed)           0.105    -0.387    initialize_audio/data1[1]
-    SLICE_X161Y114       LUT6 (Prop_lut6_I5_O)        0.045    -0.342 r  initialize_audio/data_i[1]_i_1/O
-                         net (fo=1, routed)           0.000    -0.342    initialize_audio/data_i[1]_i_1_n_0
-    SLICE_X161Y114       FDRE                                         r  initialize_audio/data_i_reg[1]/D
+    SLICE_X161Y119       FDRE (Prop_fdre_C_Q)         0.141    -0.519 r  initialize_audio/initWord_reg[15]/Q
+                         net (fo=1, routed)           0.137    -0.382    initialize_audio/data2[7]
+    SLICE_X160Y119       LUT6 (Prop_lut6_I2_O)        0.045    -0.337 r  initialize_audio/data_i[7]_i_1/O
+                         net (fo=1, routed)           0.000    -0.337    initialize_audio/data_i[7]_i_1_n_0
+    SLICE_X160Y119       FDRE                                         r  initialize_audio/data_i_reg[7]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2869,30 +2803,30 @@ Slack (MET) :             0.207ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.916    -0.898    initialize_audio/clk_out4
-    SLICE_X161Y114       FDRE                                         r  initialize_audio/data_i_reg[1]/C
-                         clock pessimism              0.257    -0.641    
-    SLICE_X161Y114       FDRE (Hold_fdre_C_D)         0.092    -0.549    initialize_audio/data_i_reg[1]
+                         net (fo=120, routed)         0.911    -0.903    initialize_audio/clk_out4
+    SLICE_X160Y119       FDRE                                         r  initialize_audio/data_i_reg[7]/C
+                         clock pessimism              0.256    -0.647    
+    SLICE_X160Y119       FDRE (Hold_fdre_C_D)         0.092    -0.555    initialize_audio/data_i_reg[7]
   -------------------------------------------------------------------
-                         required time                          0.549    
-                         arrival time                          -0.342    
+                         required time                          0.555    
+                         arrival time                          -0.337    
   -------------------------------------------------------------------
-                         slack                                  0.207    
+                         slack                                  0.218    
 
-Slack (MET) :             0.208ns  (arrival time - required time)
-  Source:                 initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+Slack (MET) :             0.219ns  (arrival time - required time)
+  Source:                 initialize_audio/data_i_reg[1]/C
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
-  Destination:            initialize_audio/twi_controller/FSM_gray_state_reg[1]/D
+  Destination:            initialize_audio/twi_controller/dataByte_reg[1]/D
                             (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0  {rise@0.000ns fall@10.000ns period=20.000ns})
   Path Group:             clk_out4_clk_wiz_0
   Path Type:              Hold (Min at Fast Process Corner)
   Requirement:            0.000ns  (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
-  Data Path Delay:        0.335ns  (logic 0.186ns (55.563%)  route 0.149ns (44.437%))
-  Logic Levels:           1  (LUT6=1)
-  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
-    Destination Clock Delay (DCD):    -0.901ns
-    Source Clock Delay      (SCD):    -0.657ns
-    Clock Pessimism Removal (CPR):    -0.280ns
+  Data Path Delay:        0.323ns  (logic 0.186ns (57.598%)  route 0.137ns (42.402%))
+  Logic Levels:           1  (LUT4=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    -0.904ns
+    Source Clock Delay      (SCD):    -0.661ns
+    Clock Pessimism Removal (CPR):    -0.256ns
 
     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
   -------------------------------------------------------------------    -------------------
@@ -2906,14 +2840,14 @@ Slack (MET) :             0.208ns  (arrival time - required time)
                                                      -2.540    -1.856 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.531    -1.325    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026    -1.299 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.643    -0.657    initialize_audio/twi_controller/clk_out4
-    SLICE_X160Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+                         net (fo=120, routed)         0.639    -0.661    initialize_audio/clk_out4
+    SLICE_X160Y120       FDRE                                         r  initialize_audio/data_i_reg[1]/C
   -------------------------------------------------------------------    -------------------
-    SLICE_X160Y116       FDRE (Prop_fdre_C_Q)         0.141    -0.516 r  initialize_audio/twi_controller/FSM_gray_state_reg[0]/Q
-                         net (fo=26, routed)          0.149    -0.367    initialize_audio/twi_controller/state[0]
-    SLICE_X159Y116       LUT6 (Prop_lut6_I5_O)        0.045    -0.322 r  initialize_audio/twi_controller/FSM_gray_state[1]_i_1/O
-                         net (fo=1, routed)           0.000    -0.322    initialize_audio/twi_controller/FSM_gray_state[1]_i_1_n_0
-    SLICE_X159Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/D
+    SLICE_X160Y120       FDRE (Prop_fdre_C_Q)         0.141    -0.520 r  initialize_audio/data_i_reg[1]/Q
+                         net (fo=1, routed)           0.137    -0.383    initialize_audio/twi_controller/Q[0]
+    SLICE_X161Y120       LUT4 (Prop_lut4_I2_O)        0.045    -0.338 r  initialize_audio/twi_controller/dataByte[1]_i_1/O
+                         net (fo=1, routed)           0.000    -0.338    initialize_audio/twi_controller/p_1_in[1]
+    SLICE_X161Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[1]/D
   -------------------------------------------------------------------    -------------------
 
                          (clock clk_out4_clk_wiz_0 rise edge)
@@ -2926,15 +2860,15 @@ Slack (MET) :             0.208ns  (arrival time - required time)
                                                      -3.332    -2.421 r  clk_1/inst/mmcm_adv_inst/CLKOUT3
                          net (fo=1, routed)           0.579    -1.843    clk_1/inst/clk_out4_clk_wiz_0
     BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029    -1.814 r  clk_1/inst/clkout4_buf/O
-                         net (fo=120, routed)         0.913    -0.901    initialize_audio/twi_controller/clk_out4
-    SLICE_X159Y116       FDRE                                         r  initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
-                         clock pessimism              0.280    -0.621    
-    SLICE_X159Y116       FDRE (Hold_fdre_C_D)         0.091    -0.530    initialize_audio/twi_controller/FSM_gray_state_reg[1]
+                         net (fo=120, routed)         0.910    -0.904    initialize_audio/twi_controller/clk_out4
+    SLICE_X161Y120       FDRE                                         r  initialize_audio/twi_controller/dataByte_reg[1]/C
+                         clock pessimism              0.256    -0.648    
+    SLICE_X161Y120       FDRE (Hold_fdre_C_D)         0.091    -0.557    initialize_audio/twi_controller/dataByte_reg[1]
   -------------------------------------------------------------------
-                         required time                          0.530    
-                         arrival time                          -0.322    
+                         required time                          0.557    
+                         arrival time                          -0.338    
   -------------------------------------------------------------------
-                         slack                                  0.208    
+                         slack                                  0.219    
 
 
 
@@ -2950,35 +2884,35 @@ Sources:            { clk_1/inst/mmcm_adv_inst/CLKOUT3 }
 Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
 Min Period        n/a     BUFG/I              n/a            2.155         20.000      17.845     BUFGCTRL_X0Y2    clk_1/inst/clkout4_buf/I
 Min Period        n/a     MMCME2_ADV/CLKOUT3  n/a            1.249         20.000      18.751     MMCME2_ADV_X1Y2  clk_1/inst/mmcm_adv_inst/CLKOUT3
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y114   initialize_audio/data_i_reg[0]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X161Y114   initialize_audio/data_i_reg[1]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y114   initialize_audio/data_i_reg[2]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y113   initialize_audio/data_i_reg[3]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X160Y115   initialize_audio/data_i_reg[4]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y113   initialize_audio/data_i_reg[5]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X161Y114   initialize_audio/data_i_reg[6]/C
-Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X161Y114   initialize_audio/data_i_reg[7]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y119   initialize_audio/data_i_reg[0]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X160Y120   initialize_audio/data_i_reg[1]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y118   initialize_audio/data_i_reg[2]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y118   initialize_audio/data_i_reg[3]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X160Y119   initialize_audio/data_i_reg[4]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X159Y118   initialize_audio/data_i_reg[5]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X160Y120   initialize_audio/data_i_reg[6]/C
+Min Period        n/a     FDRE/C              n/a            1.000         20.000      19.000     SLICE_X160Y119   initialize_audio/data_i_reg[7]/C
 Max Period        n/a     MMCME2_ADV/CLKOUT3  n/a            213.360       20.000      193.360    MMCME2_ADV_X1Y2  clk_1/inst/mmcm_adv_inst/CLKOUT3
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[0]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[0]/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X161Y114   initialize_audio/data_i_reg[1]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X161Y114   initialize_audio/data_i_reg[1]/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[2]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[2]/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y113   initialize_audio/data_i_reg[3]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y113   initialize_audio/data_i_reg[3]/C
-Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y115   initialize_audio/data_i_reg[4]/C
-Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y115   initialize_audio/data_i_reg[4]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[0]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[0]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X161Y114   initialize_audio/data_i_reg[1]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X161Y114   initialize_audio/data_i_reg[1]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[2]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y114   initialize_audio/data_i_reg[2]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y113   initialize_audio/data_i_reg[3]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y113   initialize_audio/data_i_reg[3]/C
-High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y115   initialize_audio/data_i_reg[4]/C
-High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y115   initialize_audio/data_i_reg[4]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y119   initialize_audio/data_i_reg[0]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y119   initialize_audio/data_i_reg[0]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y120   initialize_audio/data_i_reg[1]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y120   initialize_audio/data_i_reg[1]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[2]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[2]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[3]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[3]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y119   initialize_audio/data_i_reg[4]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y119   initialize_audio/data_i_reg[4]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y119   initialize_audio/data_i_reg[0]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y119   initialize_audio/data_i_reg[0]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y120   initialize_audio/data_i_reg[1]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y120   initialize_audio/data_i_reg[1]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[2]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[2]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[3]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X159Y118   initialize_audio/data_i_reg[3]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y119   initialize_audio/data_i_reg[4]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         10.000      9.500      SLICE_X160Y119   initialize_audio/data_i_reg[4]/C
 
 
 
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx
index 65b0da8c80d1f921a5a6dfe884168f338d6b3c46..15670b446079dede91f1a5af35b45f3a7c8a6b5c 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb
index 6bf38ddf52649c8defe8e82e86e9d9f890205207..2ad3bdf9f710ede2b9500ec7fb09e57c182004f7 100644
Binary files a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb and b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
index 78c24222c01cc80728567dd80230e52a613161c2..930925882639fd045f7e97fe365270c0a8a8d210 100644
--- a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
+++ b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:48:58 2025
+| Date         : Mon May 12 16:23:14 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
 | Design       : audioProc
@@ -32,8 +32,8 @@ Table of Contents
 +-------------------------+------+-------+------------+-----------+-------+
 |        Site Type        | Used | Fixed | Prohibited | Available | Util% |
 +-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs              |  531 |     0 |        800 |    133800 |  0.40 |
-|   LUT as Logic          |  531 |     0 |        800 |    133800 |  0.40 |
+| Slice LUTs              |  527 |     0 |        800 |    133800 |  0.39 |
+|   LUT as Logic          |  527 |     0 |        800 |    133800 |  0.39 |
 |   LUT as Memory         |    0 |     0 |          0 |     46200 |  0.00 |
 | Slice Registers         |  903 |     0 |       1600 |    267600 |  0.34 |
 |   Register as Flip Flop |  893 |     0 |       1600 |    267600 |  0.33 |
@@ -69,12 +69,12 @@ Table of Contents
 +--------------------------------------------+------+-------+------------+-----------+-------+
 |                  Site Type                 | Used | Fixed | Prohibited | Available | Util% |
 +--------------------------------------------+------+-------+------------+-----------+-------+
-| Slice                                      |  263 |     0 |        200 |     33450 |  0.79 |
+| Slice                                      |  257 |     0 |        200 |     33450 |  0.77 |
 |   SLICEL                                   |  162 |     0 |            |           |       |
-|   SLICEM                                   |  101 |     0 |            |           |       |
-| LUT as Logic                               |  531 |     0 |        800 |    133800 |  0.40 |
+|   SLICEM                                   |   95 |     0 |            |           |       |
+| LUT as Logic                               |  527 |     0 |        800 |    133800 |  0.39 |
 |   using O5 output only                     |    0 |       |            |           |       |
-|   using O6 output only                     |  487 |       |            |           |       |
+|   using O6 output only                     |  483 |       |            |           |       |
 |   using O5 and O6                          |   44 |       |            |           |       |
 | LUT as Memory                              |    0 |     0 |          0 |     46200 |  0.00 |
 |   LUT as Distributed RAM                   |    0 |     0 |            |           |       |
@@ -86,10 +86,10 @@ Table of Contents
 |     using O6 output only                   |    0 |       |            |           |       |
 |     using O5 and O6                        |    0 |       |            |           |       |
 | Slice Registers                            |  903 |     0 |       1600 |    267600 |  0.34 |
-|   Register driven from within the Slice    |  330 |       |            |           |       |
-|   Register driven from outside the Slice   |  573 |       |            |           |       |
-|     LUT in front of the register is unused |  493 |       |            |           |       |
-|     LUT in front of the register is used   |   80 |       |            |           |       |
+|   Register driven from within the Slice    |  329 |       |            |           |       |
+|   Register driven from outside the Slice   |  574 |       |            |           |       |
+|     LUT in front of the register is unused |  501 |       |            |           |       |
+|     LUT in front of the register is used   |   73 |       |            |           |       |
 | Unique Control Sets                        |   32 |       |        200 |     33450 |  0.10 |
 +--------------------------------------------+------+-------+------------+-----------+-------+
 * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -187,14 +187,14 @@ Table of Contents
 |  Ref Name  | Used | Functional Category |
 +------------+------+---------------------+
 | FDCE       |  632 |        Flop & Latch |
-| LUT6       |  248 |                 LUT |
+| LUT6       |  245 |                 LUT |
 | FDRE       |  239 |        Flop & Latch |
-| LUT2       |  119 |                 LUT |
-| LUT4       |   79 |                 LUT |
+| LUT2       |  115 |                 LUT |
+| LUT4       |   81 |                 LUT |
 | MUXF7      |   64 |               MuxFx |
-| LUT5       |   52 |                 LUT |
+| LUT5       |   55 |                 LUT |
 | LUT1       |   41 |                 LUT |
-| LUT3       |   36 |                 LUT |
+| LUT3       |   34 |                 LUT |
 | MUXF8      |   32 |               MuxFx |
 | FDSE       |   20 |        Flop & Latch |
 | CARRY4     |   20 |          CarryLogic |
diff --git a/proj/AudioProc.runs/impl_1/clockInfo.txt b/proj/AudioProc.runs/impl_1/clockInfo.txt
index 78097d0dc6c600b56be7b2bc0e8896a1e47d4309..f884049d8ea7dba1181f23bb47df830d94683ec3 100644
--- a/proj/AudioProc.runs/impl_1/clockInfo.txt
+++ b/proj/AudioProc.runs/impl_1/clockInfo.txt
@@ -1,6 +1,6 @@
 -------------------------------------
 | Tool Version : Vivado v.2024.1
-| Date         : Fri May  9 15:48:48 2025
+| Date         : Mon May 12 16:23:09 2025
 | Host         : fl-tp-br-551
 | Design       : design_1
 | Device       : xc7a200t-sbg484-1--
diff --git a/proj/AudioProc.runs/impl_1/gen_run.xml b/proj/AudioProc.runs/impl_1/gen_run.xml
index 814f81b4c5e3995c51de2b11719e826fc417321b..63ee518425d92c1f90ad32144722dd7a20901603 100644
--- a/proj/AudioProc.runs/impl_1/gen_run.xml
+++ b/proj/AudioProc.runs/impl_1/gen_run.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1746798426">
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747059566">
   <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
   <File Type="POSTROUTE-PHYSOPT-RQS" Name="audioProc_postroute_physopted.rqs"/>
   <File Type="ROUTE-RQS" Name="audioProc_routed.rqs"/>
@@ -38,33 +38,33 @@
   <File Type="ROUTE-BUS-SKEW-RPX" Name="audioProc_bus_skew_routed.rpx"/>
   <File Type="ROUTE-BUS-SKEW-PB" Name="audioProc_bus_skew_routed.pb"/>
   <File Type="ROUTE-BUS-SKEW" Name="audioProc_bus_skew_routed.rpt"/>
-  <File Type="PLACE-UTIL-PB" Name="audioProc_utilization_placed.pb"/>
-  <File Type="OPT-METHODOLOGY-DRC" Name="audioProc_methodology_drc_opted.rpt"/>
-  <File Type="PLACE-UTIL" Name="audioProc_utilization_placed.rpt"/>
-  <File Type="PLACE-CLK" Name="audioProc_clock_utilization_placed.rpt"/>
-  <File Type="PLACE-IO" Name="audioProc_io_placed.rpt"/>
-  <File Type="PHYSOPT-TIMING" Name="audioProc_timing_summary_physopted.rpt"/>
-  <File Type="PWROPT-DRC" Name="audioProc_drc_pwropted.rpt"/>
-  <File Type="PWROPT-TIMING" Name="audioProc_timing_summary_pwropted.rpt"/>
-  <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
-  <File Type="PLACE-TIMING" Name="audioProc_timing_summary_placed.rpt"/>
-  <File Type="INIT-TIMING" Name="audioProc_timing_summary_init.rpt"/>
   <File Type="PA-TCL" Name="audioProc.tcl"/>
-  <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
-  <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
+  <File Type="INIT-TIMING" Name="audioProc_timing_summary_init.rpt"/>
   <File Type="OPT-DCP" Name="audioProc_opt.dcp"/>
   <File Type="OPT-RQA-PB" Name="audioProc_rqa_opted.pb"/>
+  <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
+  <File Type="PLACE-TIMING" Name="audioProc_timing_summary_placed.rpt"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="audioProc_methodology_drc_opted.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="audioProc_utilization_placed.pb"/>
   <File Type="OPT-HWDEF" Name="audioProc.hwdef"/>
   <File Type="POSTPLACE-PWROPT-TIMING" Name="audioProc_timing_summary_postplace_pwropted.rpt"/>
   <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
   <File Type="OPT-TIMING" Name="audioProc_timing_summary_opted.rpt"/>
-  <File Type="PLACE-SIMILARITY" Name="audioProc_incremental_reuse_placed.rpt"/>
-  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
+  <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
+  <File Type="PWROPT-DRC" Name="audioProc_drc_pwropted.rpt"/>
+  <File Type="PWROPT-TIMING" Name="audioProc_timing_summary_pwropted.rpt"/>
   <File Type="PLACE-DCP" Name="audioProc_placed.dcp"/>
   <File Type="PLACE-RQA-PB" Name="audioProc_rqa_placed.pb"/>
+  <File Type="PLACE-IO" Name="audioProc_io_placed.rpt"/>
+  <File Type="PHYSOPT-TIMING" Name="audioProc_timing_summary_physopted.rpt"/>
+  <File Type="PLACE-CLK" Name="audioProc_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="audioProc_utilization_placed.rpt"/>
+  <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="audioProc_incremental_reuse_placed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
   <File Type="PLACE-PRE-SIMILARITY" Name="audioProc_incremental_reuse_pre_placed.rpt"/>
   <File Type="ROUTE-DRC-RPX" Name="audioProc_drc_routed.rpx"/>
-  <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
   <File Type="POSTPLACE-PWROPT-DCP" Name="audioProc_postplace_pwropt.dcp"/>
   <File Type="PHYSOPT-DCP" Name="audioProc_physopt.dcp"/>
   <File Type="PHYSOPT-DRC" Name="audioProc_drc_physopted.rpt"/>
@@ -107,20 +107,19 @@
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
+    <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="implementation"/>
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+    <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+    <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="simulation"/>
@@ -151,13 +150,6 @@
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
-      <FileInfo>
-        <Attr Name="UserDisabled" Val="1"/>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="simulation"/>
-      </FileInfo>
-    </File>
     <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
       <FileInfo>
         <Attr Name="AutoDisabled" Val="1"/>
@@ -190,9 +182,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
-      <Desc>Vivado Implementation Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
     <Step Id="init_design"/>
     <Step Id="opt_design"/>
     <Step Id="power_opt_design"/>
diff --git a/proj/AudioProc.runs/impl_1/init_design.pb b/proj/AudioProc.runs/impl_1/init_design.pb
index 8fb34d5f14edcad69830830bd8a043d011688d9b..5652bb04378eb29d0ac296d0e1e1cde7fb2a16c8 100644
Binary files a/proj/AudioProc.runs/impl_1/init_design.pb and b/proj/AudioProc.runs/impl_1/init_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/opt_design.pb b/proj/AudioProc.runs/impl_1/opt_design.pb
index a48ee69fdfb456d9269776e1d4d5f1af705dccc9..55f12640c525568be0dbf40ae72ea4e455d260cd 100644
Binary files a/proj/AudioProc.runs/impl_1/opt_design.pb and b/proj/AudioProc.runs/impl_1/opt_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/place_design.pb b/proj/AudioProc.runs/impl_1/place_design.pb
index 30b44888db5a8c6711fbe49f922dbdaec808c5c9..0b1d19dfa1e0b844248253d21b71918219bfbb34 100644
Binary files a/proj/AudioProc.runs/impl_1/place_design.pb and b/proj/AudioProc.runs/impl_1/place_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/project.wdf b/proj/AudioProc.runs/impl_1/project.wdf
index b97fa11cc4865863ef25c6ee5f35f44a84cc1374..98bf4d09d9c36d47dbf8c416f4437f18313fbf36 100644
--- a/proj/AudioProc.runs/impl_1/project.wdf
+++ b/proj/AudioProc.runs/impl_1/project.wdf
@@ -1,5 +1,5 @@
 version:1
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3132:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:466c6f775f506572664f7074696d697a65645f48696768:00:00
@@ -14,7 +14,7 @@ version:1
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c3c6970636f72656e616d653e5c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:36:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:34:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
@@ -28,5 +28,5 @@ version:1
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3531616266366332333962393437613562646662663631376638343233316332:506172656e742050412070726f6a656374204944:00
-eof:2024053235
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3630303535313133613565333462303962393366626431636339643164613066:506172656e742050412070726f6a656374204944:00
+eof:1722730069
diff --git a/proj/AudioProc.runs/impl_1/route_design.pb b/proj/AudioProc.runs/impl_1/route_design.pb
index f7b09263ffe07412b5eb2c3410e61d89f660ff57..c9f2a40bddd00562c3c599046ed0c7df83070978 100644
Binary files a/proj/AudioProc.runs/impl_1/route_design.pb and b/proj/AudioProc.runs/impl_1/route_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/runme.log b/proj/AudioProc.runs/impl_1/runme.log
index b9ddcaecda824a27916512e6d57170aee1ae7713..bf18e1fe5977315de8e497a290337106c5fb9d2c 100644
--- a/proj/AudioProc.runs/impl_1/runme.log
+++ b/proj/AudioProc.runs/impl_1/runme.log
@@ -7,12 +7,12 @@
   **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
   **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
   **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-  **** Start of session at: Fri May  9 15:47:11 2025
+  **** Start of session at: Mon May 12 16:21:34 2025
     ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
     ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 
 source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1680.555 ; gain = 325.840 ; free physical = 1454 ; free virtual = 7989
+create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 1680.617 ; gain = 327.840 ; free physical = 1556 ; free virtual = 11335
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/repo'; Can't find the specified path.
 If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -23,7 +23,7 @@ Design is defaulting to constrset: constrs_1
 INFO: [Device 21-403] Loading part xc7a200tsbg484-1
 INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
 INFO: [Project 1-454] Reading design checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2098.805 ; gain = 0.000 ; free physical = 1037 ; free virtual = 7573
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2097.469 ; gain = 0.000 ; free physical = 1140 ; free virtual = 10919
 INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-479] Netlist was created with Vivado 2015.3
@@ -33,20 +33,20 @@ Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudian
 Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
 INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
 INFO: [Timing 38-2] Deriving generated clocks [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
-get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2746.297 ; gain = 544.930 ; free physical = 463 ; free virtual = 6998
+get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2743.961 ; gain = 551.961 ; free physical = 573 ; free virtual = 10351
 Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
 Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/constraints/NexysVideo_Master.xdc]
 Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/constraints/NexysVideo_Master.xdc]
 INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0.dcp'
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2746.297 ; gain = 0.000 ; free physical = 460 ; free virtual = 6996
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2743.961 ; gain = 0.000 ; free physical = 572 ; free virtual = 10350
 INFO: [Project 1-111] Unisim Transformation Summary:
   A total of 2 instances were transformed.
   IOBUF => IOBUF (IBUF, OBUFT): 2 instances
 
 14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 link_design completed successfully
-link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 2746.297 ; gain = 1050.898 ; free physical = 460 ; free virtual = 6996
+link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 2743.961 ; gain = 1048.500 ; free physical = 572 ; free virtual = 10350
 Command: opt_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
@@ -57,113 +57,112 @@ INFO: [DRC 23-27] Running DRC with 4 threads
 INFO: [Project 1-461] DRC finished with 0 Errors
 INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2755.203 ; gain = 8.906 ; free physical = 458 ; free virtual = 6993
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2755.836 ; gain = 11.875 ; free physical = 544 ; free virtual = 10322
 
 Starting Cache Timing Information Task
 INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 27a691c2e
+Ending Cache Timing Information Task | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2766.109 ; gain = 10.906 ; free physical = 458 ; free virtual = 6993
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2764.742 ; gain = 8.906 ; free physical = 544 ; free virtual = 10322
 
 Starting Logic Optimization Task
 
 Phase 1 Initialization
 
 Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 27a691c2e
+Phase 1.1 Core Generation And Design Setup | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 27a691c2e
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 1 Initialization | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Phase 1 Initialization | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 2 Timer Update And Timing Data Collection
 
 Phase 2.1 Timer Update
-Phase 2.1 Timer Update | Checksum: 27a691c2e
+Phase 2.1 Timer Update | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 2.2 Timing Data Collection
-Phase 2.2 Timing Data Collection | Checksum: 27a691c2e
+Phase 2.2 Timing Data Collection | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 2 Timer Update And Timing Data Collection | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
 
 Phase 3 Retarget
 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 27a691c2e
+Phase 3 Retarget | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Retarget | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Retarget | Checksum: 2b42ff704
 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
 INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 
 Phase 4 Constant propagation
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 27a691c2e
+Phase 4 Constant propagation | Checksum: 2b42ff704
 
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Constant propagation | Checksum: 27a691c2e
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Constant propagation | Checksum: 2b42ff704
 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
 
 Phase 5 Sweep
-Phase 5 Sweep | Checksum: 2f081e065
+Phase 5 Sweep | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Sweep | Checksum: 2f081e065
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 223 ; free virtual = 10001
+Sweep | Checksum: 2f3b7e24b
 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
 
 Phase 6 BUFG optimization
-INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells
-Phase 6 BUFG optimization | Checksum: 254f45935
+Phase 6 BUFG optimization | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-BUFG optimization | Checksum: 254f45935
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells.
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+BUFG optimization | Checksum: 2f3b7e24b
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
 
 Phase 7 Shift Register Optimization
 INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 254f45935
+Phase 7 Shift Register Optimization | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Shift Register Optimization | Checksum: 254f45935
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Shift Register Optimization | Checksum: 2f3b7e24b
 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
 
 Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 27a0b14a7
+Phase 8 Post Processing Netlist | Checksum: 2f3b7e24b
 
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Post Processing Netlist | Checksum: 27a0b14a7
+Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Post Processing Netlist | Checksum: 2f3b7e24b
 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
 
 Phase 9 Finalization
 
 Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2105fe3c5
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 9.2 Verifying Netlist Connectivity
 
 Starting Connectivity Check Task
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 2105fe3c5
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Phase 9 Finalization | Checksum: 2105fe3c5
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
+Phase 9 Finalization | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 Opt_design Change Summary
 =========================
 
@@ -174,34 +173,34 @@ Opt_design Change Summary
 |  Retarget                     |               0  |               0  |                                              1  |
 |  Constant propagation         |               0  |               0  |                                              0  |
 |  Sweep                        |               0  |               1  |                                              0  |
-|  BUFG optimization            |               0  |               2  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
 |  Shift Register Optimization  |               0  |               0  |                                              0  |
 |  Post Processing Netlist      |               0  |               0  |                                              0  |
 -------------------------------------------------------------------------------------------------------------------------
 
 
-Ending Logic Optimization Task | Checksum: 2105fe3c5
+Ending Logic Optimization Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Starting Power Optimization Task
 INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 2105fe3c5
+Ending Power Optimization Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 2105fe3c5
+Ending Final Cleanup Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
-Ending Netlist Obfuscation Task | Checksum: 2105fe3c5
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
+Ending Netlist Obfuscation Task | Checksum: 353293909
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3065.977 ; gain = 0.000 ; free physical = 280 ; free virtual = 6676
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3066.609 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 INFO: [Common 17-83] Releasing license: Implementation
-34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 opt_design completed successfully
 INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
 Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
@@ -210,16 +209,16 @@ INFO: [DRC 23-27] Running DRC with 4 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
 report_drc completed successfully
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 275 ; free virtual = 6671
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 275 ; free virtual = 6671
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 275 ; free virtual = 6671
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6667
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6667
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6668
-Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 271 ; free virtual = 6668
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 221 ; free virtual = 9999
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 220 ; free virtual = 9999
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 220 ; free virtual = 9999
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
 Command: place_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -239,57 +238,57 @@ Starting Placer Task
 Phase 1 Placer Initialization
 
 Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 256 ; free virtual = 6653
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1971e65b5
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 228 ; free virtual = 10007
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 27ecc6cee
 
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 256 ; free virtual = 6653
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 256 ; free virtual = 6653
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 228 ; free virtual = 10006
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 228 ; free virtual = 10006
 
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
 INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d834e537
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 167eef5db
 
-Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 255 ; free virtual = 6652
+Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 24479b66e
+Phase 1.3 Build Placer Netlist Model | Checksum: 243fe7c31
 
-Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.74 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 254 ; free virtual = 6650
+Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.65 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 24479b66e
+Phase 1.4 Constrain Clocks/Macros | Checksum: 243fe7c31
 
-Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.75 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 254 ; free virtual = 6650
-Phase 1 Placer Initialization | Checksum: 24479b66e
+Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.66 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
+Phase 1 Placer Initialization | Checksum: 243fe7c31
 
-Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.76 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 254 ; free virtual = 6650
+Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10001
 
 Phase 2 Global Placement
 
 Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1f0769a16
+Phase 2.1 Floorplanning | Checksum: 235583514
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.91 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 253 ; free virtual = 6649
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2d5cde647
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2509677d8
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 253 ; free virtual = 6649
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.83 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2d5cde647
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 2509677d8
 
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 253 ; free virtual = 6649
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.83 . Memory (MB): peak = 3114.633 ; gain = 0.000 ; free physical = 222 ; free virtual = 10000
 
 Phase 2.4 Global Placement Core
 
 Phase 2.4.1 UpdateTiming Before Physical Synthesis
-Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 24e71af8c
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1ef3d9d04
 
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3114.000 ; gain = 0.000 ; free physical = 349 ; free virtual = 6649
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3116.480 ; gain = 1.848 ; free physical = 207 ; free virtual = 9985
 
 Phase 2.4.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 96 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 93 LUT instances to create LUTNM shape
 INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
 INFO: [Physopt 32-1138] End 1 Pass. Optimized 44 nets or LUTs. Breaked 0 LUT, combined 44 existing LUTs and moved 0 existing LUT
 INFO: [Physopt 32-65] No nets found for high-fanout optimization.
@@ -302,7 +301,7 @@ INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was
 INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
 INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3117.781 ; gain = 0.000 ; free physical = 350 ; free virtual = 6650
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3117.383 ; gain = 0.000 ; free physical = 205 ; free virtual = 9984
 
 Summary of Physical Synthesis Optimizations
 ============================================
@@ -324,55 +323,55 @@ Summary of Physical Synthesis Optimizations
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 
 
-Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2d955f418
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1d76f29f6
 
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 350 ; free virtual = 6650
-Phase 2.4 Global Placement Core | Checksum: 24d73e065
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 205 ; free virtual = 9984
+Phase 2.4 Global Placement Core | Checksum: 1ce08bc3f
 
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 341 ; free virtual = 6641
-Phase 2 Global Placement | Checksum: 24d73e065
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 209 ; free virtual = 9987
+Phase 2 Global Placement | Checksum: 1ce08bc3f
 
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 341 ; free virtual = 6641
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 209 ; free virtual = 9987
 
 Phase 3 Detail Placement
 
 Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 23d657603
+Phase 3.1 Commit Multi Column Macros | Checksum: 118a6c22e
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 340 ; free virtual = 6641
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 209 ; free virtual = 9987
 
 Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22513e1c8
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 146facb8f
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 342 ; free virtual = 6642
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 208 ; free virtual = 9987
 
 Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 1ea1af04a
+Phase 3.3 Area Swap Optimization | Checksum: 1b29482ac
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 342 ; free virtual = 6642
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 208 ; free virtual = 9987
 
 Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 178715a17
+Phase 3.4 Pipeline Register Optimization | Checksum: 1f0d117d7
 
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 341 ; free virtual = 6642
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 208 ; free virtual = 9987
 
 Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 2d4f2065c
+Phase 3.5 Small Shape Detail Placement | Checksum: 2526c07bc
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9978
 
 Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1f22d608d
+Phase 3.6 Re-assign LUT pins | Checksum: 2624e5e42
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9979
 
 Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 146f8e4d1
+Phase 3.7 Pipeline Register Optimization | Checksum: 1a4d57885
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
-Phase 3 Detail Placement | Checksum: 146f8e4d1
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9979
+Phase 3 Detail Placement | Checksum: 1a4d57885
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3117.781 ; gain = 3.781 ; free physical = 338 ; free virtual = 6638
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3117.383 ; gain = 2.750 ; free physical = 200 ; free virtual = 9979
 
 Phase 4 Post Placement Optimization and Clean-Up
 
@@ -380,7 +379,7 @@ Phase 4.1 Post Commit Optimization
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 
 Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 236af2095
+Post Placement Optimization Initialization | Checksum: 195809db6
 
 Phase 4.1.1.1 BUFG Insertion
 
@@ -388,33 +387,33 @@ Starting Physical Synthesis Task
 
 Phase 1 Physical Synthesis Initialization
 INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.794 | TNS=0.000 |
-Phase 1 Physical Synthesis Initialization | Checksum: 2004c68b1
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.560 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 1178deb16
 
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 199 ; free virtual = 9978
 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1bfcb37d3
+Ending Physical Synthesis Task | Checksum: 236d54c7b
 
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 339 ; free virtual = 6640
-Phase 4.1.1.1 BUFG Insertion | Checksum: 236af2095
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 199 ; free virtual = 9978
+Phase 4.1.1.1 BUFG Insertion | Checksum: 195809db6
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.794. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 242e1e100
+INFO: [Place 30-746] Post Placement Timing Summary WNS=1.560. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Phase 4.1 Post Commit Optimization | Checksum: 242e1e100
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Phase 4.1 Post Commit Optimization | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 242e1e100
+Phase 4.2 Post Placement Cleanup | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.3 Placer Reporting
 
@@ -433,44 +432,44 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
 |       West|                1x1|                1x1|
 |___________|___________________|___________________|
 
-Phase 4.3.1 Print Estimated Congestion | Checksum: 242e1e100
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Phase 4.3 Placer Reporting | Checksum: 242e1e100
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Phase 4.3 Placer Reporting | Checksum: 2273b8652
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 
 Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 339 ; free virtual = 6639
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 199 ; free virtual = 9978
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c155315a
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 31419600f
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-Ending Placer Task | Checksum: c4fd0a1d
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+Ending Placer Task | Checksum: 24f565a1d
 
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
-69 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
+68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 place_design completed successfully
-place_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 3137.625 ; gain = 23.625 ; free physical = 339 ; free virtual = 6639
+place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3139.195 ; gain = 24.562 ; free physical = 199 ; free virtual = 9978
 INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
 Running report generation with 3 threads.
 INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 322 ; free virtual = 6623
+report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 179 ; free virtual = 9958
 INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
 INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 321 ; free virtual = 6622
+report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 183 ; free virtual = 9962
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 322 ; free virtual = 6622
-Wrote PlaceDB: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 318 ; free virtual = 6620
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6617
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 183 ; free virtual = 9962
+Wrote PlaceDB: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 183 ; free virtual = 9963
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6617
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6618
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6618
-Write Physdb Complete: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3137.625 ; gain = 0.000 ; free physical = 315 ; free virtual = 6618
+Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9963
+Write Physdb Complete: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3139.195 ; gain = 0.000 ; free physical = 181 ; free virtual = 9962
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
 Command: route_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -485,122 +484,121 @@ Starting Routing Task
 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
 
 Phase 1 Build RT Design
-Checksum: PlaceDB: 17894a90 ConstDB: 0 ShapeSum: 1558d429 RouteDB: 981aeb64
-Post Restoration Checksum: NetGraph: a8773583 | NumContArr: fe331ce0 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 32bfc479d
+Checksum: PlaceDB: ba349357 ConstDB: 0 ShapeSum: fd06db62 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: f76f7af6 | NumContArr: ea613dbe | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 36722adee
 
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 3339.742 ; gain = 178.105 ; free physical = 245 ; free virtual = 6437
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:47 . Memory (MB): peak = 3340.250 ; gain = 177.043 ; free physical = 176 ; free virtual = 9757
 
 Phase 2 Router Initialization
 
 Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 32bfc479d
+Phase 2.1 Fix Topology Constraints | Checksum: 36722adee
 
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 3339.742 ; gain = 178.105 ; free physical = 295 ; free virtual = 6436
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:47 . Memory (MB): peak = 3340.250 ; gain = 177.043 ; free physical = 176 ; free virtual = 9757
 
 Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 32bfc479d
+Phase 2.2 Pre Route Cleanup | Checksum: 36722adee
 
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 3339.742 ; gain = 178.105 ; free physical = 295 ; free virtual = 6436
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:47 . Memory (MB): peak = 3340.250 ; gain = 177.043 ; free physical = 176 ; free virtual = 9757
  Number of Nodes with overlaps = 0
 
 Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 2d1d4910a
+Phase 2.3 Update Timing | Checksum: 29d3a4195
 
-Time (s): cpu = 00:00:57 ; elapsed = 00:00:51 . Memory (MB): peak = 3388.719 ; gain = 227.082 ; free physical = 283 ; free virtual = 6388
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.803  | TNS=0.000  | WHS=-0.144 | THS=-22.944|
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:48 . Memory (MB): peak = 3388.227 ; gain = 225.020 ; free physical = 220 ; free virtual = 9702
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.562  | TNS=0.000  | WHS=-0.148 | THS=-26.208|
 
 
 Router Utilization Summary
-  Global Vertical Routing Utilization    = 0.000182205 %
-  Global Horizontal Routing Utilization  = 0.000165235 %
+  Global Vertical Routing Utilization    = 0.000141715 %
+  Global Horizontal Routing Utilization  = 6.60939e-05 %
   Routable Net Status*
   *Does not include unroutable nets such as driverless and loadless.
   Run report_route_status for detailed report.
-  Number of Failed Nets               = 1211
+  Number of Failed Nets               = 1207
     (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 1201
+  Number of Unrouted Nets             = 1197
   Number of Partially Routed Nets     = 10
-  Number of Node Overlaps             = 11
+  Number of Node Overlaps             = 10
 
-Phase 2 Router Initialization | Checksum: 269f51fe2
+Phase 2 Router Initialization | Checksum: 30251a708
 
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:51 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
 
 Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 269f51fe2
+Phase 3 Global Routing | Checksum: 30251a708
 
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:51 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
 
 Phase 4 Initial Routing
 
 Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 2c245566f
+Phase 4.1 Initial Net Routing Pass | Checksum: 266713b99
 
-Time (s): cpu = 00:00:59 ; elapsed = 00:00:52 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
-Phase 4 Initial Routing | Checksum: 2c245566f
+Time (s): cpu = 00:00:59 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
+Phase 4 Initial Routing | Checksum: 266713b99
 
-Time (s): cpu = 00:00:59 ; elapsed = 00:00:52 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 273 ; free virtual = 6378
+Time (s): cpu = 00:00:59 ; elapsed = 00:00:49 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 220 ; free virtual = 9701
 
 Phase 5 Rip-up And Reroute
 
 Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 238
- Number of Nodes with overlaps = 126
- Number of Nodes with overlaps = 68
- Number of Nodes with overlaps = 32
- Number of Nodes with overlaps = 10
- Number of Nodes with overlaps = 6
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 156
+ Number of Nodes with overlaps = 46
+ Number of Nodes with overlaps = 22
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 4
+ Number of Nodes with overlaps = 1
  Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.534  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.473  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 
-Phase 5.1 Global Iteration 0 | Checksum: 2abe36016
+Phase 5.1 Global Iteration 0 | Checksum: 2bbc7cb6a
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6365
-Phase 5 Rip-up And Reroute | Checksum: 2abe36016
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Phase 5 Rip-up And Reroute | Checksum: 2bbc7cb6a
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 6 Delay and Skew Optimization
 
 Phase 6.1 Delay CleanUp
 
 Phase 6.1.1 Update Timing
-Phase 6.1.1 Update Timing | Checksum: 2efa28e2c
+Phase 6.1.1 Update Timing | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.567  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 
-Phase 6.1 Delay CleanUp | Checksum: 2efa28e2c
+Phase 6.1 Delay CleanUp | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 2efa28e2c
+Phase 6.2 Clock Skew Optimization | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6365
-Phase 6 Delay and Skew Optimization | Checksum: 2efa28e2c
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Phase 6 Delay and Skew Optimization | Checksum: 250606fc2
 
-Time (s): cpu = 00:01:02 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 7 Post Hold Fix
 
 Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.613  | TNS=0.000  | WHS=0.107  | THS=0.000  |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.567  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 
-Phase 7.1 Hold Fix Iter | Checksum: 2486ccefa
+Phase 7.1 Hold Fix Iter | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
-Phase 7 Post Hold Fix | Checksum: 2486ccefa
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Phase 7 Post Hold Fix | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6366
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 8 Route finalize
 
 Router Utilization Summary
-  Global Vertical Routing Utilization    = 0.0942403 %
-  Global Horizontal Routing Utilization  = 0.118209 %
+  Global Vertical Routing Utilization    = 0.0912643 %
+  Global Horizontal Routing Utilization  = 0.112888 %
   Routable Net Status*
   *Does not include unroutable nets such as driverless and loadless.
   Run report_route_status for detailed report.
@@ -610,50 +608,50 @@ Router Utilization Summary
   Number of Partially Routed Nets     = 0
   Number of Node Overlaps             = 0
 
-Phase 8 Route finalize | Checksum: 2486ccefa
+Phase 8 Route finalize | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 262 ; free virtual = 6366
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 9 Verifying routed nets
 
  Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2486ccefa
+Phase 9 Verifying routed nets | Checksum: 2304ec34a
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 261 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 16786fc76
+Phase 10 Depositing Routes | Checksum: 26991fca5
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6365
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 16786fc76
+Phase 11 Post Process Routing | Checksum: 26991fca5
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.613  | TNS=0.000  | WHS=0.107  | THS=0.000  |
+INFO: [Route 35-57] Estimated Timing Summary | WNS=1.567  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 
 INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 16786fc76
+Phase 12 Post Router Timing | Checksum: 26991fca5
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
-Total Elapsed time in route_design: 55.27 secs
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
+Total Elapsed time in route_design: 50.86 secs
 
 Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: d2e3295b
+Phase 13 Post-Route Event Processing | Checksum: 1cf931110
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: d2e3295b
+Ending Routing Task | Checksum: 1cf931110
 
-Time (s): cpu = 00:01:03 ; elapsed = 00:00:55 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 260 ; free virtual = 6364
+Time (s): cpu = 00:01:01 ; elapsed = 00:00:51 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 
 Routing Is Done.
 INFO: [Common 17-83] Releasing license: Implementation
-88 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+87 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 route_design completed successfully
-route_design: Time (s): cpu = 00:01:04 ; elapsed = 00:00:56 . Memory (MB): peak = 3396.109 ; gain = 234.473 ; free physical = 259 ; free virtual = 6364
+route_design: Time (s): cpu = 00:01:03 ; elapsed = 00:00:52 . Memory (MB): peak = 3395.617 ; gain = 232.410 ; free physical = 218 ; free virtual = 9700
 INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
 Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -683,23 +681,22 @@ Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summa
 Running Vector-less Activity Propagation...
 
 Finished Running Vector-less Activity Propagation
-108 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+107 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 report_power completed successfully
 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
 WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
 WARNING: [Device 21-2174] Failed to initialize Virtual grid.
-generate_parallel_reports: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3452.137 ; gain = 56.027 ; free physical = 351 ; free virtual = 6361
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 351 ; free virtual = 6361
-Wrote PlaceDB: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 352 ; free virtual = 6362
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 351 ; free virtual = 6361
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 206 ; free virtual = 9689
+Wrote PlaceDB: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 205 ; free virtual = 9690
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 205 ; free virtual = 9690
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 350 ; free virtual = 6361
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 350 ; free virtual = 6361
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 349 ; free virtual = 6361
-Write Physdb Complete: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.42 . Memory (MB): peak = 3452.137 ; gain = 0.000 ; free physical = 349 ; free virtual = 6361
+Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 205 ; free virtual = 9690
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 204 ; free virtual = 9689
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 204 ; free virtual = 9689
+Write Physdb Complete: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3451.645 ; gain = 0.000 ; free physical = 204 ; free virtual = 9689
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
 Command: write_bitstream -force audioProc.bit -bin_file
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
@@ -726,8 +723,8 @@ WARNING: [DRC DPOP-1] PREG Output pipelining: DSP leftFir/firUnit_1/operativeUni
 WARNING: [DRC DPOP-1] PREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult output rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
 WARNING: [DRC DPOP-2] MREG Output pipelining: DSP leftFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage leftFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
 WARNING: [DRC DPOP-2] MREG Output pipelining: DSP rightFir/firUnit_1/operativeUnit_1/SC_addResult multiplier stage rightFir/firUnit_1/operativeUnit_1/SC_addResult/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
-WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
-WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_nextState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_nextState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
 INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
 INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
 INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
@@ -741,7 +738,7 @@ Writing bitstream ./audioProc.bit...
 Writing bitstream ./audioProc.bin...
 INFO: [Vivado 12-1842] Bitgen Completed Successfully.
 INFO: [Common 17-83] Releasing license: Implementation
-119 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
+118 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
 write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 3773.680 ; gain = 321.543 ; free physical = 301 ; free virtual = 5990
-INFO: [Common 17-206] Exiting Vivado at Fri May  9 15:50:23 2025...
+write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 3771.219 ; gain = 319.574 ; free physical = 153 ; free virtual = 9353
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:24:32 2025...
diff --git a/proj/AudioProc.runs/impl_1/vivado.jou b/proj/AudioProc.runs/impl_1/vivado.jou
index 0aeedac4ef7e18afe93d4a351c46b9304c9fd550..31039fdffc791e70d2d476ef13865eddd16bc9e7 100644
--- a/proj/AudioProc.runs/impl_1/vivado.jou
+++ b/proj/AudioProc.runs/impl_1/vivado.jou
@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May  9 15:47:10 2025
-# Process ID: 2029775
+# Start of session at: Mon May 12 16:21:34 2025
+# Process ID: 78259
 # Current directory: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1
 # Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
 # Log file: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -13,12 +13,12 @@
 # Platform          :Ubuntu
 # Operating System  :Ubuntu 24.04.2 LTS
 # Processor Detail  :Intel(R) Xeon(R) CPU E5-1607 v4 @ 3.10GHz
-# CPU Frequency     :3092.852 MHz
+# CPU Frequency     :3092.499 MHz
 # CPU Physical cores:4
 # CPU Logical cores :4
 # Host memory       :16687 MB
 # Swap memory       :4294 MB
 # Total Virtual     :20982 MB
-# Available Virtual :9024 MB
+# Available Virtual :12515 MB
 #-----------------------------------------------------------
 source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado.pb b/proj/AudioProc.runs/impl_1/vivado.pb
index 0b65bdb17b689272098f902bfdadb08947594e20..7eb252e42548ce97972bee5dcc10597e8d4b9c22 100644
Binary files a/proj/AudioProc.runs/impl_1/vivado.pb and b/proj/AudioProc.runs/impl_1/vivado.pb differ
diff --git a/proj/AudioProc.runs/impl_1/write_bitstream.pb b/proj/AudioProc.runs/impl_1/write_bitstream.pb
index 394844bde45de37f5861b9201361569b195b572a..e416619522aefecd431876722a6979cb6b8de951 100644
Binary files a/proj/AudioProc.runs/impl_1/write_bitstream.pb and b/proj/AudioProc.runs/impl_1/write_bitstream.pb differ
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
index 5f7945894f601bb7c7f597a167a00b9ac1d86b34..f14427f3d0ed491d2ad9defaf63db1fde974ee84 100644
--- a/proj/AudioProc.runs/synth_1/.vivado.begin.rst
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command="vivado" Owner="g24demon" Host="fl-tp-br-551" Pid="2028730" HostCore="4" HostMemory="16296788">
+    <Process Command="vivado" Owner="g24demon" Host="fl-tp-br-551" Pid="77494" HostCore="4" HostMemory="16296780">
     </Process>
 </ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/audioProc.dcp b/proj/AudioProc.runs/synth_1/audioProc.dcp
index b65995c714e13989394e03f37c1f277053b303e5..a705d1c2c678263646c51f71b89215ad84aab222 100644
Binary files a/proj/AudioProc.runs/synth_1/audioProc.dcp and b/proj/AudioProc.runs/synth_1/audioProc.dcp differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc.tcl b/proj/AudioProc.runs/synth_1/audioProc.tcl
index f07071f0311d3c60825200c3f9d6a29b6f520d69..ed7cf0169974920d8889adbbd668661c1bcf8e9b 100644
--- a/proj/AudioProc.runs/synth_1/audioProc.tcl
+++ b/proj/AudioProc.runs/synth_1/audioProc.tcl
@@ -56,6 +56,8 @@ if {$::dispatch::connected} {
 }
 
 OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param chipscope.maxJobs 1
+set_msg_config -id {Common 17-41} -limit 10000000
 OPTRACE "Creating in-memory project" START { }
 create_project -in_memory -part xc7a200tsbg484-1
 
@@ -76,12 +78,12 @@ OPTRACE "Adding files" START { }
 read_verilog -library xil_defaultlib {
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audio_init.v
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/debounce.v
-  /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v
 }
 read_vhdl -library xil_defaultlib {
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/TWICtl.vhd
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd
+  /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/fir.vhd
   /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/i2s_ctl.vhd
diff --git a/proj/AudioProc.runs/synth_1/audioProc.vds b/proj/AudioProc.runs/synth_1/audioProc.vds
index 05a7671c06a2414b2ea30bf259a92e8f03833fab..b80e67db707f6b589d3dc2147eee931784edf21a 100644
--- a/proj/AudioProc.runs/synth_1/audioProc.vds
+++ b/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May  9 15:43:37 2025
-# Process ID: 2028801
+# Start of session at: Mon May 12 16:19:30 2025
+# Process ID: 77565
 # Current directory: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1
 # Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
 # Log file: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -13,16 +13,16 @@
 # Platform          :Ubuntu
 # Operating System  :Ubuntu 24.04.2 LTS
 # Processor Detail  :Intel(R) Xeon(R) CPU E5-1607 v4 @ 3.10GHz
-# CPU Frequency     :3092.855 MHz
+# CPU Frequency     :3092.499 MHz
 # CPU Physical cores:4
 # CPU Logical cores :4
 # Host memory       :16687 MB
 # Swap memory       :4294 MB
 # Total Virtual     :20982 MB
-# Available Virtual :8828 MB
+# Available Virtual :12524 MB
 #-----------------------------------------------------------
 source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 1680.617 ; gain = 326.840 ; free physical = 276 ; free virtual = 7898
+create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:35 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 1559 ; free virtual = 11337
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/repo'; Can't find the specified path.
 If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -43,12 +43,12 @@ INFO: [Device 21-403] Loading part xc7a200tsbg484-1
 INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
 INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 2029065
+INFO: [Synth 8-7075] Helper process launched with PID 77893
 ---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2500.855 ; gain = 419.516 ; free physical = 217 ; free virtual = 6888
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2500.824 ; gain = 419.516 ; free physical = 460 ; free virtual = 10238
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:13]
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/.Xil/Vivado-2028801-fl-tp-br-551/realtime/clk_wiz_0_stub.vhdl:18]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/.Xil/Vivado-77565-fl-tp-br-551/realtime/clk_wiz_0_stub.vhdl:18]
 WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:87]
 WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:87]
 INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audio_init.v:24]
@@ -75,124 +75,8 @@ INFO: [Synth 8-6054] Found Dynamic range expression with variable size [/homes/g
 INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd:42]
 INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd:45]
 INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd:45]
-INFO: [Synth 8-6157] synthesizing module 'operativeUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:17]
-INFO: [Synth 8-6157] synthesizing module 'GND' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6155] done synthesizing module 'GND' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6157] synthesizing module 'OBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6157] synthesizing module 'LUT3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-	Parameter INIT bound to: 8'b10000000 
-INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'DSP48E1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
-	Parameter ACASCREG bound to: 0 - type: integer 
-	Parameter ADREG bound to: 1 - type: integer 
-	Parameter ALUMODEREG bound to: 0 - type: integer 
-	Parameter AREG bound to: 0 - type: integer 
-	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
-	Parameter A_INPUT bound to: DIRECT - type: string 
-	Parameter BCASCREG bound to: 0 - type: integer 
-	Parameter BREG bound to: 0 - type: integer 
-	Parameter B_INPUT bound to: DIRECT - type: string 
-	Parameter CARRYINREG bound to: 0 - type: integer 
-	Parameter CARRYINSELREG bound to: 0 - type: integer 
-	Parameter CREG bound to: 0 - type: integer 
-	Parameter DREG bound to: 1 - type: integer 
-	Parameter INMODEREG bound to: 0 - type: integer 
-	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
-	Parameter MREG bound to: 0 - type: integer 
-	Parameter OPMODEREG bound to: 0 - type: integer 
-	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
-	Parameter PREG bound to: 0 - type: integer 
-	Parameter SEL_MASK bound to: MASK - type: string 
-	Parameter SEL_PATTERN bound to: PATTERN - type: string 
-	Parameter USE_DPORT bound to: FALSE - type: string 
-	Parameter USE_MULT bound to: MULTIPLY - type: string 
-	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
-	Parameter USE_SIMD bound to: ONE48 - type: string 
-INFO: [Synth 8-6155] done synthesizing module 'DSP48E1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
-WARNING: [Synth 8-689] width (36) of port connection 'P' does not match port width (48) of module 'DSP48E1' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:422]
-WARNING: [Synth 8-7071] port 'ACOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'BCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYCASCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'MULTSIGNOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'OVERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNBDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'UNDERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7023] instance 'SC_addResult' of module 'DSP48E1' has 49 connections declared, but only 39 given [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-INFO: [Synth 8-6157] synthesizing module 'LUT2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b0110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1011111111111101 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
-	Parameter INIT bound to: 64'b1010111110100000110011111100111110101111101000001100000011000000 
-INFO: [Synth 8-6155] done synthesizing module 'LUT6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0101100000011010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1111011001101111 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0001111001111000 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1110100110010111 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0110000110000110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-	Parameter INIT bound to: 8'b01000010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1010001001000101 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1111000110001111 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1101010110101011 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'FDCE' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
-	Parameter INIT bound to: 1'b0 
-INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
-INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:1478]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b0001 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-	Parameter INIT bound to: 8'b00000110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0000000001101010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b1110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
-	Parameter INIT bound to: 32'b00000000000000000110101010101010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b0010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'VCC' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'VCC' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'operativeUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:17]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd:55]
 INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd:42]
 INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/fir.vhd:28]
 WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:199]
@@ -241,20 +125,18 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
 WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
 WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
 ---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2589.793 ; gain = 508.453 ; free physical = 217 ; free virtual = 6789
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2584.762 ; gain = 503.453 ; free physical = 365 ; free virtual = 10143
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2607.605 ; gain = 526.266 ; free physical = 214 ; free virtual = 6786
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2602.574 ; gain = 521.266 ; free physical = 364 ; free virtual = 10141
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2607.605 ; gain = 526.266 ; free physical = 214 ; free virtual = 6786
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2602.574 ; gain = 521.266 ; free physical = 364 ; free virtual = 10141
 ---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2613.543 ; gain = 0.000 ; free physical = 216 ; free virtual = 6781
-INFO: [Netlist 29-17] Analyzing 106 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2602.574 ; gain = 0.000 ; free physical = 363 ; free virtual = 10141
 INFO: [Project 1-570] Preparing netlist for logic optimization
 
 Processing XDC Constraints
@@ -269,20 +151,20 @@ Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noel
 Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/dont_touch.xdc]
 Completed Processing XDC Constraints
 
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 220 ; free virtual = 6778
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2752.324 ; gain = 0.000 ; free physical = 343 ; free virtual = 10121
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 223 ; free virtual = 6781
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2752.324 ; gain = 0.000 ; free physical = 343 ; free virtual = 10121
 ---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 218 ; free virtual = 6772
+Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 361 ; free virtual = 10139
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7a200tsbg484-1
 ---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 218 ; free virtual = 6772
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 360 ; free virtual = 10139
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
@@ -290,7 +172,7 @@ Start Applying 'set_property' XDC Constraints
 Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file  /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
 Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file  auto generated constraint).
 ---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 219 ; free virtual = 6772
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 359 ; free virtual = 10138
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
 INFO: [Synth 8-802] inferred FSM for state register 'SR_currentState_reg' in module 'controlUnit'
@@ -320,7 +202,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding
 INFO: [Synth 8-3354] encoded FSM with state register 'SR_currentState_reg' using encoding 'one-hot' in module 'controlUnit'
 WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_nextState_reg' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd:62]
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 224 ; free virtual = 6776
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 352 ; free virtual = 10131
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start RTL Component Statistics 
@@ -330,39 +212,44 @@ Detailed RTL Component Info :
 	   2 Input   32 Bit       Adders := 3     
 	   2 Input   31 Bit       Adders := 1     
 	   2 Input   24 Bit       Adders := 2     
+	   2 Input   16 Bit       Adders := 2     
 	   2 Input   13 Bit       Adders := 5     
 	   2 Input    7 Bit       Adders := 3     
 	   2 Input    5 Bit       Adders := 2     
-	   2 Input    4 Bit       Adders := 1     
+	   2 Input    4 Bit       Adders := 3     
 	   2 Input    3 Bit       Adders := 1     
 	   2 Input    2 Bit       Adders := 1     
 +---Registers : 
+	               36 Bit    Registers := 2     
 	               33 Bit    Registers := 1     
 	               32 Bit    Registers := 3     
 	               31 Bit    Registers := 1     
 	               24 Bit    Registers := 2     
+	               16 Bit    Registers := 34    
 	               13 Bit    Registers := 5     
 	                8 Bit    Registers := 3     
 	                7 Bit    Registers := 3     
 	                5 Bit    Registers := 4     
-	                4 Bit    Registers := 2     
+	                4 Bit    Registers := 4     
 	                3 Bit    Registers := 1     
 	                2 Bit    Registers := 2     
 	                1 Bit    Registers := 18    
 +---Muxes : 
+	   2 Input   36 Bit        Muxes := 2     
 	   2 Input   32 Bit        Muxes := 3     
 	   2 Input   24 Bit        Muxes := 2     
 	   2 Input   16 Bit        Muxes := 6     
+	  16 Input   12 Bit        Muxes := 2     
 	   2 Input    8 Bit        Muxes := 2     
 	   2 Input    5 Bit        Muxes := 9     
 	   8 Input    5 Bit        Muxes := 1     
 	   5 Input    5 Bit        Muxes := 2     
 	   9 Input    4 Bit        Muxes := 1     
 	  21 Input    4 Bit        Muxes := 1     
-	   2 Input    4 Bit        Muxes := 7     
+	   2 Input    4 Bit        Muxes := 9     
 	   5 Input    3 Bit        Muxes := 2     
 	   3 Input    2 Bit        Muxes := 1     
-	   2 Input    1 Bit        Muxes := 39    
+	   2 Input    1 Bit        Muxes := 45    
 	   4 Input    1 Bit        Muxes := 21    
 	   3 Input    1 Bit        Muxes := 5     
 	   9 Input    1 Bit        Muxes := 1     
@@ -386,6 +273,12 @@ Finished Part Resource Summary
 Start Cross Boundary and Area Optimization
 ---------------------------------------------------------------------------------
 WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
 WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
 WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
 WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
@@ -408,25 +301,43 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
 WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
 WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
 ---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 231 ; free virtual = 6771
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 329 ; free virtual = 10113
+---------------------------------------------------------------------------------
+ Sort Area is  firUnit_1/operativeUnit_1/SC_addResult_0 : 0 0 : 1641 1641 : Used 1 time 0
+ Sort Area is  firUnit_1/operativeUnit_1/SC_addResult_2 : 0 0 : 1641 1641 : Used 1 time 0
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name   | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B       | 16     | 13     | 36     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
+|operativeUnit | C+A*B       | 16     | 13     | 36     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 241 ; free virtual = 6782
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 327 ; free virtual = 10112
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 241 ; free virtual = 6782
+Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 329 ; free virtual = 10114
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 315 ; free virtual = 10100
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start IO Insertion
@@ -446,49 +357,49 @@ Finished Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
 ---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
 ---------------------------------------------------------------------------------
 
 DSP Final Report (the ' indicates corresponding REG is set)
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name     | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|operativeUnit_3 | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
-|operativeUnit   | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name   | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
+|operativeUnit | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
 
 
 Report BlackBoxes: 
@@ -503,217 +414,52 @@ Report Cell Usage:
 |      |Cell    |Count |
 +------+--------+------+
 |1     |clk_wiz |     1|
-|2     |BUFG    |     2|
-|3     |CARRY4  |    20|
-|4     |DSP48E1 |     2|
-|5     |LUT1    |    41|
-|6     |LUT2    |   119|
-|7     |LUT3    |    36|
-|8     |LUT4    |    79|
-|9     |LUT5    |    52|
-|10    |LUT6    |   248|
-|11    |MUXF7   |    64|
-|12    |MUXF8   |    32|
-|13    |FDCE    |   632|
-|14    |FDPE    |     2|
-|15    |FDRE    |   239|
-|16    |FDSE    |    20|
-|17    |LD      |    10|
-|18    |IBUF    |    57|
-|19    |IOBUF   |     2|
-|20    |OBUF    |    44|
+|2     |CARRY4  |    20|
+|3     |DSP48E1 |     2|
+|4     |LUT1    |    41|
+|5     |LUT2    |   115|
+|6     |LUT3    |    34|
+|7     |LUT4    |    81|
+|8     |LUT5    |    55|
+|9     |LUT6    |   245|
+|10    |MUXF7   |    64|
+|11    |MUXF8   |    32|
+|12    |FDCE    |   632|
+|13    |FDPE    |     2|
+|14    |FDRE    |   239|
+|15    |FDSE    |    20|
+|16    |LD      |    10|
+|17    |IBUF    |     9|
+|18    |IOBUF   |     2|
+|19    |OBUF    |    10|
 +------+--------+------+
 ---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 1 critical warnings and 23 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2712.559 ; gain = 526.266 ; free physical = 240 ; free virtual = 6781
-Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 239 ; free virtual = 6780
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 2752.324 ; gain = 521.266 ; free physical = 319 ; free virtual = 10104
+Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.332 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 507 ; free virtual = 7047
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2752.332 ; gain = 0.000 ; free physical = 586 ; free virtual = 10371
 INFO: [Netlist 29-17] Analyzing 130 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 501 ; free virtual = 7042
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2752.332 ; gain = 0.000 ; free physical = 589 ; free virtual = 10374
 INFO: [Project 1-111] Unisim Transformation Summary:
   A total of 12 instances were transformed.
   IOBUF => IOBUF (IBUF, OBUFT): 2 instances
   LD => LDCE: 10 instances
 
-Synth Design complete | Checksum: b2a6bd97
+Synth Design complete | Checksum: 9d7d69d1
 INFO: [Common 17-83] Releasing license: Synthesis
-112 Infos, 167 Warnings, 1 Critical Warnings and 0 Errors encountered.
+52 Infos, 72 Warnings, 1 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2712.559 ; gain = 1018.066 ; free physical = 501 ; free virtual = 7042
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2269.532; main = 1935.690; forked = 384.271
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3742.785; main = 2696.562; forked = 1046.223
+synth_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:59 . Memory (MB): peak = 2752.332 ; gain = 1057.871 ; free physical = 589 ; free virtual = 10374
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2266.205; main = 1946.902; forked = 368.975
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3787.715; main = 2752.328; forked = 1035.387
 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 501 ; free virtual = 7042
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2752.332 ; gain = 0.000 ; free physical = 590 ; free virtual = 10374
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
 INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri May  9 15:45:40 2025...
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:21:29 2025...
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb
index 3d1cb5d828a3e6e04ebf438ca6a7834f268cb835..b7ca11972801aeab0f7f9b629aec837447b63e5d 100644
Binary files a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb and b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
index e09f291258fa20ed9b6025c2f9705baf3bf5e5d1..65a0e91ff72d4b66d3e23741162456f67e57a810 100644
--- a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
+++ b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date         : Fri May  9 15:45:39 2025
+| Date         : Mon May 12 16:21:28 2025
 | Host         : fl-tp-br-551 running 64-bit Ubuntu 24.04.2 LTS
 | Command      : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
 | Design       : audioProc
@@ -31,8 +31,8 @@ Table of Contents
 +-------------------------+------+-------+------------+-----------+-------+
 |        Site Type        | Used | Fixed | Prohibited | Available | Util% |
 +-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs*             |  575 |     0 |          0 |    134600 |  0.43 |
-|   LUT as Logic          |  575 |     0 |          0 |    134600 |  0.43 |
+| Slice LUTs*             |  571 |     0 |          0 |    134600 |  0.42 |
+|   LUT as Logic          |  571 |     0 |          0 |    134600 |  0.42 |
 |   LUT as Memory         |    0 |     0 |          0 |     46200 |  0.00 |
 | Slice Registers         |  903 |     0 |          0 |    269200 |  0.34 |
 |   Register as Flip Flop |  893 |     0 |          0 |    269200 |  0.33 |
@@ -119,7 +119,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
 +------------+------+-------+------------+-----------+-------+
 |  Site Type | Used | Fixed | Prohibited | Available | Util% |
 +------------+------+-------+------------+-----------+-------+
-| BUFGCTRL   |    2 |     0 |          0 |        32 |  6.25 |
+| BUFGCTRL   |    0 |     0 |          0 |        32 |  0.00 |
 | BUFIO      |    0 |     0 |          0 |        40 |  0.00 |
 | MMCME2_ADV |    0 |     0 |          0 |        10 |  0.00 |
 | PLLE2_ADV  |    0 |     0 |          0 |        10 |  0.00 |
@@ -154,14 +154,14 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
 | Ref Name | Used | Functional Category |
 +----------+------+---------------------+
 | FDCE     |  632 |        Flop & Latch |
-| LUT6     |  248 |                 LUT |
+| LUT6     |  245 |                 LUT |
 | FDRE     |  239 |        Flop & Latch |
-| LUT2     |  119 |                 LUT |
-| LUT4     |   79 |                 LUT |
+| LUT2     |  115 |                 LUT |
+| LUT4     |   81 |                 LUT |
 | MUXF7    |   64 |               MuxFx |
-| LUT5     |   52 |                 LUT |
+| LUT5     |   55 |                 LUT |
 | LUT1     |   41 |                 LUT |
-| LUT3     |   36 |                 LUT |
+| LUT3     |   34 |                 LUT |
 | MUXF8    |   32 |               MuxFx |
 | FDSE     |   20 |        Flop & Latch |
 | CARRY4   |   20 |          CarryLogic |
@@ -171,7 +171,6 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
 | OBUFT    |    2 |                  IO |
 | FDPE     |    2 |        Flop & Latch |
 | DSP48E1  |    2 |    Block Arithmetic |
-| BUFG     |    2 |               Clock |
 +----------+------+---------------------+
 
 
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
index fbbea061dc8a074720eb5402c0afa78eea108430..68fac0c6e40b37bee7c3e842830d887f4a3dce69 100644
--- a/proj/AudioProc.runs/synth_1/gen_run.xml
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -1,14 +1,14 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1746798213">
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1747059565">
   <File Type="VDS-TIMINGSUMMARY" Name="audioProc_timing_summary_synth.rpt"/>
   <File Type="RDS-DCP" Name="audioProc.dcp"/>
   <File Type="RDS-UTIL-PB" Name="audioProc_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="audioProc_utilization_synth.rpt"/>
+  <File Type="RDS-PROPCONSTRS" Name="audioProc_drc_synth.rpt"/>
+  <File Type="RDS-RDS" Name="audioProc.vds"/>
+  <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
   <File Type="VDS-TIMING-PB" Name="audioProc_timing_summary_synth.pb"/>
   <File Type="PA-TCL" Name="audioProc.tcl"/>
-  <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
-  <File Type="RDS-RDS" Name="audioProc.vds"/>
-  <File Type="RDS-PROPCONSTRS" Name="audioProc_drc_synth.rpt"/>
   <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
     <Filter Type="Srcs"/>
     <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
@@ -32,20 +32,19 @@
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
+    <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="implementation"/>
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+    <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+    <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="simulation"/>
@@ -76,13 +75,6 @@
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
-      <FileInfo>
-        <Attr Name="UserDisabled" Val="1"/>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="simulation"/>
-      </FileInfo>
-    </File>
     <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
       <FileInfo>
         <Attr Name="AutoDisabled" Val="1"/>
@@ -115,9 +107,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
-      <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred  with a larger threshold</Desc>
-    </StratHandle>
+    <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
     <Step Id="synth_design">
       <Option Id="FsmExtraction">1</Option>
       <Option Id="KeepEquivalentRegisters">1</Option>
diff --git a/proj/AudioProc.runs/synth_1/project.wdf b/proj/AudioProc.runs/synth_1/project.wdf
deleted file mode 100644
index b97fa11cc4865863ef25c6ee5f35f44a84cc1374..0000000000000000000000000000000000000000
--- a/proj/AudioProc.runs/synth_1/project.wdf
+++ /dev/null
@@ -1,32 +0,0 @@
-version:1
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3132:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:466c6f775f506572664f7074696d697a65645f48696768:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
-70726f6a656374:69705f636f72655f636f6e7461696e65725c3c6970636f72656e616d653e5c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:36:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3531616266366332333962393437613562646662663631376638343233316332:506172656e742050412070726f6a656374204944:00
-eof:2024053235
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
index 67ad7aff40b993022c34a815957b6a2dfbdd7e4b..44fa06c9e7540c7189cc1edcb374f3df0b3805ce 100644
--- a/proj/AudioProc.runs/synth_1/runme.log
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -7,12 +7,12 @@
   **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
   **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
   **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-  **** Start of session at: Fri May  9 15:43:38 2025
+  **** Start of session at: Mon May 12 16:19:30 2025
     ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
     ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 
 source audioProc.tcl -notrace
-create_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 1680.617 ; gain = 326.840 ; free physical = 276 ; free virtual = 7898
+create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:35 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 1559 ; free virtual = 11337
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/repo'; Can't find the specified path.
 If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
@@ -33,12 +33,12 @@ INFO: [Device 21-403] Loading part xc7a200tsbg484-1
 INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
 INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 2029065
+INFO: [Synth 8-7075] Helper process launched with PID 77893
 ---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2500.855 ; gain = 419.516 ; free physical = 217 ; free virtual = 6888
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2500.824 ; gain = 419.516 ; free physical = 460 ; free virtual = 10238
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:13]
-INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/.Xil/Vivado-2028801-fl-tp-br-551/realtime/clk_wiz_0_stub.vhdl:18]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/.Xil/Vivado-77565-fl-tp-br-551/realtime/clk_wiz_0_stub.vhdl:18]
 WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:87]
 WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:87]
 INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audio_init.v:24]
@@ -65,124 +65,8 @@ INFO: [Synth 8-6054] Found Dynamic range expression with variable size [/homes/g
 INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd:42]
 INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd:45]
 INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd:45]
-INFO: [Synth 8-6157] synthesizing module 'operativeUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:17]
-INFO: [Synth 8-6157] synthesizing module 'GND' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6155] done synthesizing module 'GND' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
-INFO: [Synth 8-6157] synthesizing module 'OBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
-INFO: [Synth 8-6157] synthesizing module 'LUT3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-	Parameter INIT bound to: 8'b10000000 
-INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'DSP48E1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
-	Parameter ACASCREG bound to: 0 - type: integer 
-	Parameter ADREG bound to: 1 - type: integer 
-	Parameter ALUMODEREG bound to: 0 - type: integer 
-	Parameter AREG bound to: 0 - type: integer 
-	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
-	Parameter A_INPUT bound to: DIRECT - type: string 
-	Parameter BCASCREG bound to: 0 - type: integer 
-	Parameter BREG bound to: 0 - type: integer 
-	Parameter B_INPUT bound to: DIRECT - type: string 
-	Parameter CARRYINREG bound to: 0 - type: integer 
-	Parameter CARRYINSELREG bound to: 0 - type: integer 
-	Parameter CREG bound to: 0 - type: integer 
-	Parameter DREG bound to: 1 - type: integer 
-	Parameter INMODEREG bound to: 0 - type: integer 
-	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
-	Parameter MREG bound to: 0 - type: integer 
-	Parameter OPMODEREG bound to: 0 - type: integer 
-	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
-	Parameter PREG bound to: 0 - type: integer 
-	Parameter SEL_MASK bound to: MASK - type: string 
-	Parameter SEL_PATTERN bound to: PATTERN - type: string 
-	Parameter USE_DPORT bound to: FALSE - type: string 
-	Parameter USE_MULT bound to: MULTIPLY - type: string 
-	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
-	Parameter USE_SIMD bound to: ONE48 - type: string 
-INFO: [Synth 8-6155] done synthesizing module 'DSP48E1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:39754]
-WARNING: [Synth 8-689] width (36) of port connection 'P' does not match port width (48) of module 'DSP48E1' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:422]
-WARNING: [Synth 8-7071] port 'ACOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'BCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYCASCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'CARRYOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'MULTSIGNOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'OVERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNBDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PATTERNDETECT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'PCOUT' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7071] port 'UNDERFLOW' of module 'DSP48E1' is unconnected for instance 'SC_addResult' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-WARNING: [Synth 8-7023] instance 'SC_addResult' of module 'DSP48E1' has 49 connections declared, but only 39 given [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:394]
-INFO: [Synth 8-6157] synthesizing module 'LUT2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b0110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1011111111111101 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
-	Parameter INIT bound to: 64'b1010111110100000110011111100111110101111101000001100000011000000 
-INFO: [Synth 8-6155] done synthesizing module 'LUT6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0101100000011010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1111011001101111 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0001111001111000 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1110100110010111 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0110000110000110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-	Parameter INIT bound to: 8'b01000010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1010001001000101 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1111000110001111 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b1101010110101011 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'FDCE' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
-	Parameter INIT bound to: 1'b0 
-INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
-INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
-WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:1478]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b0001 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-	Parameter INIT bound to: 8'b00000110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
-INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-	Parameter INIT bound to: 16'b0000000001101010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b1110 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'LUT5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
-	Parameter INIT bound to: 32'b00000000000000000110101010101010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
-INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-	Parameter INIT bound to: 4'b0010 
-INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
-INFO: [Synth 8-6157] synthesizing module 'VCC' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'VCC' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
-INFO: [Synth 8-6155] done synthesizing module 'operativeUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v:17]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd:55]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd:55]
 INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd:42]
 INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/fir.vhd:28]
 WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/audioProc.v:199]
@@ -231,20 +115,18 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
 WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
 WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
 ---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2589.793 ; gain = 508.453 ; free physical = 217 ; free virtual = 6789
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2584.762 ; gain = 503.453 ; free physical = 365 ; free virtual = 10143
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2607.605 ; gain = 526.266 ; free physical = 214 ; free virtual = 6786
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2602.574 ; gain = 521.266 ; free physical = 364 ; free virtual = 10141
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2607.605 ; gain = 526.266 ; free physical = 214 ; free virtual = 6786
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2602.574 ; gain = 521.266 ; free physical = 364 ; free virtual = 10141
 ---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2613.543 ; gain = 0.000 ; free physical = 216 ; free virtual = 6781
-INFO: [Netlist 29-17] Analyzing 106 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2602.574 ; gain = 0.000 ; free physical = 363 ; free virtual = 10141
 INFO: [Project 1-570] Preparing netlist for logic optimization
 
 Processing XDC Constraints
@@ -259,20 +141,20 @@ Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noel
 Finished Parsing XDC File [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/dont_touch.xdc]
 Completed Processing XDC Constraints
 
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 220 ; free virtual = 6778
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2752.324 ; gain = 0.000 ; free physical = 343 ; free virtual = 10121
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 223 ; free virtual = 6781
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2752.324 ; gain = 0.000 ; free physical = 343 ; free virtual = 10121
 ---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 218 ; free virtual = 6772
+Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 361 ; free virtual = 10139
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7a200tsbg484-1
 ---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 218 ; free virtual = 6772
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 360 ; free virtual = 10139
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
@@ -280,7 +162,7 @@ Start Applying 'set_property' XDC Constraints
 Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file  /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
 Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file  auto generated constraint).
 ---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 219 ; free virtual = 6772
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 359 ; free virtual = 10138
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
 INFO: [Synth 8-802] inferred FSM for state register 'SR_currentState_reg' in module 'controlUnit'
@@ -310,7 +192,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding
 INFO: [Synth 8-3354] encoded FSM with state register 'SR_currentState_reg' using encoding 'one-hot' in module 'controlUnit'
 WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_nextState_reg' [/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd:62]
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 224 ; free virtual = 6776
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 352 ; free virtual = 10131
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start RTL Component Statistics 
@@ -320,39 +202,44 @@ Detailed RTL Component Info :
 	   2 Input   32 Bit       Adders := 3     
 	   2 Input   31 Bit       Adders := 1     
 	   2 Input   24 Bit       Adders := 2     
+	   2 Input   16 Bit       Adders := 2     
 	   2 Input   13 Bit       Adders := 5     
 	   2 Input    7 Bit       Adders := 3     
 	   2 Input    5 Bit       Adders := 2     
-	   2 Input    4 Bit       Adders := 1     
+	   2 Input    4 Bit       Adders := 3     
 	   2 Input    3 Bit       Adders := 1     
 	   2 Input    2 Bit       Adders := 1     
 +---Registers : 
+	               36 Bit    Registers := 2     
 	               33 Bit    Registers := 1     
 	               32 Bit    Registers := 3     
 	               31 Bit    Registers := 1     
 	               24 Bit    Registers := 2     
+	               16 Bit    Registers := 34    
 	               13 Bit    Registers := 5     
 	                8 Bit    Registers := 3     
 	                7 Bit    Registers := 3     
 	                5 Bit    Registers := 4     
-	                4 Bit    Registers := 2     
+	                4 Bit    Registers := 4     
 	                3 Bit    Registers := 1     
 	                2 Bit    Registers := 2     
 	                1 Bit    Registers := 18    
 +---Muxes : 
+	   2 Input   36 Bit        Muxes := 2     
 	   2 Input   32 Bit        Muxes := 3     
 	   2 Input   24 Bit        Muxes := 2     
 	   2 Input   16 Bit        Muxes := 6     
+	  16 Input   12 Bit        Muxes := 2     
 	   2 Input    8 Bit        Muxes := 2     
 	   2 Input    5 Bit        Muxes := 9     
 	   8 Input    5 Bit        Muxes := 1     
 	   5 Input    5 Bit        Muxes := 2     
 	   9 Input    4 Bit        Muxes := 1     
 	  21 Input    4 Bit        Muxes := 1     
-	   2 Input    4 Bit        Muxes := 7     
+	   2 Input    4 Bit        Muxes := 9     
 	   5 Input    3 Bit        Muxes := 2     
 	   3 Input    2 Bit        Muxes := 1     
-	   2 Input    1 Bit        Muxes := 39    
+	   2 Input    1 Bit        Muxes := 45    
 	   4 Input    1 Bit        Muxes := 21    
 	   3 Input    1 Bit        Muxes := 5     
 	   9 Input    1 Bit        Muxes := 1     
@@ -376,6 +263,12 @@ Finished Part Resource Summary
 Start Cross Boundary and Area Optimization
 ---------------------------------------------------------------------------------
 WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: Generating DSP firUnit_1/operativeUnit_1/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_addResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
+DSP Report: operator firUnit_1/operativeUnit_1/SC_MultResult is absorbed into DSP firUnit_1/operativeUnit_1/SC_addResult.
 WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
 WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
 WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
@@ -398,25 +291,43 @@ WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or
 WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
 WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
 ---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 231 ; free virtual = 6771
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 329 ; free virtual = 10113
+---------------------------------------------------------------------------------
+ Sort Area is  firUnit_1/operativeUnit_1/SC_addResult_0 : 0 0 : 1641 1641 : Used 1 time 0
+ Sort Area is  firUnit_1/operativeUnit_1/SC_addResult_2 : 0 0 : 1641 1641 : Used 1 time 0
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name   | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B       | 16     | 13     | 36     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
+|operativeUnit | C+A*B       | 16     | 13     | 36     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 241 ; free virtual = 6782
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 327 ; free virtual = 10112
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 241 ; free virtual = 6782
+Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 329 ; free virtual = 10114
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 315 ; free virtual = 10100
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start IO Insertion
@@ -436,49 +347,49 @@ Finished Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
 ---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
 ---------------------------------------------------------------------------------
 
 DSP Final Report (the ' indicates corresponding REG is set)
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name     | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|operativeUnit_3 | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
-|operativeUnit   | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
-+----------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name   | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|operativeUnit | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
+|operativeUnit | C+A*B       | 30     | 12     | 48     | -      | 36     | 0    | 0    | 0    | -    | -     | 0    | 0    | 
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
 
 
 Report BlackBoxes: 
@@ -493,217 +404,52 @@ Report Cell Usage:
 |      |Cell    |Count |
 +------+--------+------+
 |1     |clk_wiz |     1|
-|2     |BUFG    |     2|
-|3     |CARRY4  |    20|
-|4     |DSP48E1 |     2|
-|5     |LUT1    |    41|
-|6     |LUT2    |   119|
-|7     |LUT3    |    36|
-|8     |LUT4    |    79|
-|9     |LUT5    |    52|
-|10    |LUT6    |   248|
-|11    |MUXF7   |    64|
-|12    |MUXF8   |    32|
-|13    |FDCE    |   632|
-|14    |FDPE    |     2|
-|15    |FDRE    |   239|
-|16    |FDSE    |    20|
-|17    |LD      |    10|
-|18    |IBUF    |    57|
-|19    |IOBUF   |     2|
-|20    |OBUF    |    44|
+|2     |CARRY4  |    20|
+|3     |DSP48E1 |     2|
+|4     |LUT1    |    41|
+|5     |LUT2    |   115|
+|6     |LUT3    |    34|
+|7     |LUT4    |    81|
+|8     |LUT5    |    55|
+|9     |LUT6    |   245|
+|10    |MUXF7   |    64|
+|11    |MUXF8   |    32|
+|12    |FDCE    |   632|
+|13    |FDPE    |     2|
+|14    |FDRE    |   239|
+|15    |FDSE    |    20|
+|16    |LD      |    10|
+|17    |IBUF    |     9|
+|18    |IOBUF   |     2|
+|19    |OBUF    |    10|
 +------+--------+------+
 ---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 242 ; free virtual = 6783
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.324 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 1 critical warnings and 23 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2712.559 ; gain = 526.266 ; free physical = 240 ; free virtual = 6781
-Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 2712.559 ; gain = 631.219 ; free physical = 239 ; free virtual = 6780
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 2752.324 ; gain = 521.266 ; free physical = 319 ; free virtual = 10104
+Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 2752.332 ; gain = 671.016 ; free physical = 319 ; free virtual = 10104
 INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 507 ; free virtual = 7047
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2752.332 ; gain = 0.000 ; free physical = 586 ; free virtual = 10371
 INFO: [Netlist 29-17] Analyzing 130 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[10]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[11]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[12]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[13]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[14]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[15]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[8]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[9]_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadOutput_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst 
-Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[0]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[10]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[11]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[12]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[13]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[14]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[15]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[1]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[2]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[3]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[4]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[5]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[6]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[7]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[8]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_filteredSample_OBUF[9]_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
-WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst 
-Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 501 ; free virtual = 7042
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2752.332 ; gain = 0.000 ; free physical = 589 ; free virtual = 10374
 INFO: [Project 1-111] Unisim Transformation Summary:
   A total of 12 instances were transformed.
   IOBUF => IOBUF (IBUF, OBUFT): 2 instances
   LD => LDCE: 10 instances
 
-Synth Design complete | Checksum: b2a6bd97
+Synth Design complete | Checksum: 9d7d69d1
 INFO: [Common 17-83] Releasing license: Synthesis
-112 Infos, 167 Warnings, 1 Critical Warnings and 0 Errors encountered.
+52 Infos, 72 Warnings, 1 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2712.559 ; gain = 1018.066 ; free physical = 501 ; free virtual = 7042
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2269.532; main = 1935.690; forked = 384.271
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3742.785; main = 2696.562; forked = 1046.223
+synth_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:59 . Memory (MB): peak = 2752.332 ; gain = 1057.871 ; free physical = 589 ; free virtual = 10374
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2266.205; main = 1946.902; forked = 368.975
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3787.715; main = 2752.328; forked = 1035.387
 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2712.559 ; gain = 0.000 ; free physical = 501 ; free virtual = 7042
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2752.332 ; gain = 0.000 ; free physical = 590 ; free virtual = 10374
 INFO: [Common 17-1381] The checkpoint '/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
 INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri May  9 15:45:40 2025...
+INFO: [Common 17-206] Exiting Vivado at Mon May 12 16:21:29 2025...
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
index ce7169ff4c6a7ed3110c88af61042b38b93db201..0240c68dc589e4b4d697e0982b9df4d3ca19ddfe 100644
--- a/proj/AudioProc.runs/synth_1/vivado.jou
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Fri May  9 15:43:37 2025
-# Process ID: 2028801
+# Start of session at: Mon May 12 16:19:30 2025
+# Process ID: 77565
 # Current directory: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1
 # Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
 # Log file: /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -13,12 +13,12 @@
 # Platform          :Ubuntu
 # Operating System  :Ubuntu 24.04.2 LTS
 # Processor Detail  :Intel(R) Xeon(R) CPU E5-1607 v4 @ 3.10GHz
-# CPU Frequency     :3092.855 MHz
+# CPU Frequency     :3092.499 MHz
 # CPU Physical cores:4
 # CPU Logical cores :4
 # Host memory       :16687 MB
 # Swap memory       :4294 MB
 # Total Virtual     :20982 MB
-# Available Virtual :8828 MB
+# Available Virtual :12524 MB
 #-----------------------------------------------------------
 source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
index 55d7fc82689906a9f5e98c4ba9bb32cfbb8a753c..1244e88892d8b613e1f6f1346423257391e4e293 100644
Binary files a/proj/AudioProc.runs/synth_1/vivado.pb and b/proj/AudioProc.runs/synth_1/vivado.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/.usf.tcl_error.log b/proj/AudioProc.sim/sim_1/behav/xsim/.usf.tcl_error.log
deleted file mode 100644
index 2e66011d667a8de754d8532ed7804dd1262f6e26..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/.usf.tcl_error.log
+++ /dev/null
@@ -1,21 +0,0 @@
-********************************************************************************
-* Unified simulation Tcl App stack trace dump
-*
-* File: .usf.tcl_error.log (Fri May  9 16:11:27 2025)
-*
-* This file is generated by the unified simulation automation and contains the
-* tcl stack trace of error returned by the simulator App for the current run.
-*
-********************************************************************************
-1
-    while executing
-"catch {rdi::execute_script $scr_file} error_log"
-    (procedure "xcs_exec_script" line 12)
-    invoked from within
-"xcs_exec_script $scr_file error_log"
-    (procedure "usf_launch_script" line 42)
-    invoked from within
-"usf_launch_script "xsim" $step"
-    (procedure "tclapp::xilinx::xsim::compile" line 13)
-    invoked from within
-"tclapp::xilinx::xsim::compile { -simset sim_1 -mode behavioral -run_dir /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc..."
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..96e359f34588f46348d12fe1fbce0b937a58d6c2 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
index 807b5f853f6184fd9d20326c5662b0669dae1a91..b08ae15f9703c7075f302400a1f9c7b99a21177a 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Fri May 09 16:11:17 CEST 2025
+# Generated by Vivado on Mon May 12 16:13:22 CEST 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -16,13 +16,9 @@
 #
 # ****************************************************************************
 set -Eeuo pipefail
-# compile Verilog/System Verilog design sources
-echo "xvlog --incr --relax -prj tb_firUnit_vlog.prj"
-xvlog --incr --relax -prj tb_firUnit_vlog.prj 2>&1 | tee compile.log
-
 # compile VHDL design sources
 echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
-xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee -a compile.log
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee compile.log
 
 echo "Waiting for jobs to finish..."
 echo "No pending jobs, compilation finished."
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
index b9631eaa358c938237e5b4a70ed9e419f8435c49..b867df2ccdc367813708de0bded87f946e1f9592 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Fri May 09 15:36:50 CEST 2025
+# Generated by Vivado on Mon May 12 16:13:24 CEST 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -17,6 +17,6 @@
 # ****************************************************************************
 set -Eeuo pipefail
 # elaborate design
-echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log"
-xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
 
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
deleted file mode 100755
index ed3b249ceef65a0d1b42790def9ee8179363679c..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
+++ /dev/null
@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
index 56031989449c826508186525a0acc4bad7a0083e..f2e4a52ef7b21a00a5b8a8e17c0a336b2603c263 100755
--- a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for simulating the design by launching the simulator
 #
-# Generated by Vivado on Fri May 09 15:24:26 CEST 2025
+# Generated by Vivado on Mon May 12 16:13:27 CEST 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index 8f7c598c123a2970f4b78c30de3d13847520a48b..82861cda6674a71f41d4a8418ec1a18c760f9915 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb and b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
index f5164303db8b7813dd76fdb363b7c18c0c679809..0107b4e0d82614c83b8f672cdff5fbeac1c3cfc2 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -1,6 +1,7 @@
 # compile vhdl design source files
 vhdl xil_defaultlib  \
 "../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
 "../../../../../src/hdl/firUnit.vhd" \
 "../../../../../src/hdl/tb_firUnit.vhd" \
 
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
deleted file mode 100644
index 4918d41c886ff6e9c7b433572c2692552e42d4f0..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
+++ /dev/null
@@ -1,9 +0,0 @@
-# compile verilog/system verilog design source files
-verilog xil_defaultlib  \
-"../../../../../src/hdl/operativeUnit.v" \
-
-# compile glbl module
-verilog xil_defaultlib "glbl.v"
-
-# Do not sort compile order
-nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb
index 6ac7f42e766b1bcdec47a583a2bc5b6333b536d4..f17fb2dfa33c0317a5b8bf49cd8cf2f51e64bf31 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb and b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
index 2965ab3b73825075d89f3fba7755ebff3606c69a..8a25a911b8deeb63be565a8d140a089d2d79bd2f 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -1 +1 @@
---incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" "xil_defaultlib.glbl" -log "elaborate.log" 
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log" 
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
index 155c2ebeaa75e09b24b5ff995730472d1e16cf1a..b9ed925465813ae56ca1ee01f4e1d7adfb536fff 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
index 82891810cefac246dd5535788ebac91bf57678ef..c9f38b089b7890e304c5c8351f5a219f05e35b77 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -54,595 +54,40 @@
 #endif
 typedef void (*funcp)(char *, char *);
 extern int main(int, char**);
-IKI_DLLESPEC extern void execute_2(char*, char *);
-IKI_DLLESPEC extern void execute_3(char*, char *);
-IKI_DLLESPEC extern void execute_4(char*, char *);
-IKI_DLLESPEC extern void execute_5(char*, char *);
-IKI_DLLESPEC extern void execute_6(char*, char *);
-IKI_DLLESPEC extern void execute_7(char*, char *);
-IKI_DLLESPEC extern void execute_8(char*, char *);
-IKI_DLLESPEC extern void execute_9(char*, char *);
-IKI_DLLESPEC extern void execute_10(char*, char *);
-IKI_DLLESPEC extern void execute_11(char*, char *);
-IKI_DLLESPEC extern void execute_21(char*, char *);
-IKI_DLLESPEC extern void execute_22(char*, char *);
-IKI_DLLESPEC extern void execute_23(char*, char *);
-IKI_DLLESPEC extern void execute_24(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
 IKI_DLLESPEC extern void execute_27(char*, char *);
 IKI_DLLESPEC extern void execute_28(char*, char *);
 IKI_DLLESPEC extern void execute_29(char*, char *);
-IKI_DLLESPEC extern void execute_30(char*, char *);
-IKI_DLLESPEC extern void execute_31(char*, char *);
 IKI_DLLESPEC extern void execute_32(char*, char *);
 IKI_DLLESPEC extern void execute_33(char*, char *);
 IKI_DLLESPEC extern void execute_34(char*, char *);
 IKI_DLLESPEC extern void execute_35(char*, char *);
-IKI_DLLESPEC extern void execute_3821(char*, char *);
-IKI_DLLESPEC extern void execute_3822(char*, char *);
-IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
-IKI_DLLESPEC extern void execute_1958(char*, char *);
-IKI_DLLESPEC extern void execute_41(char*, char *);
-IKI_DLLESPEC extern void execute_1959(char*, char *);
-IKI_DLLESPEC extern void execute_89(char*, char *);
-IKI_DLLESPEC extern void execute_1983(char*, char *);
-IKI_DLLESPEC extern void execute_1984(char*, char *);
-IKI_DLLESPEC extern void execute_1985(char*, char *);
-IKI_DLLESPEC extern void execute_124(char*, char *);
-IKI_DLLESPEC extern void execute_2035(char*, char *);
-IKI_DLLESPEC extern void execute_2036(char*, char *);
-IKI_DLLESPEC extern void execute_2037(char*, char *);
-IKI_DLLESPEC extern void execute_2038(char*, char *);
-IKI_DLLESPEC extern void execute_2039(char*, char *);
-IKI_DLLESPEC extern void execute_2040(char*, char *);
-IKI_DLLESPEC extern void execute_2041(char*, char *);
-IKI_DLLESPEC extern void execute_2042(char*, char *);
-IKI_DLLESPEC extern void execute_2034(char*, char *);
-IKI_DLLESPEC extern void execute_126(char*, char *);
-IKI_DLLESPEC extern void execute_127(char*, char *);
-IKI_DLLESPEC extern void execute_128(char*, char *);
-IKI_DLLESPEC extern void execute_129(char*, char *);
-IKI_DLLESPEC extern void execute_130(char*, char *);
-IKI_DLLESPEC extern void execute_131(char*, char *);
-IKI_DLLESPEC extern void execute_132(char*, char *);
-IKI_DLLESPEC extern void execute_133(char*, char *);
-IKI_DLLESPEC extern void execute_134(char*, char *);
-IKI_DLLESPEC extern void execute_135(char*, char *);
-IKI_DLLESPEC extern void execute_136(char*, char *);
-IKI_DLLESPEC extern void execute_137(char*, char *);
-IKI_DLLESPEC extern void execute_138(char*, char *);
-IKI_DLLESPEC extern void execute_139(char*, char *);
-IKI_DLLESPEC extern void execute_140(char*, char *);
-IKI_DLLESPEC extern void execute_141(char*, char *);
-IKI_DLLESPEC extern void execute_142(char*, char *);
-IKI_DLLESPEC extern void execute_143(char*, char *);
-IKI_DLLESPEC extern void execute_144(char*, char *);
-IKI_DLLESPEC extern void execute_145(char*, char *);
-IKI_DLLESPEC extern void execute_146(char*, char *);
-IKI_DLLESPEC extern void execute_147(char*, char *);
-IKI_DLLESPEC extern void execute_148(char*, char *);
-IKI_DLLESPEC extern void execute_149(char*, char *);
-IKI_DLLESPEC extern void execute_150(char*, char *);
-IKI_DLLESPEC extern void execute_151(char*, char *);
-IKI_DLLESPEC extern void execute_152(char*, char *);
-IKI_DLLESPEC extern void execute_153(char*, char *);
-IKI_DLLESPEC extern void execute_156(char*, char *);
-IKI_DLLESPEC extern void execute_157(char*, char *);
-IKI_DLLESPEC extern void execute_158(char*, char *);
-IKI_DLLESPEC extern void execute_159(char*, char *);
-IKI_DLLESPEC extern void execute_160(char*, char *);
-IKI_DLLESPEC extern void execute_161(char*, char *);
-IKI_DLLESPEC extern void execute_162(char*, char *);
-IKI_DLLESPEC extern void execute_163(char*, char *);
-IKI_DLLESPEC extern void execute_164(char*, char *);
-IKI_DLLESPEC extern void execute_165(char*, char *);
-IKI_DLLESPEC extern void execute_166(char*, char *);
-IKI_DLLESPEC extern void execute_167(char*, char *);
-IKI_DLLESPEC extern void execute_168(char*, char *);
-IKI_DLLESPEC extern void execute_169(char*, char *);
-IKI_DLLESPEC extern void execute_170(char*, char *);
-IKI_DLLESPEC extern void execute_171(char*, char *);
-IKI_DLLESPEC extern void execute_2043(char*, char *);
-IKI_DLLESPEC extern void execute_2044(char*, char *);
-IKI_DLLESPEC extern void execute_2045(char*, char *);
-IKI_DLLESPEC extern void execute_2046(char*, char *);
-IKI_DLLESPEC extern void execute_2047(char*, char *);
-IKI_DLLESPEC extern void execute_2048(char*, char *);
-IKI_DLLESPEC extern void execute_2049(char*, char *);
-IKI_DLLESPEC extern void execute_2050(char*, char *);
-IKI_DLLESPEC extern void execute_2051(char*, char *);
-IKI_DLLESPEC extern void execute_2052(char*, char *);
-IKI_DLLESPEC extern void execute_2053(char*, char *);
-IKI_DLLESPEC extern void execute_2054(char*, char *);
-IKI_DLLESPEC extern void execute_2055(char*, char *);
-IKI_DLLESPEC extern void execute_2056(char*, char *);
-IKI_DLLESPEC extern void execute_2057(char*, char *);
-IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
-IKI_DLLESPEC extern void vlog_simple_process_execute_1_fast_no_reg_no_agg(char*, char*, char*);
-IKI_DLLESPEC extern void execute_2098(char*, char *);
-IKI_DLLESPEC extern void execute_2103(char*, char *);
-IKI_DLLESPEC extern void execute_2118(char*, char *);
-IKI_DLLESPEC extern void execute_2120(char*, char *);
-IKI_DLLESPEC extern void execute_2122(char*, char *);
-IKI_DLLESPEC extern void execute_2134(char*, char *);
-IKI_DLLESPEC extern void execute_2135(char*, char *);
-IKI_DLLESPEC extern void execute_2136(char*, char *);
-IKI_DLLESPEC extern void execute_2138(char*, char *);
-IKI_DLLESPEC extern void execute_2139(char*, char *);
-IKI_DLLESPEC extern void execute_2140(char*, char *);
-IKI_DLLESPEC extern void execute_2141(char*, char *);
-IKI_DLLESPEC extern void execute_2142(char*, char *);
-IKI_DLLESPEC extern void execute_2143(char*, char *);
-IKI_DLLESPEC extern void execute_2144(char*, char *);
-IKI_DLLESPEC extern void execute_2145(char*, char *);
-IKI_DLLESPEC extern void execute_2147(char*, char *);
-IKI_DLLESPEC extern void execute_2148(char*, char *);
-IKI_DLLESPEC extern void execute_2149(char*, char *);
-IKI_DLLESPEC extern void execute_2150(char*, char *);
-IKI_DLLESPEC extern void execute_2151(char*, char *);
-IKI_DLLESPEC extern void execute_2152(char*, char *);
-IKI_DLLESPEC extern void execute_2153(char*, char *);
-IKI_DLLESPEC extern void execute_2154(char*, char *);
-IKI_DLLESPEC extern void execute_2155(char*, char *);
-IKI_DLLESPEC extern void execute_2156(char*, char *);
-IKI_DLLESPEC extern void execute_2157(char*, char *);
-IKI_DLLESPEC extern void execute_2162(char*, char *);
-IKI_DLLESPEC extern void execute_2163(char*, char *);
-IKI_DLLESPEC extern void execute_2164(char*, char *);
-IKI_DLLESPEC extern void execute_2165(char*, char *);
-IKI_DLLESPEC extern void execute_2166(char*, char *);
-IKI_DLLESPEC extern void execute_2167(char*, char *);
-IKI_DLLESPEC extern void execute_2168(char*, char *);
-IKI_DLLESPEC extern void execute_2169(char*, char *);
-IKI_DLLESPEC extern void execute_2170(char*, char *);
-IKI_DLLESPEC extern void execute_2171(char*, char *);
-IKI_DLLESPEC extern void execute_2172(char*, char *);
-IKI_DLLESPEC extern void execute_2173(char*, char *);
-IKI_DLLESPEC extern void execute_2174(char*, char *);
-IKI_DLLESPEC extern void execute_2175(char*, char *);
-IKI_DLLESPEC extern void execute_2176(char*, char *);
-IKI_DLLESPEC extern void execute_2177(char*, char *);
-IKI_DLLESPEC extern void execute_2178(char*, char *);
-IKI_DLLESPEC extern void execute_2179(char*, char *);
-IKI_DLLESPEC extern void execute_2180(char*, char *);
-IKI_DLLESPEC extern void execute_2181(char*, char *);
-IKI_DLLESPEC extern void execute_2182(char*, char *);
-IKI_DLLESPEC extern void execute_2183(char*, char *);
-IKI_DLLESPEC extern void execute_2184(char*, char *);
-IKI_DLLESPEC extern void execute_174(char*, char *);
-IKI_DLLESPEC extern void execute_2186(char*, char *);
-IKI_DLLESPEC extern void execute_2187(char*, char *);
-IKI_DLLESPEC extern void execute_2188(char*, char *);
-IKI_DLLESPEC extern void execute_2189(char*, char *);
-IKI_DLLESPEC extern void execute_2185(char*, char *);
-IKI_DLLESPEC extern void execute_177(char*, char *);
-IKI_DLLESPEC extern void execute_178(char*, char *);
-IKI_DLLESPEC extern void execute_181(char*, char *);
-IKI_DLLESPEC extern void execute_182(char*, char *);
-IKI_DLLESPEC extern void execute_288(char*, char *);
-IKI_DLLESPEC extern void execute_324(char*, char *);
-IKI_DLLESPEC extern void execute_573(char*, char *);
-IKI_DLLESPEC extern void execute_574(char*, char *);
-IKI_DLLESPEC extern void execute_575(char*, char *);
-IKI_DLLESPEC extern void execute_2330(char*, char *);
-IKI_DLLESPEC extern void execute_2331(char*, char *);
-IKI_DLLESPEC extern void execute_2332(char*, char *);
-IKI_DLLESPEC extern void execute_2333(char*, char *);
-IKI_DLLESPEC extern void execute_2342(char*, char *);
-IKI_DLLESPEC extern void execute_2343(char*, char *);
-IKI_DLLESPEC extern void execute_2344(char*, char *);
-IKI_DLLESPEC extern void execute_2347(char*, char *);
-IKI_DLLESPEC extern void execute_2348(char*, char *);
-IKI_DLLESPEC extern void execute_2349(char*, char *);
-IKI_DLLESPEC extern void execute_2350(char*, char *);
-IKI_DLLESPEC extern void execute_656(char*, char *);
-IKI_DLLESPEC extern void execute_657(char*, char *);
-IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
 IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_205(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_206(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_207(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_208(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_215(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_237(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_270(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_350(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_994(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1000(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1006(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1020(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1026(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1032(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1038(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1051(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1057(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1063(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1078(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1084(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1090(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1096(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1110(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1116(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1159(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1165(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1171(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1177(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1183(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1189(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1195(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1201(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1207(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1213(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1219(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1225(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1231(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1237(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1243(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1249(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1255(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1261(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1267(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1273(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1279(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1285(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1291(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1297(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1303(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1309(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1315(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1321(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1327(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1333(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1339(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1345(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1351(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1357(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1363(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1369(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1375(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1381(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1387(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1393(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1399(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1405(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1411(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1417(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1423(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1429(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1435(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1441(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1447(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1453(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1459(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1465(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1471(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1477(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1483(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1489(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1495(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1501(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1507(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1513(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1519(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1525(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1531(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1537(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1543(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1549(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1555(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1561(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1567(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1573(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1579(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1585(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1591(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1597(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1603(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1609(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1615(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1621(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1627(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1633(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1639(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1645(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1651(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1657(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1663(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1669(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1675(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1681(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1687(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1693(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1699(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1705(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1711(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1717(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1723(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1729(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1735(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1741(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1747(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1753(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1759(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1765(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1771(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1777(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1783(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1789(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1795(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1801(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1807(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1813(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1819(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1825(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1831(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1837(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1843(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1849(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1855(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1861(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1867(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1873(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1879(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1885(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1891(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1897(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1903(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1909(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1915(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1921(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1927(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1933(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1939(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1945(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1951(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1957(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1963(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1969(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1975(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1981(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1987(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1993(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_1999(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2005(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2011(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2017(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2023(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2029(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2035(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2041(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2047(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2053(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2059(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2065(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2071(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2077(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2083(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2089(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2095(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2101(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2107(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2113(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2119(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2125(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2131(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2137(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2143(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2149(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2155(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2161(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2167(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2173(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2179(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2185(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2191(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2197(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2203(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2209(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2215(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2221(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2227(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2233(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2239(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2245(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2251(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2257(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2263(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2269(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2275(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2281(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2287(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2293(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2299(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2305(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2311(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2317(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2323(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2329(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2335(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2341(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2347(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2353(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2359(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2365(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2371(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2377(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2383(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2389(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2395(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2401(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2407(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2413(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2419(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2425(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2431(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2437(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2443(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2449(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2455(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2461(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2467(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2473(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2479(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2485(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2491(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2497(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2503(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2509(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2515(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2521(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2527(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2533(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2539(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2545(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2551(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2557(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2563(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2569(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2575(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2581(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2587(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2593(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2599(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2605(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2611(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2617(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2623(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2629(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2635(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2641(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2647(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2653(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2659(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2665(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2671(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2677(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2683(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2689(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2695(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2701(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2707(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2713(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2941(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2947(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2953(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2959(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2965(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2971(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2977(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2983(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2989(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_2995(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3001(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3007(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3013(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3019(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3025(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3031(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3037(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3043(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3049(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3055(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3061(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3067(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3073(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3079(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3085(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3091(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3097(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3103(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3109(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3115(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3121(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3127(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3133(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3139(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3145(char*, char*, unsigned, unsigned, unsigned);
-IKI_DLLESPEC extern void transaction_3151(char*, char*, unsigned, unsigned, unsigned);
-funcp funcTab[581] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_3821, (funcp)execute_3822, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_1958, (funcp)execute_41, (funcp)execute_1959, (funcp)execute_89, (funcp)execute_1983, (funcp)execute_1984, (funcp)execute_1985, (funcp)execute_124, (funcp)execute_2035, (funcp)execute_2036, (funcp)execute_2037, (funcp)execute_2038, (funcp)execute_2039, (funcp)execute_2040, (funcp)execute_2041, (funcp)execute_2042, (funcp)execute_2034, (funcp)execute_126, (funcp)execute_127, (funcp)execute_128, (funcp)execute_129, (funcp)execute_130, (funcp)execute_131, (funcp)execute_132, (funcp)execute_133, (funcp)execute_134, (funcp)execute_135, (funcp)execute_136, (funcp)execute_137, (funcp)execute_138, (funcp)execute_139, (funcp)execute_140, (funcp)execute_141, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_145, (funcp)execute_146, (funcp)execute_147, (funcp)execute_148, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_152, (funcp)execute_153, (funcp)execute_156, (funcp)execute_157, (funcp)execute_158, (funcp)execute_159, (funcp)execute_160, (funcp)execute_161, (funcp)execute_162, (funcp)execute_163, (funcp)execute_164, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_168, (funcp)execute_169, (funcp)execute_170, (funcp)execute_171, (funcp)execute_2043, (funcp)execute_2044, (funcp)execute_2045, (funcp)execute_2046, (funcp)execute_2047, (funcp)execute_2048, (funcp)execute_2049, (funcp)execute_2050, (funcp)execute_2051, (funcp)execute_2052, (funcp)execute_2053, (funcp)execute_2054, (funcp)execute_2055, (funcp)execute_2056, (funcp)execute_2057, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)vlog_simple_process_execute_1_fast_no_reg_no_agg, (funcp)execute_2098, (funcp)execute_2103, (funcp)execute_2118, (funcp)execute_2120, (funcp)execute_2122, (funcp)execute_2134, (funcp)execute_2135, (funcp)execute_2136, (funcp)execute_2138, (funcp)execute_2139, (funcp)execute_2140, (funcp)execute_2141, (funcp)execute_2142, (funcp)execute_2143, (funcp)execute_2144, (funcp)execute_2145, (funcp)execute_2147, (funcp)execute_2148, (funcp)execute_2149, (funcp)execute_2150, (funcp)execute_2151, (funcp)execute_2152, (funcp)execute_2153, (funcp)execute_2154, (funcp)execute_2155, (funcp)execute_2156, (funcp)execute_2157, (funcp)execute_2162, (funcp)execute_2163, (funcp)execute_2164, (funcp)execute_2165, (funcp)execute_2166, (funcp)execute_2167, (funcp)execute_2168, (funcp)execute_2169, (funcp)execute_2170, (funcp)execute_2171, (funcp)execute_2172, (funcp)execute_2173, (funcp)execute_2174, (funcp)execute_2175, (funcp)execute_2176, (funcp)execute_2177, (funcp)execute_2178, (funcp)execute_2179, (funcp)execute_2180, (funcp)execute_2181, (funcp)execute_2182, (funcp)execute_2183, (funcp)execute_2184, (funcp)execute_174, (funcp)execute_2186, (funcp)execute_2187, (funcp)execute_2188, (funcp)execute_2189, (funcp)execute_2185, (funcp)execute_177, (funcp)execute_178, (funcp)execute_181, (funcp)execute_182, (funcp)execute_288, (funcp)execute_324, (funcp)execute_573, (funcp)execute_574, (funcp)execute_575, (funcp)execute_2330, (funcp)execute_2331, (funcp)execute_2332, (funcp)execute_2333, (funcp)execute_2342, (funcp)execute_2343, (funcp)execute_2344, (funcp)execute_2347, (funcp)execute_2348, (funcp)execute_2349, (funcp)execute_2350, (funcp)execute_656, (funcp)execute_657, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_38, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_73, (funcp)transaction_183, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_205, (funcp)transaction_206, (funcp)transaction_207, (funcp)transaction_208, (funcp)transaction_215, (funcp)transaction_232, (funcp)transaction_237, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_270, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_298, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_306, (funcp)transaction_309, (funcp)transaction_311, (funcp)transaction_313, (funcp)transaction_315, (funcp)transaction_320, (funcp)transaction_323, (funcp)transaction_329, (funcp)transaction_334, (funcp)transaction_350, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_366, (funcp)transaction_994, (funcp)transaction_1000, (funcp)transaction_1006, (funcp)transaction_1020, (funcp)transaction_1026, (funcp)transaction_1032, (funcp)transaction_1038, (funcp)transaction_1051, (funcp)transaction_1057, (funcp)transaction_1063, (funcp)transaction_1078, (funcp)transaction_1084, (funcp)transaction_1090, (funcp)transaction_1096, (funcp)transaction_1110, (funcp)transaction_1116, (funcp)transaction_1159, (funcp)transaction_1165, (funcp)transaction_1171, (funcp)transaction_1177, (funcp)transaction_1183, (funcp)transaction_1189, (funcp)transaction_1195, (funcp)transaction_1201, (funcp)transaction_1207, (funcp)transaction_1213, (funcp)transaction_1219, (funcp)transaction_1225, (funcp)transaction_1231, (funcp)transaction_1237, (funcp)transaction_1243, (funcp)transaction_1249, (funcp)transaction_1255, (funcp)transaction_1261, (funcp)transaction_1267, (funcp)transaction_1273, (funcp)transaction_1279, (funcp)transaction_1285, (funcp)transaction_1291, (funcp)transaction_1297, (funcp)transaction_1303, (funcp)transaction_1309, (funcp)transaction_1315, (funcp)transaction_1321, (funcp)transaction_1327, (funcp)transaction_1333, (funcp)transaction_1339, (funcp)transaction_1345, (funcp)transaction_1351, (funcp)transaction_1357, (funcp)transaction_1363, (funcp)transaction_1369, (funcp)transaction_1375, (funcp)transaction_1381, (funcp)transaction_1387, (funcp)transaction_1393, (funcp)transaction_1399, (funcp)transaction_1405, (funcp)transaction_1411, (funcp)transaction_1417, (funcp)transaction_1423, (funcp)transaction_1429, (funcp)transaction_1435, (funcp)transaction_1441, (funcp)transaction_1447, (funcp)transaction_1453, (funcp)transaction_1459, (funcp)transaction_1465, (funcp)transaction_1471, (funcp)transaction_1477, (funcp)transaction_1483, (funcp)transaction_1489, (funcp)transaction_1495, (funcp)transaction_1501, (funcp)transaction_1507, (funcp)transaction_1513, (funcp)transaction_1519, (funcp)transaction_1525, (funcp)transaction_1531, (funcp)transaction_1537, (funcp)transaction_1543, (funcp)transaction_1549, (funcp)transaction_1555, (funcp)transaction_1561, (funcp)transaction_1567, (funcp)transaction_1573, (funcp)transaction_1579, (funcp)transaction_1585, (funcp)transaction_1591, (funcp)transaction_1597, (funcp)transaction_1603, (funcp)transaction_1609, (funcp)transaction_1615, (funcp)transaction_1621, (funcp)transaction_1627, (funcp)transaction_1633, (funcp)transaction_1639, (funcp)transaction_1645, (funcp)transaction_1651, (funcp)transaction_1657, (funcp)transaction_1663, (funcp)transaction_1669, (funcp)transaction_1675, (funcp)transaction_1681, (funcp)transaction_1687, (funcp)transaction_1693, (funcp)transaction_1699, (funcp)transaction_1705, (funcp)transaction_1711, (funcp)transaction_1717, (funcp)transaction_1723, (funcp)transaction_1729, (funcp)transaction_1735, (funcp)transaction_1741, (funcp)transaction_1747, (funcp)transaction_1753, (funcp)transaction_1759, (funcp)transaction_1765, (funcp)transaction_1771, (funcp)transaction_1777, (funcp)transaction_1783, (funcp)transaction_1789, (funcp)transaction_1795, (funcp)transaction_1801, (funcp)transaction_1807, (funcp)transaction_1813, (funcp)transaction_1819, (funcp)transaction_1825, (funcp)transaction_1831, (funcp)transaction_1837, (funcp)transaction_1843, (funcp)transaction_1849, (funcp)transaction_1855, (funcp)transaction_1861, (funcp)transaction_1867, (funcp)transaction_1873, (funcp)transaction_1879, (funcp)transaction_1885, (funcp)transaction_1891, (funcp)transaction_1897, (funcp)transaction_1903, (funcp)transaction_1909, (funcp)transaction_1915, (funcp)transaction_1921, (funcp)transaction_1927, (funcp)transaction_1933, (funcp)transaction_1939, (funcp)transaction_1945, (funcp)transaction_1951, (funcp)transaction_1957, (funcp)transaction_1963, (funcp)transaction_1969, (funcp)transaction_1975, (funcp)transaction_1981, (funcp)transaction_1987, (funcp)transaction_1993, (funcp)transaction_1999, (funcp)transaction_2005, (funcp)transaction_2011, (funcp)transaction_2017, (funcp)transaction_2023, (funcp)transaction_2029, (funcp)transaction_2035, (funcp)transaction_2041, (funcp)transaction_2047, (funcp)transaction_2053, (funcp)transaction_2059, (funcp)transaction_2065, (funcp)transaction_2071, (funcp)transaction_2077, (funcp)transaction_2083, (funcp)transaction_2089, (funcp)transaction_2095, (funcp)transaction_2101, (funcp)transaction_2107, (funcp)transaction_2113, (funcp)transaction_2119, (funcp)transaction_2125, (funcp)transaction_2131, (funcp)transaction_2137, (funcp)transaction_2143, (funcp)transaction_2149, (funcp)transaction_2155, (funcp)transaction_2161, (funcp)transaction_2167, (funcp)transaction_2173, (funcp)transaction_2179, (funcp)transaction_2185, (funcp)transaction_2191, (funcp)transaction_2197, (funcp)transaction_2203, (funcp)transaction_2209, (funcp)transaction_2215, (funcp)transaction_2221, (funcp)transaction_2227, (funcp)transaction_2233, (funcp)transaction_2239, (funcp)transaction_2245, (funcp)transaction_2251, (funcp)transaction_2257, (funcp)transaction_2263, (funcp)transaction_2269, (funcp)transaction_2275, (funcp)transaction_2281, (funcp)transaction_2287, (funcp)transaction_2293, (funcp)transaction_2299, (funcp)transaction_2305, (funcp)transaction_2311, (funcp)transaction_2317, (funcp)transaction_2323, (funcp)transaction_2329, (funcp)transaction_2335, (funcp)transaction_2341, (funcp)transaction_2347, (funcp)transaction_2353, (funcp)transaction_2359, (funcp)transaction_2365, (funcp)transaction_2371, (funcp)transaction_2377, (funcp)transaction_2383, (funcp)transaction_2389, (funcp)transaction_2395, (funcp)transaction_2401, (funcp)transaction_2407, (funcp)transaction_2413, (funcp)transaction_2419, (funcp)transaction_2425, (funcp)transaction_2431, (funcp)transaction_2437, (funcp)transaction_2443, (funcp)transaction_2449, (funcp)transaction_2455, (funcp)transaction_2461, (funcp)transaction_2467, (funcp)transaction_2473, (funcp)transaction_2479, (funcp)transaction_2485, (funcp)transaction_2491, (funcp)transaction_2497, (funcp)transaction_2503, (funcp)transaction_2509, (funcp)transaction_2515, (funcp)transaction_2521, (funcp)transaction_2527, (funcp)transaction_2533, (funcp)transaction_2539, (funcp)transaction_2545, (funcp)transaction_2551, (funcp)transaction_2557, (funcp)transaction_2563, (funcp)transaction_2569, (funcp)transaction_2575, (funcp)transaction_2581, (funcp)transaction_2587, (funcp)transaction_2593, (funcp)transaction_2599, (funcp)transaction_2605, (funcp)transaction_2611, (funcp)transaction_2617, (funcp)transaction_2623, (funcp)transaction_2629, (funcp)transaction_2635, (funcp)transaction_2641, (funcp)transaction_2647, (funcp)transaction_2653, (funcp)transaction_2659, (funcp)transaction_2665, (funcp)transaction_2671, (funcp)transaction_2677, (funcp)transaction_2683, (funcp)transaction_2689, (funcp)transaction_2695, (funcp)transaction_2701, (funcp)transaction_2707, (funcp)transaction_2713, (funcp)transaction_2941, (funcp)transaction_2947, (funcp)transaction_2953, (funcp)transaction_2959, (funcp)transaction_2965, (funcp)transaction_2971, (funcp)transaction_2977, (funcp)transaction_2983, (funcp)transaction_2989, (funcp)transaction_2995, (funcp)transaction_3001, (funcp)transaction_3007, (funcp)transaction_3013, (funcp)transaction_3019, (funcp)transaction_3025, (funcp)transaction_3031, (funcp)transaction_3037, (funcp)transaction_3043, (funcp)transaction_3049, (funcp)transaction_3055, (funcp)transaction_3061, (funcp)transaction_3067, (funcp)transaction_3073, (funcp)transaction_3079, (funcp)transaction_3085, (funcp)transaction_3091, (funcp)transaction_3097, (funcp)transaction_3103, (funcp)transaction_3109, (funcp)transaction_3115, (funcp)transaction_3121, (funcp)transaction_3127, (funcp)transaction_3133, (funcp)transaction_3139, (funcp)transaction_3145, (funcp)transaction_3151};
-const int NumRelocateId= 581;
+funcp funcTab[26] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 26;
 
 void relocate(char *dp)
 {
-	iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc",  (void **)funcTab, 581);
-	iki_vhdl_file_variable_register(dp + 701048);
-	iki_vhdl_file_variable_register(dp + 701104);
+	iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc",  (void **)funcTab, 26);
+	iki_vhdl_file_variable_register(dp + 8352);
+	iki_vhdl_file_variable_register(dp + 8408);
 
 
 	/*Populate the transaction function pointer field in the whole net structure */
@@ -653,37 +98,10 @@ void sensitize(char *dp)
 	iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
 }
 
-	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
-
-void wrapper_func_0(char *dp)
-
-{
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 706376, dp + 710584, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 706432, dp + 711536, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 706488, dp + 711088, 0, 15, 0, 15, 16, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707760, dp + 711312, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707816, dp + 710864, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707872, dp + 710752, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707928, dp + 710976, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 707984, dp + 711424, 0, 0, 0, 0, 1, 1);
-
-	iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 708040, dp + 711200, 0, 0, 0, 0, 1, 1);
-
-}
-
 void simulate(char *dp)
 {
 		iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
-	wrapper_func_0(dp);
-
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
 	iki_execute_processes();
 
 	// Schedule resolution functions for the multiply driven Verilog nets that have strength
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
index a9f97708d37957c5b7332b318e1a8328f23eb48b..6347e4da7209e8b0908794cf5461bd74caade9b7 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
index 8cb9f39b67e8495574faef971c4c5019ebfeec70..a0177e5dce410b65ad59eafbd2317f09defec9ec 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
index dd6fc9b8e9f10bef048e3840ebe619e95cb8586c..2badf5b054626bfb3433f77fc3e16d06083d0a51 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
index fc47b423b3ee70d11db834f8c2a490b5d1c6d05a..cd7cbc3c66ff96d4022bc58d6566d044618a7e67 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
index e5642f4fa126f61de851eac7698e885b8350f1ee..77d435ab74e2d64c897adebaaddb757b480ed421 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -1,8 +1,8 @@
 
 { 
-    crc :  7748289134640279419  , 
+    crc :  12959059154649624264  , 
     ccp_crc :  0  , 
-    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl" , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" , 
     buildDate : "May 22 2024" , 
     buildTime : "18:54:44" , 
     linkCmd : "/usr/bin/gcc -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/tb_firUnit_behav/xsimk\"   \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel    -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" , 
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
index 9381670ae9beafb75a9f01586a403df298a09381..3fbbbea3e68fae40bedbb9cf84705b5f4d2ee5be 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
index 57a1c98a5f6d4cad2df1f5c52fb8d6f99ce7db99..6dc1deb65a85fafe2dcea36f677983510a180e28 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
index 360308b6976beedd970291f39bc83996587fe718..89c53562a84ef2da97b3c2c7cadbb34ec6aa694e 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
index 524490d8222703b36418f578f10d00c3a1f2af39..ec4fe88fc59b7fb90f125d035291ee4f67594f23 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
index bbac340f36291bf728d22a4898240931d7600b1c..3bb6a10cef2cf46bbee1be42bf71a22843994408 100755
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
index be8a8212c4d9ca1e2a2a1cd9ca7d31a517f4d57e..4b494928eb8a8fdfad3587a9202f7c1d9c21c531 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -1,7 +1,4 @@
-Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 39729
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 37717
 Design successfully loaded
-Design Loading Memory Usage: 22124 KB (Peak: 22132 KB)
-Design Loading CPU Usage: 20 ms
-Simulation completed
-Simulation Memory Usage: 108480 KB (Peak: 161392 KB)
-Simulation CPU Usage: 100 ms
+Design Loading Memory Usage: 20176 KB (Peak: 20764 KB)
+Design Loading CPU Usage: 30 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
index 4108b60f26ec95e13c207190b64ad54790616917..c2a7f9f93325805a0249e6d202594c568ba22e9c 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
index 339e94263b7874de5e9e2d90f8a2a1bdcc2d927c..7d96a46a86e28534aeccc8afb6e99179aff66f8a 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb
deleted file mode 100644
index 9fa04973ab392d39193f50f8968368a3e401cc3b..0000000000000000000000000000000000000000
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb and /dev/null differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operative@unit.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operative@unit.sdb
deleted file mode 100644
index 81e2120c76717ff444307d9a8592b25286c6e0e2..0000000000000000000000000000000000000000
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operative@unit.sdb and /dev/null differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
index c0cc4e398ebb98149f7992f5cfc5152af4bed0b3..f99a2fe0cb1d8a2b76a7e2df780c6d450151ea92 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index 0633b51256a9d46fd96b4b24e27a038dcb4f02a0..15bde163138c59230168a2f9f576edd04472f3e1 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -2,8 +2,7 @@
 2020.2
 May 22 2024
 18:54:44
-/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v,1708598507,verilog,,,,glbl,,,,,,,,
 /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/controlUnit.vhd,1746797603,vhdl,/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
 /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd,1746792833,vhdl,/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
-/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.v,1746792833,verilog,/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd,,,\operativeUnit\,,,,,,,,
+/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd,1747059192,vhdl,/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
 /homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/tb_firUnit.vhd,1746792833,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..96e359f34588f46348d12fe1fbce0b937a58d6c2 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
index b155e40f06a230303a04d2a77f07560e35c5dc93..b77490a99623c842746766577781e7507ff312d0 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb and b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
deleted file mode 100644
index b155e40f06a230303a04d2a77f07560e35c5dc93..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
index bc3de20a0d962fc97e179d229da35d4d2d469acc..4e826ab2576e94c1522e3ee636e4fdd804c49c0c 100644
--- a/proj/AudioProc.xpr
+++ b/proj/AudioProc.xpr
@@ -7,7 +7,7 @@
 <Project Product="Vivado" Version="7" Minor="67" Path="/homes/g24demon/Documents/SA_filtre/tp-filtre-etudiant-p24noels/proj/AudioProc.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="51abf6c239b947a5bdfbf617f84231c2"/>
+    <Option Name="Id" Val="60055113a5e34b09b93fbd1cc9d1da0f"/>
     <Option Name="Part" Val="xc7a200tsbg484-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -60,7 +60,7 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="7"/>
+    <Option Name="WTXSimLaunchSim" Val="4"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -155,14 +155,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../src/hdl/operativeUnit.v">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
@@ -189,6 +181,7 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="tb_firUnit"/>
@@ -234,9 +227,7 @@
   <Runs Version="1" Minor="22">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred  with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
-          <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred  with a larger threshold</Desc>
-        </StratHandle>
+        <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
         <Step Id="synth_design">
           <Option Id="FsmExtraction">1</Option>
           <Option Id="KeepEquivalentRegisters">1</Option>
@@ -253,9 +244,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
-          <Desc>Vivado Implementation Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/src/hdl/operativeUnit.v b/src/hdl/operativeUnit.v
deleted file mode 100644
index 167baf65b9d519f5dfc3b2a0e004bb70af020cc2..0000000000000000000000000000000000000000
--- a/src/hdl/operativeUnit.v
+++ /dev/null
@@ -1,4199 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-// Date        : Wed Apr  9 16:08:04 2025
-// Host        : marzel-XPS-13-7390-2-in-1 running 64-bit Ubuntu 22.04.5 LTS
-// Command     : write_verilog
-//               /home/marzel/Documents/enseignements/IMTA_ELEC_A1S2_TAF/UE_EE/SAR_TA/Filtre_NexysVideo_PROF/proj/operativeUnit.v
-// Design      : operativeUnit
-// Purpose     : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
-//               IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
-//               design files.
-// Device      : xc7a200tsbg484-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* STRUCTURAL_NETLIST = "yes" *)
-module operativeUnit
-   (I_clock,
-    I_reset,
-    I_inputSample,
-    I_loadShift,
-    I_initAddress,
-    I_incrAddress,
-    I_initSum,
-    I_loadSum,
-    I_loadOutput,
-    O_processingDone,
-    O_filteredSample);
-  input I_clock;
-  input I_reset;
-  input [15:0]I_inputSample;
-  input I_loadShift;
-  input I_initAddress;
-  input I_incrAddress;
-  input I_initSum;
-  input I_loadSum;
-  input I_loadOutput;
-  output O_processingDone;
-  output [15:0]O_filteredSample;
-
-  wire \<const0> ;
-  wire \<const1> ;
-  wire GND_2;
-  wire I_clock;
-  wire I_clock_IBUF;
-  wire I_clock_IBUF_BUFG;
-  wire I_incrAddress;
-  wire I_incrAddress_IBUF;
-  wire I_initAddress;
-  wire I_initAddress_IBUF;
-  wire I_initSum;
-  wire I_initSum_IBUF;
-  wire [15:0]I_inputSample;
-  wire [15:0]I_inputSample_IBUF;
-  wire I_loadOutput;
-  wire I_loadOutput_IBUF;
-  wire I_loadShift;
-  wire I_loadShift_IBUF;
-  wire I_loadSum;
-  wire I_loadSum_IBUF;
-  wire I_reset;
-  wire I_reset_IBUF;
-  wire [30:15]L;
-  wire [15:0]O_filteredSample;
-  wire [15:0]O_filteredSample_OBUF;
-  wire O_processingDone;
-  wire O_processingDone_OBUF;
-  wire SC_addResult_i_100_n_0;
-  wire SC_addResult_i_101_n_0;
-  wire SC_addResult_i_102_n_0;
-  wire SC_addResult_i_103_n_0;
-  wire SC_addResult_i_104_n_0;
-  wire SC_addResult_i_105_n_0;
-  wire SC_addResult_i_106_n_0;
-  wire SC_addResult_i_107_n_0;
-  wire SC_addResult_i_108_n_0;
-  wire SC_addResult_i_109_n_0;
-  wire SC_addResult_i_110_n_0;
-  wire SC_addResult_i_111_n_0;
-  wire SC_addResult_i_112_n_0;
-  wire SC_addResult_i_113_n_0;
-  wire SC_addResult_i_114_n_0;
-  wire SC_addResult_i_115_n_0;
-  wire SC_addResult_i_116_n_0;
-  wire SC_addResult_i_117_n_0;
-  wire SC_addResult_i_118_n_0;
-  wire SC_addResult_i_119_n_0;
-  wire SC_addResult_i_120_n_0;
-  wire SC_addResult_i_121_n_0;
-  wire SC_addResult_i_122_n_0;
-  wire SC_addResult_i_123_n_0;
-  wire SC_addResult_i_124_n_0;
-  wire SC_addResult_i_29_n_0;
-  wire SC_addResult_i_30_n_0;
-  wire SC_addResult_i_31_n_0;
-  wire SC_addResult_i_32_n_0;
-  wire SC_addResult_i_33_n_0;
-  wire SC_addResult_i_34_n_0;
-  wire SC_addResult_i_35_n_0;
-  wire SC_addResult_i_36_n_0;
-  wire SC_addResult_i_37_n_0;
-  wire SC_addResult_i_38_n_0;
-  wire SC_addResult_i_39_n_0;
-  wire SC_addResult_i_40_n_0;
-  wire SC_addResult_i_41_n_0;
-  wire SC_addResult_i_42_n_0;
-  wire SC_addResult_i_43_n_0;
-  wire SC_addResult_i_44_n_0;
-  wire SC_addResult_i_45_n_0;
-  wire SC_addResult_i_46_n_0;
-  wire SC_addResult_i_47_n_0;
-  wire SC_addResult_i_48_n_0;
-  wire SC_addResult_i_49_n_0;
-  wire SC_addResult_i_50_n_0;
-  wire SC_addResult_i_51_n_0;
-  wire SC_addResult_i_52_n_0;
-  wire SC_addResult_i_53_n_0;
-  wire SC_addResult_i_54_n_0;
-  wire SC_addResult_i_55_n_0;
-  wire SC_addResult_i_56_n_0;
-  wire SC_addResult_i_57_n_0;
-  wire SC_addResult_i_58_n_0;
-  wire SC_addResult_i_59_n_0;
-  wire SC_addResult_i_60_n_0;
-  wire SC_addResult_i_61_n_0;
-  wire SC_addResult_i_62_n_0;
-  wire SC_addResult_i_63_n_0;
-  wire SC_addResult_i_64_n_0;
-  wire SC_addResult_i_65_n_0;
-  wire SC_addResult_i_66_n_0;
-  wire SC_addResult_i_67_n_0;
-  wire SC_addResult_i_68_n_0;
-  wire SC_addResult_i_69_n_0;
-  wire SC_addResult_i_70_n_0;
-  wire SC_addResult_i_71_n_0;
-  wire SC_addResult_i_72_n_0;
-  wire SC_addResult_i_73_n_0;
-  wire SC_addResult_i_74_n_0;
-  wire SC_addResult_i_75_n_0;
-  wire SC_addResult_i_76_n_0;
-  wire SC_addResult_i_77_n_0;
-  wire SC_addResult_i_78_n_0;
-  wire SC_addResult_i_79_n_0;
-  wire SC_addResult_i_80_n_0;
-  wire SC_addResult_i_81_n_0;
-  wire SC_addResult_i_82_n_0;
-  wire SC_addResult_i_83_n_0;
-  wire SC_addResult_i_84_n_0;
-  wire SC_addResult_i_85_n_0;
-  wire SC_addResult_i_86_n_0;
-  wire SC_addResult_i_87_n_0;
-  wire SC_addResult_i_88_n_0;
-  wire SC_addResult_i_89_n_0;
-  wire SC_addResult_i_90_n_0;
-  wire SC_addResult_i_91_n_0;
-  wire SC_addResult_i_92_n_0;
-  wire SC_addResult_i_93_n_0;
-  wire SC_addResult_i_94_n_0;
-  wire SC_addResult_i_95_n_0;
-  wire SC_addResult_i_96_n_0;
-  wire SC_addResult_i_97_n_0;
-  wire SC_addResult_i_98_n_0;
-  wire SC_addResult_i_99_n_0;
-  wire SC_addResult_n_100;
-  wire SC_addResult_n_101;
-  wire SC_addResult_n_102;
-  wire SC_addResult_n_103;
-  wire SC_addResult_n_104;
-  wire SC_addResult_n_105;
-  wire SC_addResult_n_70;
-  wire SC_addResult_n_71;
-  wire SC_addResult_n_72;
-  wire SC_addResult_n_73;
-  wire SC_addResult_n_74;
-  wire SC_addResult_n_91;
-  wire SC_addResult_n_92;
-  wire SC_addResult_n_93;
-  wire SC_addResult_n_94;
-  wire SC_addResult_n_95;
-  wire SC_addResult_n_96;
-  wire SC_addResult_n_97;
-  wire SC_addResult_n_98;
-  wire SC_addResult_n_99;
-  wire [11:0]SC_multOperand2;
-  wire \SR_filteredSample[3]_i_2_n_0 ;
-  wire \SR_filteredSample_reg[11]_i_1_n_0 ;
-  wire \SR_filteredSample_reg[11]_i_1_n_1 ;
-  wire \SR_filteredSample_reg[11]_i_1_n_2 ;
-  wire \SR_filteredSample_reg[11]_i_1_n_3 ;
-  wire \SR_filteredSample_reg[15]_i_1_n_1 ;
-  wire \SR_filteredSample_reg[15]_i_1_n_2 ;
-  wire \SR_filteredSample_reg[15]_i_1_n_3 ;
-  wire \SR_filteredSample_reg[3]_i_1_n_0 ;
-  wire \SR_filteredSample_reg[3]_i_1_n_1 ;
-  wire \SR_filteredSample_reg[3]_i_1_n_2 ;
-  wire \SR_filteredSample_reg[3]_i_1_n_3 ;
-  wire \SR_filteredSample_reg[7]_i_1_n_0 ;
-  wire \SR_filteredSample_reg[7]_i_1_n_1 ;
-  wire \SR_filteredSample_reg[7]_i_1_n_2 ;
-  wire \SR_filteredSample_reg[7]_i_1_n_3 ;
-  wire [3:0]SR_readAddress;
-  wire \SR_readAddress[0]_i_1_n_0 ;
-  wire \SR_readAddress[1]_i_1_n_0 ;
-  wire \SR_readAddress[2]_i_1_n_0 ;
-  wire \SR_readAddress[3]_i_1_n_0 ;
-  wire \SR_readAddress[3]_i_2_n_0 ;
-  wire [15:0]\SR_shiftRegister[0] ;
-  wire [15:0]\SR_shiftRegister_reg[0] ;
-  wire [15:0]\SR_shiftRegister_reg[10] ;
-  wire [15:0]\SR_shiftRegister_reg[11] ;
-  wire [15:0]\SR_shiftRegister_reg[12] ;
-  wire [15:0]\SR_shiftRegister_reg[13] ;
-  wire [15:0]\SR_shiftRegister_reg[14] ;
-  wire [15:0]\SR_shiftRegister_reg[15] ;
-  wire [15:0]\SR_shiftRegister_reg[1] ;
-  wire [15:0]\SR_shiftRegister_reg[2] ;
-  wire [15:0]\SR_shiftRegister_reg[3] ;
-  wire [15:0]\SR_shiftRegister_reg[4] ;
-  wire [15:0]\SR_shiftRegister_reg[5] ;
-  wire [15:0]\SR_shiftRegister_reg[6] ;
-  wire [15:0]\SR_shiftRegister_reg[7] ;
-  wire [15:0]\SR_shiftRegister_reg[8] ;
-  wire [15:0]\SR_shiftRegister_reg[9] ;
-  wire [35:0]SR_sum;
-  wire \SR_sum[35]_i_1_n_0 ;
-  wire [15:0]p_0_in;
-  wire [35:0]p_1_in;
-
-  GND GND
-       (.G(\<const0> ));
-  GND GND_1
-       (.G(GND_2));
-  BUFG I_clock_IBUF_BUFG_inst
-       (.I(I_clock_IBUF),
-        .O(I_clock_IBUF_BUFG));
-  IBUF I_clock_IBUF_inst
-       (.I(I_clock),
-        .O(I_clock_IBUF));
-  IBUF I_incrAddress_IBUF_inst
-       (.I(I_incrAddress),
-        .O(I_incrAddress_IBUF));
-  IBUF I_initAddress_IBUF_inst
-       (.I(I_initAddress),
-        .O(I_initAddress_IBUF));
-  IBUF I_initSum_IBUF_inst
-       (.I(I_initSum),
-        .O(I_initSum_IBUF));
-  IBUF \I_inputSample_IBUF[0]_inst 
-       (.I(I_inputSample[0]),
-        .O(I_inputSample_IBUF[0]));
-  IBUF \I_inputSample_IBUF[10]_inst 
-       (.I(I_inputSample[10]),
-        .O(I_inputSample_IBUF[10]));
-  IBUF \I_inputSample_IBUF[11]_inst 
-       (.I(I_inputSample[11]),
-        .O(I_inputSample_IBUF[11]));
-  IBUF \I_inputSample_IBUF[12]_inst 
-       (.I(I_inputSample[12]),
-        .O(I_inputSample_IBUF[12]));
-  IBUF \I_inputSample_IBUF[13]_inst 
-       (.I(I_inputSample[13]),
-        .O(I_inputSample_IBUF[13]));
-  IBUF \I_inputSample_IBUF[14]_inst 
-       (.I(I_inputSample[14]),
-        .O(I_inputSample_IBUF[14]));
-  IBUF \I_inputSample_IBUF[15]_inst 
-       (.I(I_inputSample[15]),
-        .O(I_inputSample_IBUF[15]));
-  IBUF \I_inputSample_IBUF[1]_inst 
-       (.I(I_inputSample[1]),
-        .O(I_inputSample_IBUF[1]));
-  IBUF \I_inputSample_IBUF[2]_inst 
-       (.I(I_inputSample[2]),
-        .O(I_inputSample_IBUF[2]));
-  IBUF \I_inputSample_IBUF[3]_inst 
-       (.I(I_inputSample[3]),
-        .O(I_inputSample_IBUF[3]));
-  IBUF \I_inputSample_IBUF[4]_inst 
-       (.I(I_inputSample[4]),
-        .O(I_inputSample_IBUF[4]));
-  IBUF \I_inputSample_IBUF[5]_inst 
-       (.I(I_inputSample[5]),
-        .O(I_inputSample_IBUF[5]));
-  IBUF \I_inputSample_IBUF[6]_inst 
-       (.I(I_inputSample[6]),
-        .O(I_inputSample_IBUF[6]));
-  IBUF \I_inputSample_IBUF[7]_inst 
-       (.I(I_inputSample[7]),
-        .O(I_inputSample_IBUF[7]));
-  IBUF \I_inputSample_IBUF[8]_inst 
-       (.I(I_inputSample[8]),
-        .O(I_inputSample_IBUF[8]));
-  IBUF \I_inputSample_IBUF[9]_inst 
-       (.I(I_inputSample[9]),
-        .O(I_inputSample_IBUF[9]));
-  IBUF I_loadOutput_IBUF_inst
-       (.I(I_loadOutput),
-        .O(I_loadOutput_IBUF));
-  IBUF I_loadShift_IBUF_inst
-       (.I(I_loadShift),
-        .O(I_loadShift_IBUF));
-  IBUF I_loadSum_IBUF_inst
-       (.I(I_loadSum),
-        .O(I_loadSum_IBUF));
-  IBUF I_reset_IBUF_inst
-       (.I(I_reset),
-        .O(I_reset_IBUF));
-  OBUF \O_filteredSample_OBUF[0]_inst 
-       (.I(O_filteredSample_OBUF[0]),
-        .O(O_filteredSample[0]));
-  OBUF \O_filteredSample_OBUF[10]_inst 
-       (.I(O_filteredSample_OBUF[10]),
-        .O(O_filteredSample[10]));
-  OBUF \O_filteredSample_OBUF[11]_inst 
-       (.I(O_filteredSample_OBUF[11]),
-        .O(O_filteredSample[11]));
-  OBUF \O_filteredSample_OBUF[12]_inst 
-       (.I(O_filteredSample_OBUF[12]),
-        .O(O_filteredSample[12]));
-  OBUF \O_filteredSample_OBUF[13]_inst 
-       (.I(O_filteredSample_OBUF[13]),
-        .O(O_filteredSample[13]));
-  OBUF \O_filteredSample_OBUF[14]_inst 
-       (.I(O_filteredSample_OBUF[14]),
-        .O(O_filteredSample[14]));
-  OBUF \O_filteredSample_OBUF[15]_inst 
-       (.I(O_filteredSample_OBUF[15]),
-        .O(O_filteredSample[15]));
-  OBUF \O_filteredSample_OBUF[1]_inst 
-       (.I(O_filteredSample_OBUF[1]),
-        .O(O_filteredSample[1]));
-  OBUF \O_filteredSample_OBUF[2]_inst 
-       (.I(O_filteredSample_OBUF[2]),
-        .O(O_filteredSample[2]));
-  OBUF \O_filteredSample_OBUF[3]_inst 
-       (.I(O_filteredSample_OBUF[3]),
-        .O(O_filteredSample[3]));
-  OBUF \O_filteredSample_OBUF[4]_inst 
-       (.I(O_filteredSample_OBUF[4]),
-        .O(O_filteredSample[4]));
-  OBUF \O_filteredSample_OBUF[5]_inst 
-       (.I(O_filteredSample_OBUF[5]),
-        .O(O_filteredSample[5]));
-  OBUF \O_filteredSample_OBUF[6]_inst 
-       (.I(O_filteredSample_OBUF[6]),
-        .O(O_filteredSample[6]));
-  OBUF \O_filteredSample_OBUF[7]_inst 
-       (.I(O_filteredSample_OBUF[7]),
-        .O(O_filteredSample[7]));
-  OBUF \O_filteredSample_OBUF[8]_inst 
-       (.I(O_filteredSample_OBUF[8]),
-        .O(O_filteredSample[8]));
-  OBUF \O_filteredSample_OBUF[9]_inst 
-       (.I(O_filteredSample_OBUF[9]),
-        .O(O_filteredSample[9]));
-  OBUF O_processingDone_OBUF_inst
-       (.I(O_processingDone_OBUF),
-        .O(O_processingDone));
-  LUT3 #(
-    .INIT(8'h80)) 
-    O_processingDone_OBUF_inst_i_1
-       (.I0(SR_readAddress[1]),
-        .I1(SR_readAddress[3]),
-        .I2(SR_readAddress[2]),
-        .O(O_processingDone_OBUF));
-  (* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *) 
-  DSP48E1 #(
-    .ACASCREG(0),
-    .ADREG(1),
-    .ALUMODEREG(0),
-    .AREG(0),
-    .AUTORESET_PATDET("NO_RESET"),
-    .A_INPUT("DIRECT"),
-    .BCASCREG(0),
-    .BREG(0),
-    .B_INPUT("DIRECT"),
-    .CARRYINREG(0),
-    .CARRYINSELREG(0),
-    .CREG(0),
-    .DREG(1),
-    .INMODEREG(0),
-    .MASK(48'h3FFFFFFFFFFF),
-    .MREG(0),
-    .OPMODEREG(0),
-    .PATTERN(48'h000000000000),
-    .PREG(0),
-    .SEL_MASK("MASK"),
-    .SEL_PATTERN("PATTERN"),
-    .USE_DPORT("FALSE"),
-    .USE_MULT("MULTIPLY"),
-    .USE_PATTERN_DETECT("NO_PATDET"),
-    .USE_SIMD("ONE48")) 
-    SC_addResult
-       (.A({\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] }),
-        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,SC_multOperand2}),
-        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .C({SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum}),
-        .CARRYCASCIN(\<const0> ),
-        .CARRYIN(\<const0> ),
-        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
-        .CEA1(\<const0> ),
-        .CEA2(\<const0> ),
-        .CEAD(\<const0> ),
-        .CEALUMODE(\<const0> ),
-        .CEB1(\<const0> ),
-        .CEB2(\<const0> ),
-        .CEC(\<const0> ),
-        .CECARRYIN(\<const0> ),
-        .CECTRL(\<const0> ),
-        .CED(\<const0> ),
-        .CEINMODE(\<const0> ),
-        .CEM(\<const0> ),
-        .CEP(\<const0> ),
-        .CLK(\<const0> ),
-        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
-        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .MULTSIGNIN(\<const0> ),
-        .OPMODE({\<const0> ,\<const1> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
-        .P({SC_addResult_n_70,SC_addResult_n_71,SC_addResult_n_72,SC_addResult_n_73,SC_addResult_n_74,L,SC_addResult_n_91,SC_addResult_n_92,SC_addResult_n_93,SC_addResult_n_94,SC_addResult_n_95,SC_addResult_n_96,SC_addResult_n_97,SC_addResult_n_98,SC_addResult_n_99,SC_addResult_n_100,SC_addResult_n_101,SC_addResult_n_102,SC_addResult_n_103,SC_addResult_n_104,SC_addResult_n_105}),
-        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .RSTA(\<const0> ),
-        .RSTALLCARRYIN(\<const0> ),
-        .RSTALUMODE(\<const0> ),
-        .RSTB(\<const0> ),
-        .RSTC(\<const0> ),
-        .RSTCTRL(\<const0> ),
-        .RSTD(\<const0> ),
-        .RSTINMODE(\<const0> ),
-        .RSTM(\<const0> ),
-        .RSTP(\<const0> ));
-  LUT2 #(
-    .INIT(4'h6)) 
-    SC_addResult_i_1
-       (.I0(SR_readAddress[2]),
-        .I1(SR_readAddress[3]),
-        .O(SC_multOperand2[11]));
-  LUT4 #(
-    .INIT(16'hBFFD)) 
-    SC_addResult_i_10
-       (.I0(SR_readAddress[2]),
-        .I1(SR_readAddress[3]),
-        .I2(SR_readAddress[1]),
-        .I3(SR_readAddress[0]),
-        .O(SC_multOperand2[2]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_100
-       (.I0(\SR_shiftRegister_reg[15] [6]),
-        .I1(\SR_shiftRegister_reg[14] [6]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [6]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [6]),
-        .O(SC_addResult_i_100_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_101
-       (.I0(\SR_shiftRegister_reg[3] [5]),
-        .I1(\SR_shiftRegister_reg[2] [5]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [5]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [5]),
-        .O(SC_addResult_i_101_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_102
-       (.I0(\SR_shiftRegister_reg[7] [5]),
-        .I1(\SR_shiftRegister_reg[6] [5]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [5]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [5]),
-        .O(SC_addResult_i_102_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_103
-       (.I0(\SR_shiftRegister_reg[11] [5]),
-        .I1(\SR_shiftRegister_reg[10] [5]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [5]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [5]),
-        .O(SC_addResult_i_103_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_104
-       (.I0(\SR_shiftRegister_reg[15] [5]),
-        .I1(\SR_shiftRegister_reg[14] [5]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [5]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [5]),
-        .O(SC_addResult_i_104_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_105
-       (.I0(\SR_shiftRegister_reg[3] [4]),
-        .I1(\SR_shiftRegister_reg[2] [4]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [4]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [4]),
-        .O(SC_addResult_i_105_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_106
-       (.I0(\SR_shiftRegister_reg[7] [4]),
-        .I1(\SR_shiftRegister_reg[6] [4]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [4]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [4]),
-        .O(SC_addResult_i_106_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_107
-       (.I0(\SR_shiftRegister_reg[11] [4]),
-        .I1(\SR_shiftRegister_reg[10] [4]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [4]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [4]),
-        .O(SC_addResult_i_107_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_108
-       (.I0(\SR_shiftRegister_reg[15] [4]),
-        .I1(\SR_shiftRegister_reg[14] [4]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [4]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [4]),
-        .O(SC_addResult_i_108_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_109
-       (.I0(\SR_shiftRegister_reg[3] [3]),
-        .I1(\SR_shiftRegister_reg[2] [3]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [3]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [3]),
-        .O(SC_addResult_i_109_n_0));
-  LUT4 #(
-    .INIT(16'h581A)) 
-    SC_addResult_i_11
-       (.I0(SR_readAddress[3]),
-        .I1(SR_readAddress[1]),
-        .I2(SR_readAddress[2]),
-        .I3(SR_readAddress[0]),
-        .O(SC_multOperand2[1]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_110
-       (.I0(\SR_shiftRegister_reg[7] [3]),
-        .I1(\SR_shiftRegister_reg[6] [3]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [3]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [3]),
-        .O(SC_addResult_i_110_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_111
-       (.I0(\SR_shiftRegister_reg[11] [3]),
-        .I1(\SR_shiftRegister_reg[10] [3]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [3]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [3]),
-        .O(SC_addResult_i_111_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_112
-       (.I0(\SR_shiftRegister_reg[15] [3]),
-        .I1(\SR_shiftRegister_reg[14] [3]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [3]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [3]),
-        .O(SC_addResult_i_112_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_113
-       (.I0(\SR_shiftRegister_reg[3] [2]),
-        .I1(\SR_shiftRegister_reg[2] [2]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [2]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [2]),
-        .O(SC_addResult_i_113_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_114
-       (.I0(\SR_shiftRegister_reg[7] [2]),
-        .I1(\SR_shiftRegister_reg[6] [2]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [2]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [2]),
-        .O(SC_addResult_i_114_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_115
-       (.I0(\SR_shiftRegister_reg[11] [2]),
-        .I1(\SR_shiftRegister_reg[10] [2]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [2]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [2]),
-        .O(SC_addResult_i_115_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_116
-       (.I0(\SR_shiftRegister_reg[15] [2]),
-        .I1(\SR_shiftRegister_reg[14] [2]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [2]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [2]),
-        .O(SC_addResult_i_116_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_117
-       (.I0(\SR_shiftRegister_reg[3] [1]),
-        .I1(\SR_shiftRegister_reg[2] [1]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [1]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [1]),
-        .O(SC_addResult_i_117_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_118
-       (.I0(\SR_shiftRegister_reg[7] [1]),
-        .I1(\SR_shiftRegister_reg[6] [1]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [1]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [1]),
-        .O(SC_addResult_i_118_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_119
-       (.I0(\SR_shiftRegister_reg[11] [1]),
-        .I1(\SR_shiftRegister_reg[10] [1]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [1]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [1]),
-        .O(SC_addResult_i_119_n_0));
-  LUT4 #(
-    .INIT(16'hF66F)) 
-    SC_addResult_i_12
-       (.I0(SR_readAddress[3]),
-        .I1(SR_readAddress[1]),
-        .I2(SR_readAddress[2]),
-        .I3(SR_readAddress[0]),
-        .O(SC_multOperand2[0]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_120
-       (.I0(\SR_shiftRegister_reg[15] [1]),
-        .I1(\SR_shiftRegister_reg[14] [1]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [1]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [1]),
-        .O(SC_addResult_i_120_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_121
-       (.I0(\SR_shiftRegister_reg[3] [0]),
-        .I1(\SR_shiftRegister_reg[2] [0]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [0]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [0]),
-        .O(SC_addResult_i_121_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_122
-       (.I0(\SR_shiftRegister_reg[7] [0]),
-        .I1(\SR_shiftRegister_reg[6] [0]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [0]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [0]),
-        .O(SC_addResult_i_122_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_123
-       (.I0(\SR_shiftRegister_reg[11] [0]),
-        .I1(\SR_shiftRegister_reg[10] [0]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [0]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [0]),
-        .O(SC_addResult_i_123_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_124
-       (.I0(\SR_shiftRegister_reg[15] [0]),
-        .I1(\SR_shiftRegister_reg[14] [0]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [0]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [0]),
-        .O(SC_addResult_i_124_n_0));
-  MUXF8 SC_addResult_i_13
-       (.I0(SC_addResult_i_29_n_0),
-        .I1(SC_addResult_i_30_n_0),
-        .O(\SR_shiftRegister[0] [15]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_14
-       (.I0(SC_addResult_i_31_n_0),
-        .I1(SC_addResult_i_32_n_0),
-        .O(\SR_shiftRegister[0] [14]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_15
-       (.I0(SC_addResult_i_33_n_0),
-        .I1(SC_addResult_i_34_n_0),
-        .O(\SR_shiftRegister[0] [13]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_16
-       (.I0(SC_addResult_i_35_n_0),
-        .I1(SC_addResult_i_36_n_0),
-        .O(\SR_shiftRegister[0] [12]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_17
-       (.I0(SC_addResult_i_37_n_0),
-        .I1(SC_addResult_i_38_n_0),
-        .O(\SR_shiftRegister[0] [11]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_18
-       (.I0(SC_addResult_i_39_n_0),
-        .I1(SC_addResult_i_40_n_0),
-        .O(\SR_shiftRegister[0] [10]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_19
-       (.I0(SC_addResult_i_41_n_0),
-        .I1(SC_addResult_i_42_n_0),
-        .O(\SR_shiftRegister[0] [9]),
-        .S(SR_readAddress[3]));
-  LUT4 #(
-    .INIT(16'h1E78)) 
-    SC_addResult_i_2
-       (.I0(SR_readAddress[2]),
-        .I1(SR_readAddress[1]),
-        .I2(SR_readAddress[3]),
-        .I3(SR_readAddress[0]),
-        .O(SC_multOperand2[10]));
-  MUXF8 SC_addResult_i_20
-       (.I0(SC_addResult_i_43_n_0),
-        .I1(SC_addResult_i_44_n_0),
-        .O(\SR_shiftRegister[0] [8]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_21
-       (.I0(SC_addResult_i_45_n_0),
-        .I1(SC_addResult_i_46_n_0),
-        .O(\SR_shiftRegister[0] [7]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_22
-       (.I0(SC_addResult_i_47_n_0),
-        .I1(SC_addResult_i_48_n_0),
-        .O(\SR_shiftRegister[0] [6]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_23
-       (.I0(SC_addResult_i_49_n_0),
-        .I1(SC_addResult_i_50_n_0),
-        .O(\SR_shiftRegister[0] [5]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_24
-       (.I0(SC_addResult_i_51_n_0),
-        .I1(SC_addResult_i_52_n_0),
-        .O(\SR_shiftRegister[0] [4]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_25
-       (.I0(SC_addResult_i_53_n_0),
-        .I1(SC_addResult_i_54_n_0),
-        .O(\SR_shiftRegister[0] [3]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_26
-       (.I0(SC_addResult_i_55_n_0),
-        .I1(SC_addResult_i_56_n_0),
-        .O(\SR_shiftRegister[0] [2]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_27
-       (.I0(SC_addResult_i_57_n_0),
-        .I1(SC_addResult_i_58_n_0),
-        .O(\SR_shiftRegister[0] [1]),
-        .S(SR_readAddress[3]));
-  MUXF8 SC_addResult_i_28
-       (.I0(SC_addResult_i_59_n_0),
-        .I1(SC_addResult_i_60_n_0),
-        .O(\SR_shiftRegister[0] [0]),
-        .S(SR_readAddress[3]));
-  MUXF7 SC_addResult_i_29
-       (.I0(SC_addResult_i_61_n_0),
-        .I1(SC_addResult_i_62_n_0),
-        .O(SC_addResult_i_29_n_0),
-        .S(SR_readAddress[2]));
-  LUT2 #(
-    .INIT(4'h6)) 
-    SC_addResult_i_3
-       (.I0(SR_readAddress[1]),
-        .I1(SR_readAddress[3]),
-        .O(SC_multOperand2[9]));
-  MUXF7 SC_addResult_i_30
-       (.I0(SC_addResult_i_63_n_0),
-        .I1(SC_addResult_i_64_n_0),
-        .O(SC_addResult_i_30_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_31
-       (.I0(SC_addResult_i_65_n_0),
-        .I1(SC_addResult_i_66_n_0),
-        .O(SC_addResult_i_31_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_32
-       (.I0(SC_addResult_i_67_n_0),
-        .I1(SC_addResult_i_68_n_0),
-        .O(SC_addResult_i_32_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_33
-       (.I0(SC_addResult_i_69_n_0),
-        .I1(SC_addResult_i_70_n_0),
-        .O(SC_addResult_i_33_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_34
-       (.I0(SC_addResult_i_71_n_0),
-        .I1(SC_addResult_i_72_n_0),
-        .O(SC_addResult_i_34_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_35
-       (.I0(SC_addResult_i_73_n_0),
-        .I1(SC_addResult_i_74_n_0),
-        .O(SC_addResult_i_35_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_36
-       (.I0(SC_addResult_i_75_n_0),
-        .I1(SC_addResult_i_76_n_0),
-        .O(SC_addResult_i_36_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_37
-       (.I0(SC_addResult_i_77_n_0),
-        .I1(SC_addResult_i_78_n_0),
-        .O(SC_addResult_i_37_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_38
-       (.I0(SC_addResult_i_79_n_0),
-        .I1(SC_addResult_i_80_n_0),
-        .O(SC_addResult_i_38_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_39
-       (.I0(SC_addResult_i_81_n_0),
-        .I1(SC_addResult_i_82_n_0),
-        .O(SC_addResult_i_39_n_0),
-        .S(SR_readAddress[2]));
-  LUT4 #(
-    .INIT(16'hE997)) 
-    SC_addResult_i_4
-       (.I0(SR_readAddress[1]),
-        .I1(SR_readAddress[3]),
-        .I2(SR_readAddress[2]),
-        .I3(SR_readAddress[0]),
-        .O(SC_multOperand2[8]));
-  MUXF7 SC_addResult_i_40
-       (.I0(SC_addResult_i_83_n_0),
-        .I1(SC_addResult_i_84_n_0),
-        .O(SC_addResult_i_40_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_41
-       (.I0(SC_addResult_i_85_n_0),
-        .I1(SC_addResult_i_86_n_0),
-        .O(SC_addResult_i_41_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_42
-       (.I0(SC_addResult_i_87_n_0),
-        .I1(SC_addResult_i_88_n_0),
-        .O(SC_addResult_i_42_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_43
-       (.I0(SC_addResult_i_89_n_0),
-        .I1(SC_addResult_i_90_n_0),
-        .O(SC_addResult_i_43_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_44
-       (.I0(SC_addResult_i_91_n_0),
-        .I1(SC_addResult_i_92_n_0),
-        .O(SC_addResult_i_44_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_45
-       (.I0(SC_addResult_i_93_n_0),
-        .I1(SC_addResult_i_94_n_0),
-        .O(SC_addResult_i_45_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_46
-       (.I0(SC_addResult_i_95_n_0),
-        .I1(SC_addResult_i_96_n_0),
-        .O(SC_addResult_i_46_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_47
-       (.I0(SC_addResult_i_97_n_0),
-        .I1(SC_addResult_i_98_n_0),
-        .O(SC_addResult_i_47_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_48
-       (.I0(SC_addResult_i_99_n_0),
-        .I1(SC_addResult_i_100_n_0),
-        .O(SC_addResult_i_48_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_49
-       (.I0(SC_addResult_i_101_n_0),
-        .I1(SC_addResult_i_102_n_0),
-        .O(SC_addResult_i_49_n_0),
-        .S(SR_readAddress[2]));
-  LUT4 #(
-    .INIT(16'h6186)) 
-    SC_addResult_i_5
-       (.I0(SR_readAddress[1]),
-        .I1(SR_readAddress[3]),
-        .I2(SR_readAddress[2]),
-        .I3(SR_readAddress[0]),
-        .O(SC_multOperand2[7]));
-  MUXF7 SC_addResult_i_50
-       (.I0(SC_addResult_i_103_n_0),
-        .I1(SC_addResult_i_104_n_0),
-        .O(SC_addResult_i_50_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_51
-       (.I0(SC_addResult_i_105_n_0),
-        .I1(SC_addResult_i_106_n_0),
-        .O(SC_addResult_i_51_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_52
-       (.I0(SC_addResult_i_107_n_0),
-        .I1(SC_addResult_i_108_n_0),
-        .O(SC_addResult_i_52_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_53
-       (.I0(SC_addResult_i_109_n_0),
-        .I1(SC_addResult_i_110_n_0),
-        .O(SC_addResult_i_53_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_54
-       (.I0(SC_addResult_i_111_n_0),
-        .I1(SC_addResult_i_112_n_0),
-        .O(SC_addResult_i_54_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_55
-       (.I0(SC_addResult_i_113_n_0),
-        .I1(SC_addResult_i_114_n_0),
-        .O(SC_addResult_i_55_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_56
-       (.I0(SC_addResult_i_115_n_0),
-        .I1(SC_addResult_i_116_n_0),
-        .O(SC_addResult_i_56_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_57
-       (.I0(SC_addResult_i_117_n_0),
-        .I1(SC_addResult_i_118_n_0),
-        .O(SC_addResult_i_57_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_58
-       (.I0(SC_addResult_i_119_n_0),
-        .I1(SC_addResult_i_120_n_0),
-        .O(SC_addResult_i_58_n_0),
-        .S(SR_readAddress[2]));
-  MUXF7 SC_addResult_i_59
-       (.I0(SC_addResult_i_121_n_0),
-        .I1(SC_addResult_i_122_n_0),
-        .O(SC_addResult_i_59_n_0),
-        .S(SR_readAddress[2]));
-  LUT3 #(
-    .INIT(8'h42)) 
-    SC_addResult_i_6
-       (.I0(SR_readAddress[0]),
-        .I1(SR_readAddress[1]),
-        .I2(SR_readAddress[2]),
-        .O(SC_multOperand2[6]));
-  MUXF7 SC_addResult_i_60
-       (.I0(SC_addResult_i_123_n_0),
-        .I1(SC_addResult_i_124_n_0),
-        .O(SC_addResult_i_60_n_0),
-        .S(SR_readAddress[2]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_61
-       (.I0(\SR_shiftRegister_reg[3] [15]),
-        .I1(\SR_shiftRegister_reg[2] [15]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [15]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [15]),
-        .O(SC_addResult_i_61_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_62
-       (.I0(\SR_shiftRegister_reg[7] [15]),
-        .I1(\SR_shiftRegister_reg[6] [15]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [15]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [15]),
-        .O(SC_addResult_i_62_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_63
-       (.I0(\SR_shiftRegister_reg[11] [15]),
-        .I1(\SR_shiftRegister_reg[10] [15]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [15]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [15]),
-        .O(SC_addResult_i_63_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_64
-       (.I0(\SR_shiftRegister_reg[15] [15]),
-        .I1(\SR_shiftRegister_reg[14] [15]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [15]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [15]),
-        .O(SC_addResult_i_64_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_65
-       (.I0(\SR_shiftRegister_reg[3] [14]),
-        .I1(\SR_shiftRegister_reg[2] [14]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [14]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [14]),
-        .O(SC_addResult_i_65_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_66
-       (.I0(\SR_shiftRegister_reg[7] [14]),
-        .I1(\SR_shiftRegister_reg[6] [14]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [14]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [14]),
-        .O(SC_addResult_i_66_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_67
-       (.I0(\SR_shiftRegister_reg[11] [14]),
-        .I1(\SR_shiftRegister_reg[10] [14]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [14]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [14]),
-        .O(SC_addResult_i_67_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_68
-       (.I0(\SR_shiftRegister_reg[15] [14]),
-        .I1(\SR_shiftRegister_reg[14] [14]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [14]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [14]),
-        .O(SC_addResult_i_68_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_69
-       (.I0(\SR_shiftRegister_reg[3] [13]),
-        .I1(\SR_shiftRegister_reg[2] [13]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [13]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [13]),
-        .O(SC_addResult_i_69_n_0));
-  LUT4 #(
-    .INIT(16'hA245)) 
-    SC_addResult_i_7
-       (.I0(SR_readAddress[0]),
-        .I1(SR_readAddress[2]),
-        .I2(SR_readAddress[3]),
-        .I3(SR_readAddress[1]),
-        .O(SC_multOperand2[5]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_70
-       (.I0(\SR_shiftRegister_reg[7] [13]),
-        .I1(\SR_shiftRegister_reg[6] [13]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [13]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [13]),
-        .O(SC_addResult_i_70_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_71
-       (.I0(\SR_shiftRegister_reg[11] [13]),
-        .I1(\SR_shiftRegister_reg[10] [13]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [13]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [13]),
-        .O(SC_addResult_i_71_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_72
-       (.I0(\SR_shiftRegister_reg[15] [13]),
-        .I1(\SR_shiftRegister_reg[14] [13]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [13]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [13]),
-        .O(SC_addResult_i_72_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_73
-       (.I0(\SR_shiftRegister_reg[3] [12]),
-        .I1(\SR_shiftRegister_reg[2] [12]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [12]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [12]),
-        .O(SC_addResult_i_73_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_74
-       (.I0(\SR_shiftRegister_reg[7] [12]),
-        .I1(\SR_shiftRegister_reg[6] [12]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [12]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [12]),
-        .O(SC_addResult_i_74_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_75
-       (.I0(\SR_shiftRegister_reg[11] [12]),
-        .I1(\SR_shiftRegister_reg[10] [12]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [12]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [12]),
-        .O(SC_addResult_i_75_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_76
-       (.I0(\SR_shiftRegister_reg[15] [12]),
-        .I1(\SR_shiftRegister_reg[14] [12]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [12]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [12]),
-        .O(SC_addResult_i_76_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_77
-       (.I0(\SR_shiftRegister_reg[3] [11]),
-        .I1(\SR_shiftRegister_reg[2] [11]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [11]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [11]),
-        .O(SC_addResult_i_77_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_78
-       (.I0(\SR_shiftRegister_reg[7] [11]),
-        .I1(\SR_shiftRegister_reg[6] [11]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [11]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [11]),
-        .O(SC_addResult_i_78_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_79
-       (.I0(\SR_shiftRegister_reg[11] [11]),
-        .I1(\SR_shiftRegister_reg[10] [11]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [11]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [11]),
-        .O(SC_addResult_i_79_n_0));
-  LUT4 #(
-    .INIT(16'hF18F)) 
-    SC_addResult_i_8
-       (.I0(SR_readAddress[0]),
-        .I1(SR_readAddress[1]),
-        .I2(SR_readAddress[3]),
-        .I3(SR_readAddress[2]),
-        .O(SC_multOperand2[4]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_80
-       (.I0(\SR_shiftRegister_reg[15] [11]),
-        .I1(\SR_shiftRegister_reg[14] [11]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [11]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [11]),
-        .O(SC_addResult_i_80_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_81
-       (.I0(\SR_shiftRegister_reg[3] [10]),
-        .I1(\SR_shiftRegister_reg[2] [10]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [10]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [10]),
-        .O(SC_addResult_i_81_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_82
-       (.I0(\SR_shiftRegister_reg[7] [10]),
-        .I1(\SR_shiftRegister_reg[6] [10]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [10]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [10]),
-        .O(SC_addResult_i_82_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_83
-       (.I0(\SR_shiftRegister_reg[11] [10]),
-        .I1(\SR_shiftRegister_reg[10] [10]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [10]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [10]),
-        .O(SC_addResult_i_83_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_84
-       (.I0(\SR_shiftRegister_reg[15] [10]),
-        .I1(\SR_shiftRegister_reg[14] [10]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [10]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [10]),
-        .O(SC_addResult_i_84_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_85
-       (.I0(\SR_shiftRegister_reg[3] [9]),
-        .I1(\SR_shiftRegister_reg[2] [9]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [9]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [9]),
-        .O(SC_addResult_i_85_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_86
-       (.I0(\SR_shiftRegister_reg[7] [9]),
-        .I1(\SR_shiftRegister_reg[6] [9]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [9]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [9]),
-        .O(SC_addResult_i_86_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_87
-       (.I0(\SR_shiftRegister_reg[11] [9]),
-        .I1(\SR_shiftRegister_reg[10] [9]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [9]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [9]),
-        .O(SC_addResult_i_87_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_88
-       (.I0(\SR_shiftRegister_reg[15] [9]),
-        .I1(\SR_shiftRegister_reg[14] [9]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [9]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [9]),
-        .O(SC_addResult_i_88_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_89
-       (.I0(\SR_shiftRegister_reg[3] [8]),
-        .I1(\SR_shiftRegister_reg[2] [8]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [8]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [8]),
-        .O(SC_addResult_i_89_n_0));
-  LUT4 #(
-    .INIT(16'hD5AB)) 
-    SC_addResult_i_9
-       (.I0(SR_readAddress[0]),
-        .I1(SR_readAddress[2]),
-        .I2(SR_readAddress[3]),
-        .I3(SR_readAddress[1]),
-        .O(SC_multOperand2[3]));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_90
-       (.I0(\SR_shiftRegister_reg[7] [8]),
-        .I1(\SR_shiftRegister_reg[6] [8]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [8]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [8]),
-        .O(SC_addResult_i_90_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_91
-       (.I0(\SR_shiftRegister_reg[11] [8]),
-        .I1(\SR_shiftRegister_reg[10] [8]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [8]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [8]),
-        .O(SC_addResult_i_91_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_92
-       (.I0(\SR_shiftRegister_reg[15] [8]),
-        .I1(\SR_shiftRegister_reg[14] [8]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [8]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [8]),
-        .O(SC_addResult_i_92_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_93
-       (.I0(\SR_shiftRegister_reg[3] [7]),
-        .I1(\SR_shiftRegister_reg[2] [7]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [7]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [7]),
-        .O(SC_addResult_i_93_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_94
-       (.I0(\SR_shiftRegister_reg[7] [7]),
-        .I1(\SR_shiftRegister_reg[6] [7]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [7]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [7]),
-        .O(SC_addResult_i_94_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_95
-       (.I0(\SR_shiftRegister_reg[11] [7]),
-        .I1(\SR_shiftRegister_reg[10] [7]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [7]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [7]),
-        .O(SC_addResult_i_95_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_96
-       (.I0(\SR_shiftRegister_reg[15] [7]),
-        .I1(\SR_shiftRegister_reg[14] [7]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[13] [7]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[12] [7]),
-        .O(SC_addResult_i_96_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_97
-       (.I0(\SR_shiftRegister_reg[3] [6]),
-        .I1(\SR_shiftRegister_reg[2] [6]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[1] [6]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[0] [6]),
-        .O(SC_addResult_i_97_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_98
-       (.I0(\SR_shiftRegister_reg[7] [6]),
-        .I1(\SR_shiftRegister_reg[6] [6]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[5] [6]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[4] [6]),
-        .O(SC_addResult_i_98_n_0));
-  LUT6 #(
-    .INIT(64'hAFA0CFCFAFA0C0C0)) 
-    SC_addResult_i_99
-       (.I0(\SR_shiftRegister_reg[11] [6]),
-        .I1(\SR_shiftRegister_reg[10] [6]),
-        .I2(SR_readAddress[1]),
-        .I3(\SR_shiftRegister_reg[9] [6]),
-        .I4(SR_readAddress[0]),
-        .I5(\SR_shiftRegister_reg[8] [6]),
-        .O(SC_addResult_i_99_n_0));
-  LUT2 #(
-    .INIT(4'h6)) 
-    \SR_filteredSample[3]_i_2 
-       (.I0(SC_addResult_n_91),
-        .I1(L[15]),
-        .O(\SR_filteredSample[3]_i_2_n_0 ));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[0]),
-        .Q(O_filteredSample_OBUF[0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[10]),
-        .Q(O_filteredSample_OBUF[10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[11]),
-        .Q(O_filteredSample_OBUF[11]));
-  (* ADDER_THRESHOLD = "35" *) 
-  CARRY4 \SR_filteredSample_reg[11]_i_1 
-       (.CI(\SR_filteredSample_reg[7]_i_1_n_0 ),
-        .CO({\SR_filteredSample_reg[11]_i_1_n_0 ,\SR_filteredSample_reg[11]_i_1_n_1 ,\SR_filteredSample_reg[11]_i_1_n_2 ,\SR_filteredSample_reg[11]_i_1_n_3 }),
-        .CYINIT(\<const0> ),
-        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .O(p_0_in[11:8]),
-        .S(L[26:23]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[12]),
-        .Q(O_filteredSample_OBUF[12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[13]),
-        .Q(O_filteredSample_OBUF[13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[14]),
-        .Q(O_filteredSample_OBUF[14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[15]),
-        .Q(O_filteredSample_OBUF[15]));
-  (* ADDER_THRESHOLD = "35" *) 
-  CARRY4 \SR_filteredSample_reg[15]_i_1 
-       (.CI(\SR_filteredSample_reg[11]_i_1_n_0 ),
-        .CO({\SR_filteredSample_reg[15]_i_1_n_1 ,\SR_filteredSample_reg[15]_i_1_n_2 ,\SR_filteredSample_reg[15]_i_1_n_3 }),
-        .CYINIT(\<const0> ),
-        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .O(p_0_in[15:12]),
-        .S(L[30:27]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[1]),
-        .Q(O_filteredSample_OBUF[1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[2]),
-        .Q(O_filteredSample_OBUF[2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[3]),
-        .Q(O_filteredSample_OBUF[3]));
-  (* ADDER_THRESHOLD = "35" *) 
-  CARRY4 \SR_filteredSample_reg[3]_i_1 
-       (.CI(\<const0> ),
-        .CO({\SR_filteredSample_reg[3]_i_1_n_0 ,\SR_filteredSample_reg[3]_i_1_n_1 ,\SR_filteredSample_reg[3]_i_1_n_2 ,\SR_filteredSample_reg[3]_i_1_n_3 }),
-        .CYINIT(\<const0> ),
-        .DI({\<const0> ,\<const0> ,\<const0> ,SC_addResult_n_91}),
-        .O(p_0_in[3:0]),
-        .S({L[18:16],\SR_filteredSample[3]_i_2_n_0 }));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[4]),
-        .Q(O_filteredSample_OBUF[4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[5]),
-        .Q(O_filteredSample_OBUF[5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[6]),
-        .Q(O_filteredSample_OBUF[6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[7]),
-        .Q(O_filteredSample_OBUF[7]));
-  (* ADDER_THRESHOLD = "35" *) 
-  CARRY4 \SR_filteredSample_reg[7]_i_1 
-       (.CI(\SR_filteredSample_reg[3]_i_1_n_0 ),
-        .CO({\SR_filteredSample_reg[7]_i_1_n_0 ,\SR_filteredSample_reg[7]_i_1_n_1 ,\SR_filteredSample_reg[7]_i_1_n_2 ,\SR_filteredSample_reg[7]_i_1_n_3 }),
-        .CYINIT(\<const0> ),
-        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
-        .O(p_0_in[7:4]),
-        .S(L[22:19]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[8]),
-        .Q(O_filteredSample_OBUF[8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_filteredSample_reg[9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadOutput_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(p_0_in[9]),
-        .Q(O_filteredSample_OBUF[9]));
-  LUT2 #(
-    .INIT(4'h1)) 
-    \SR_readAddress[0]_i_1 
-       (.I0(SR_readAddress[0]),
-        .I1(I_initAddress_IBUF),
-        .O(\SR_readAddress[0]_i_1_n_0 ));
-  LUT3 #(
-    .INIT(8'h06)) 
-    \SR_readAddress[1]_i_1 
-       (.I0(SR_readAddress[1]),
-        .I1(SR_readAddress[0]),
-        .I2(I_initAddress_IBUF),
-        .O(\SR_readAddress[1]_i_1_n_0 ));
-  LUT4 #(
-    .INIT(16'h006A)) 
-    \SR_readAddress[2]_i_1 
-       (.I0(SR_readAddress[2]),
-        .I1(SR_readAddress[1]),
-        .I2(SR_readAddress[0]),
-        .I3(I_initAddress_IBUF),
-        .O(\SR_readAddress[2]_i_1_n_0 ));
-  LUT2 #(
-    .INIT(4'hE)) 
-    \SR_readAddress[3]_i_1 
-       (.I0(I_incrAddress_IBUF),
-        .I1(I_initAddress_IBUF),
-        .O(\SR_readAddress[3]_i_1_n_0 ));
-  LUT5 #(
-    .INIT(32'h00006AAA)) 
-    \SR_readAddress[3]_i_2 
-       (.I0(SR_readAddress[3]),
-        .I1(SR_readAddress[2]),
-        .I2(SR_readAddress[0]),
-        .I3(SR_readAddress[1]),
-        .I4(I_initAddress_IBUF),
-        .O(\SR_readAddress[3]_i_2_n_0 ));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_readAddress_reg[0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_readAddress[3]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(\SR_readAddress[0]_i_1_n_0 ),
-        .Q(SR_readAddress[0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_readAddress_reg[1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_readAddress[3]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(\SR_readAddress[1]_i_1_n_0 ),
-        .Q(SR_readAddress[1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_readAddress_reg[2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_readAddress[3]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(\SR_readAddress[2]_i_1_n_0 ),
-        .Q(SR_readAddress[2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_readAddress_reg[3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_readAddress[3]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(\SR_readAddress[3]_i_2_n_0 ),
-        .Q(SR_readAddress[3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[0]),
-        .Q(\SR_shiftRegister_reg[0] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[10]),
-        .Q(\SR_shiftRegister_reg[0] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[11]),
-        .Q(\SR_shiftRegister_reg[0] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[12]),
-        .Q(\SR_shiftRegister_reg[0] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[13]),
-        .Q(\SR_shiftRegister_reg[0] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[14]),
-        .Q(\SR_shiftRegister_reg[0] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[15]),
-        .Q(\SR_shiftRegister_reg[0] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[1]),
-        .Q(\SR_shiftRegister_reg[0] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[2]),
-        .Q(\SR_shiftRegister_reg[0] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[3]),
-        .Q(\SR_shiftRegister_reg[0] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[4]),
-        .Q(\SR_shiftRegister_reg[0] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[5]),
-        .Q(\SR_shiftRegister_reg[0] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[6]),
-        .Q(\SR_shiftRegister_reg[0] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[7]),
-        .Q(\SR_shiftRegister_reg[0] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[8]),
-        .Q(\SR_shiftRegister_reg[0] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[0][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(I_inputSample_IBUF[9]),
-        .Q(\SR_shiftRegister_reg[0] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [0]),
-        .Q(\SR_shiftRegister_reg[10] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [10]),
-        .Q(\SR_shiftRegister_reg[10] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [11]),
-        .Q(\SR_shiftRegister_reg[10] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [12]),
-        .Q(\SR_shiftRegister_reg[10] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [13]),
-        .Q(\SR_shiftRegister_reg[10] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [14]),
-        .Q(\SR_shiftRegister_reg[10] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [15]),
-        .Q(\SR_shiftRegister_reg[10] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [1]),
-        .Q(\SR_shiftRegister_reg[10] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [2]),
-        .Q(\SR_shiftRegister_reg[10] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [3]),
-        .Q(\SR_shiftRegister_reg[10] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [4]),
-        .Q(\SR_shiftRegister_reg[10] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [5]),
-        .Q(\SR_shiftRegister_reg[10] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [6]),
-        .Q(\SR_shiftRegister_reg[10] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [7]),
-        .Q(\SR_shiftRegister_reg[10] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [8]),
-        .Q(\SR_shiftRegister_reg[10] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[10][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[9] [9]),
-        .Q(\SR_shiftRegister_reg[10] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [0]),
-        .Q(\SR_shiftRegister_reg[11] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [10]),
-        .Q(\SR_shiftRegister_reg[11] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [11]),
-        .Q(\SR_shiftRegister_reg[11] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [12]),
-        .Q(\SR_shiftRegister_reg[11] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [13]),
-        .Q(\SR_shiftRegister_reg[11] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [14]),
-        .Q(\SR_shiftRegister_reg[11] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [15]),
-        .Q(\SR_shiftRegister_reg[11] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [1]),
-        .Q(\SR_shiftRegister_reg[11] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [2]),
-        .Q(\SR_shiftRegister_reg[11] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [3]),
-        .Q(\SR_shiftRegister_reg[11] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [4]),
-        .Q(\SR_shiftRegister_reg[11] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [5]),
-        .Q(\SR_shiftRegister_reg[11] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [6]),
-        .Q(\SR_shiftRegister_reg[11] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [7]),
-        .Q(\SR_shiftRegister_reg[11] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [8]),
-        .Q(\SR_shiftRegister_reg[11] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[11][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[10] [9]),
-        .Q(\SR_shiftRegister_reg[11] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [0]),
-        .Q(\SR_shiftRegister_reg[12] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [10]),
-        .Q(\SR_shiftRegister_reg[12] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [11]),
-        .Q(\SR_shiftRegister_reg[12] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [12]),
-        .Q(\SR_shiftRegister_reg[12] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [13]),
-        .Q(\SR_shiftRegister_reg[12] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [14]),
-        .Q(\SR_shiftRegister_reg[12] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [15]),
-        .Q(\SR_shiftRegister_reg[12] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [1]),
-        .Q(\SR_shiftRegister_reg[12] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [2]),
-        .Q(\SR_shiftRegister_reg[12] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [3]),
-        .Q(\SR_shiftRegister_reg[12] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [4]),
-        .Q(\SR_shiftRegister_reg[12] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [5]),
-        .Q(\SR_shiftRegister_reg[12] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [6]),
-        .Q(\SR_shiftRegister_reg[12] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [7]),
-        .Q(\SR_shiftRegister_reg[12] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [8]),
-        .Q(\SR_shiftRegister_reg[12] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[12][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[11] [9]),
-        .Q(\SR_shiftRegister_reg[12] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [0]),
-        .Q(\SR_shiftRegister_reg[13] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [10]),
-        .Q(\SR_shiftRegister_reg[13] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [11]),
-        .Q(\SR_shiftRegister_reg[13] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [12]),
-        .Q(\SR_shiftRegister_reg[13] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [13]),
-        .Q(\SR_shiftRegister_reg[13] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [14]),
-        .Q(\SR_shiftRegister_reg[13] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [15]),
-        .Q(\SR_shiftRegister_reg[13] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [1]),
-        .Q(\SR_shiftRegister_reg[13] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [2]),
-        .Q(\SR_shiftRegister_reg[13] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [3]),
-        .Q(\SR_shiftRegister_reg[13] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [4]),
-        .Q(\SR_shiftRegister_reg[13] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [5]),
-        .Q(\SR_shiftRegister_reg[13] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [6]),
-        .Q(\SR_shiftRegister_reg[13] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [7]),
-        .Q(\SR_shiftRegister_reg[13] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [8]),
-        .Q(\SR_shiftRegister_reg[13] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[13][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[12] [9]),
-        .Q(\SR_shiftRegister_reg[13] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [0]),
-        .Q(\SR_shiftRegister_reg[14] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [10]),
-        .Q(\SR_shiftRegister_reg[14] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [11]),
-        .Q(\SR_shiftRegister_reg[14] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [12]),
-        .Q(\SR_shiftRegister_reg[14] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [13]),
-        .Q(\SR_shiftRegister_reg[14] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [14]),
-        .Q(\SR_shiftRegister_reg[14] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [15]),
-        .Q(\SR_shiftRegister_reg[14] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [1]),
-        .Q(\SR_shiftRegister_reg[14] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [2]),
-        .Q(\SR_shiftRegister_reg[14] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [3]),
-        .Q(\SR_shiftRegister_reg[14] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [4]),
-        .Q(\SR_shiftRegister_reg[14] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [5]),
-        .Q(\SR_shiftRegister_reg[14] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [6]),
-        .Q(\SR_shiftRegister_reg[14] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [7]),
-        .Q(\SR_shiftRegister_reg[14] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [8]),
-        .Q(\SR_shiftRegister_reg[14] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[14][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[13] [9]),
-        .Q(\SR_shiftRegister_reg[14] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [0]),
-        .Q(\SR_shiftRegister_reg[15] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [10]),
-        .Q(\SR_shiftRegister_reg[15] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [11]),
-        .Q(\SR_shiftRegister_reg[15] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [12]),
-        .Q(\SR_shiftRegister_reg[15] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [13]),
-        .Q(\SR_shiftRegister_reg[15] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [14]),
-        .Q(\SR_shiftRegister_reg[15] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [15]),
-        .Q(\SR_shiftRegister_reg[15] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [1]),
-        .Q(\SR_shiftRegister_reg[15] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [2]),
-        .Q(\SR_shiftRegister_reg[15] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [3]),
-        .Q(\SR_shiftRegister_reg[15] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [4]),
-        .Q(\SR_shiftRegister_reg[15] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [5]),
-        .Q(\SR_shiftRegister_reg[15] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [6]),
-        .Q(\SR_shiftRegister_reg[15] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [7]),
-        .Q(\SR_shiftRegister_reg[15] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [8]),
-        .Q(\SR_shiftRegister_reg[15] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[15][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[14] [9]),
-        .Q(\SR_shiftRegister_reg[15] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [0]),
-        .Q(\SR_shiftRegister_reg[1] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [10]),
-        .Q(\SR_shiftRegister_reg[1] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [11]),
-        .Q(\SR_shiftRegister_reg[1] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [12]),
-        .Q(\SR_shiftRegister_reg[1] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [13]),
-        .Q(\SR_shiftRegister_reg[1] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [14]),
-        .Q(\SR_shiftRegister_reg[1] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [15]),
-        .Q(\SR_shiftRegister_reg[1] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [1]),
-        .Q(\SR_shiftRegister_reg[1] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [2]),
-        .Q(\SR_shiftRegister_reg[1] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [3]),
-        .Q(\SR_shiftRegister_reg[1] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [4]),
-        .Q(\SR_shiftRegister_reg[1] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [5]),
-        .Q(\SR_shiftRegister_reg[1] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [6]),
-        .Q(\SR_shiftRegister_reg[1] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [7]),
-        .Q(\SR_shiftRegister_reg[1] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [8]),
-        .Q(\SR_shiftRegister_reg[1] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[1][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[0] [9]),
-        .Q(\SR_shiftRegister_reg[1] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [0]),
-        .Q(\SR_shiftRegister_reg[2] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [10]),
-        .Q(\SR_shiftRegister_reg[2] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [11]),
-        .Q(\SR_shiftRegister_reg[2] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [12]),
-        .Q(\SR_shiftRegister_reg[2] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [13]),
-        .Q(\SR_shiftRegister_reg[2] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [14]),
-        .Q(\SR_shiftRegister_reg[2] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [15]),
-        .Q(\SR_shiftRegister_reg[2] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [1]),
-        .Q(\SR_shiftRegister_reg[2] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [2]),
-        .Q(\SR_shiftRegister_reg[2] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [3]),
-        .Q(\SR_shiftRegister_reg[2] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [4]),
-        .Q(\SR_shiftRegister_reg[2] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [5]),
-        .Q(\SR_shiftRegister_reg[2] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [6]),
-        .Q(\SR_shiftRegister_reg[2] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [7]),
-        .Q(\SR_shiftRegister_reg[2] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [8]),
-        .Q(\SR_shiftRegister_reg[2] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[2][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[1] [9]),
-        .Q(\SR_shiftRegister_reg[2] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [0]),
-        .Q(\SR_shiftRegister_reg[3] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [10]),
-        .Q(\SR_shiftRegister_reg[3] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [11]),
-        .Q(\SR_shiftRegister_reg[3] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [12]),
-        .Q(\SR_shiftRegister_reg[3] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [13]),
-        .Q(\SR_shiftRegister_reg[3] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [14]),
-        .Q(\SR_shiftRegister_reg[3] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [15]),
-        .Q(\SR_shiftRegister_reg[3] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [1]),
-        .Q(\SR_shiftRegister_reg[3] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [2]),
-        .Q(\SR_shiftRegister_reg[3] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [3]),
-        .Q(\SR_shiftRegister_reg[3] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [4]),
-        .Q(\SR_shiftRegister_reg[3] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [5]),
-        .Q(\SR_shiftRegister_reg[3] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [6]),
-        .Q(\SR_shiftRegister_reg[3] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [7]),
-        .Q(\SR_shiftRegister_reg[3] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [8]),
-        .Q(\SR_shiftRegister_reg[3] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[3][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[2] [9]),
-        .Q(\SR_shiftRegister_reg[3] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [0]),
-        .Q(\SR_shiftRegister_reg[4] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [10]),
-        .Q(\SR_shiftRegister_reg[4] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [11]),
-        .Q(\SR_shiftRegister_reg[4] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [12]),
-        .Q(\SR_shiftRegister_reg[4] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [13]),
-        .Q(\SR_shiftRegister_reg[4] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [14]),
-        .Q(\SR_shiftRegister_reg[4] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [15]),
-        .Q(\SR_shiftRegister_reg[4] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [1]),
-        .Q(\SR_shiftRegister_reg[4] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [2]),
-        .Q(\SR_shiftRegister_reg[4] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [3]),
-        .Q(\SR_shiftRegister_reg[4] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [4]),
-        .Q(\SR_shiftRegister_reg[4] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [5]),
-        .Q(\SR_shiftRegister_reg[4] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [6]),
-        .Q(\SR_shiftRegister_reg[4] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [7]),
-        .Q(\SR_shiftRegister_reg[4] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [8]),
-        .Q(\SR_shiftRegister_reg[4] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[4][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[3] [9]),
-        .Q(\SR_shiftRegister_reg[4] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [0]),
-        .Q(\SR_shiftRegister_reg[5] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [10]),
-        .Q(\SR_shiftRegister_reg[5] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [11]),
-        .Q(\SR_shiftRegister_reg[5] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [12]),
-        .Q(\SR_shiftRegister_reg[5] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [13]),
-        .Q(\SR_shiftRegister_reg[5] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [14]),
-        .Q(\SR_shiftRegister_reg[5] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [15]),
-        .Q(\SR_shiftRegister_reg[5] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [1]),
-        .Q(\SR_shiftRegister_reg[5] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [2]),
-        .Q(\SR_shiftRegister_reg[5] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [3]),
-        .Q(\SR_shiftRegister_reg[5] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [4]),
-        .Q(\SR_shiftRegister_reg[5] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [5]),
-        .Q(\SR_shiftRegister_reg[5] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [6]),
-        .Q(\SR_shiftRegister_reg[5] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [7]),
-        .Q(\SR_shiftRegister_reg[5] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [8]),
-        .Q(\SR_shiftRegister_reg[5] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[5][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[4] [9]),
-        .Q(\SR_shiftRegister_reg[5] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [0]),
-        .Q(\SR_shiftRegister_reg[6] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [10]),
-        .Q(\SR_shiftRegister_reg[6] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [11]),
-        .Q(\SR_shiftRegister_reg[6] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [12]),
-        .Q(\SR_shiftRegister_reg[6] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [13]),
-        .Q(\SR_shiftRegister_reg[6] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [14]),
-        .Q(\SR_shiftRegister_reg[6] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [15]),
-        .Q(\SR_shiftRegister_reg[6] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [1]),
-        .Q(\SR_shiftRegister_reg[6] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [2]),
-        .Q(\SR_shiftRegister_reg[6] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [3]),
-        .Q(\SR_shiftRegister_reg[6] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [4]),
-        .Q(\SR_shiftRegister_reg[6] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [5]),
-        .Q(\SR_shiftRegister_reg[6] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [6]),
-        .Q(\SR_shiftRegister_reg[6] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [7]),
-        .Q(\SR_shiftRegister_reg[6] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [8]),
-        .Q(\SR_shiftRegister_reg[6] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[6][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[5] [9]),
-        .Q(\SR_shiftRegister_reg[6] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [0]),
-        .Q(\SR_shiftRegister_reg[7] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [10]),
-        .Q(\SR_shiftRegister_reg[7] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [11]),
-        .Q(\SR_shiftRegister_reg[7] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [12]),
-        .Q(\SR_shiftRegister_reg[7] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [13]),
-        .Q(\SR_shiftRegister_reg[7] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [14]),
-        .Q(\SR_shiftRegister_reg[7] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [15]),
-        .Q(\SR_shiftRegister_reg[7] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [1]),
-        .Q(\SR_shiftRegister_reg[7] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [2]),
-        .Q(\SR_shiftRegister_reg[7] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [3]),
-        .Q(\SR_shiftRegister_reg[7] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [4]),
-        .Q(\SR_shiftRegister_reg[7] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [5]),
-        .Q(\SR_shiftRegister_reg[7] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [6]),
-        .Q(\SR_shiftRegister_reg[7] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [7]),
-        .Q(\SR_shiftRegister_reg[7] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [8]),
-        .Q(\SR_shiftRegister_reg[7] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[7][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[6] [9]),
-        .Q(\SR_shiftRegister_reg[7] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [0]),
-        .Q(\SR_shiftRegister_reg[8] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [10]),
-        .Q(\SR_shiftRegister_reg[8] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [11]),
-        .Q(\SR_shiftRegister_reg[8] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [12]),
-        .Q(\SR_shiftRegister_reg[8] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [13]),
-        .Q(\SR_shiftRegister_reg[8] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [14]),
-        .Q(\SR_shiftRegister_reg[8] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [15]),
-        .Q(\SR_shiftRegister_reg[8] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [1]),
-        .Q(\SR_shiftRegister_reg[8] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [2]),
-        .Q(\SR_shiftRegister_reg[8] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [3]),
-        .Q(\SR_shiftRegister_reg[8] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [4]),
-        .Q(\SR_shiftRegister_reg[8] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [5]),
-        .Q(\SR_shiftRegister_reg[8] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [6]),
-        .Q(\SR_shiftRegister_reg[8] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [7]),
-        .Q(\SR_shiftRegister_reg[8] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [8]),
-        .Q(\SR_shiftRegister_reg[8] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[8][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[7] [9]),
-        .Q(\SR_shiftRegister_reg[8] [9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [0]),
-        .Q(\SR_shiftRegister_reg[9] [0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [10]),
-        .Q(\SR_shiftRegister_reg[9] [10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [11]),
-        .Q(\SR_shiftRegister_reg[9] [11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [12]),
-        .Q(\SR_shiftRegister_reg[9] [12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [13]),
-        .Q(\SR_shiftRegister_reg[9] [13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [14]),
-        .Q(\SR_shiftRegister_reg[9] [14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [15]),
-        .Q(\SR_shiftRegister_reg[9] [15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [1]),
-        .Q(\SR_shiftRegister_reg[9] [1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [2]),
-        .Q(\SR_shiftRegister_reg[9] [2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [3]),
-        .Q(\SR_shiftRegister_reg[9] [3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [4]),
-        .Q(\SR_shiftRegister_reg[9] [4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [5]),
-        .Q(\SR_shiftRegister_reg[9] [5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [6]),
-        .Q(\SR_shiftRegister_reg[9] [6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [7]),
-        .Q(\SR_shiftRegister_reg[9] [7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [8]),
-        .Q(\SR_shiftRegister_reg[9] [8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_shiftRegister_reg[9][9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(I_loadShift_IBUF),
-        .CLR(I_reset_IBUF),
-        .D(\SR_shiftRegister_reg[8] [9]),
-        .Q(\SR_shiftRegister_reg[9] [9]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[0]_i_1 
-       (.I0(SC_addResult_n_105),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[0]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[10]_i_1 
-       (.I0(SC_addResult_n_95),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[10]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[11]_i_1 
-       (.I0(SC_addResult_n_94),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[11]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[12]_i_1 
-       (.I0(SC_addResult_n_93),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[12]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[13]_i_1 
-       (.I0(SC_addResult_n_92),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[13]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[14]_i_1 
-       (.I0(SC_addResult_n_91),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[14]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[15]_i_1 
-       (.I0(L[15]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[15]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[16]_i_1 
-       (.I0(L[16]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[16]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[17]_i_1 
-       (.I0(L[17]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[17]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[18]_i_1 
-       (.I0(L[18]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[18]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[19]_i_1 
-       (.I0(L[19]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[19]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[1]_i_1 
-       (.I0(SC_addResult_n_104),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[1]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[20]_i_1 
-       (.I0(L[20]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[20]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[21]_i_1 
-       (.I0(L[21]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[21]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[22]_i_1 
-       (.I0(L[22]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[22]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[23]_i_1 
-       (.I0(L[23]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[23]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[24]_i_1 
-       (.I0(L[24]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[24]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[25]_i_1 
-       (.I0(L[25]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[25]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[26]_i_1 
-       (.I0(L[26]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[26]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[27]_i_1 
-       (.I0(L[27]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[27]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[28]_i_1 
-       (.I0(L[28]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[28]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[29]_i_1 
-       (.I0(L[29]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[29]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[2]_i_1 
-       (.I0(SC_addResult_n_103),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[2]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[30]_i_1 
-       (.I0(L[30]),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[30]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[31]_i_1 
-       (.I0(SC_addResult_n_74),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[31]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[32]_i_1 
-       (.I0(SC_addResult_n_73),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[32]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[33]_i_1 
-       (.I0(SC_addResult_n_72),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[33]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[34]_i_1 
-       (.I0(SC_addResult_n_71),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[34]));
-  LUT2 #(
-    .INIT(4'hE)) 
-    \SR_sum[35]_i_1 
-       (.I0(I_loadSum_IBUF),
-        .I1(I_initSum_IBUF),
-        .O(\SR_sum[35]_i_1_n_0 ));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[35]_i_2 
-       (.I0(SC_addResult_n_70),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[35]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[3]_i_1 
-       (.I0(SC_addResult_n_102),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[3]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[4]_i_1 
-       (.I0(SC_addResult_n_101),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[4]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[5]_i_1 
-       (.I0(SC_addResult_n_100),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[5]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[6]_i_1 
-       (.I0(SC_addResult_n_99),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[6]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[7]_i_1 
-       (.I0(SC_addResult_n_98),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[7]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[8]_i_1 
-       (.I0(SC_addResult_n_97),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[8]));
-  LUT2 #(
-    .INIT(4'h2)) 
-    \SR_sum[9]_i_1 
-       (.I0(SC_addResult_n_96),
-        .I1(I_initSum_IBUF),
-        .O(p_1_in[9]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[0] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[0]),
-        .Q(SR_sum[0]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[10] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[10]),
-        .Q(SR_sum[10]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[11] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[11]),
-        .Q(SR_sum[11]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[12] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[12]),
-        .Q(SR_sum[12]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[13] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[13]),
-        .Q(SR_sum[13]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[14] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[14]),
-        .Q(SR_sum[14]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[15] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[15]),
-        .Q(SR_sum[15]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[16] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[16]),
-        .Q(SR_sum[16]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[17] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[17]),
-        .Q(SR_sum[17]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[18] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[18]),
-        .Q(SR_sum[18]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[19] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[19]),
-        .Q(SR_sum[19]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[1] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[1]),
-        .Q(SR_sum[1]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[20] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[20]),
-        .Q(SR_sum[20]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[21] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[21]),
-        .Q(SR_sum[21]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[22] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[22]),
-        .Q(SR_sum[22]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[23] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[23]),
-        .Q(SR_sum[23]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[24] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[24]),
-        .Q(SR_sum[24]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[25] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[25]),
-        .Q(SR_sum[25]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[26] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[26]),
-        .Q(SR_sum[26]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[27] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[27]),
-        .Q(SR_sum[27]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[28] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[28]),
-        .Q(SR_sum[28]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[29] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[29]),
-        .Q(SR_sum[29]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[2] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[2]),
-        .Q(SR_sum[2]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[30] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[30]),
-        .Q(SR_sum[30]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[31] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[31]),
-        .Q(SR_sum[31]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[32] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[32]),
-        .Q(SR_sum[32]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[33] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[33]),
-        .Q(SR_sum[33]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[34] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[34]),
-        .Q(SR_sum[34]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[35] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[35]),
-        .Q(SR_sum[35]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[3] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[3]),
-        .Q(SR_sum[3]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[4] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[4]),
-        .Q(SR_sum[4]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[5] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[5]),
-        .Q(SR_sum[5]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[6] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[6]),
-        .Q(SR_sum[6]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[7] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[7]),
-        .Q(SR_sum[7]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[8] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[8]),
-        .Q(SR_sum[8]));
-  FDCE #(
-    .INIT(1'b0)) 
-    \SR_sum_reg[9] 
-       (.C(I_clock_IBUF_BUFG),
-        .CE(\SR_sum[35]_i_1_n_0 ),
-        .CLR(I_reset_IBUF),
-        .D(p_1_in[9]),
-        .Q(SR_sum[9]));
-  VCC VCC
-       (.P(\<const1> ));
-endmodule
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 311b39dcdad8ec351bd777c66e6ac258dc127e8b..2648e095cefb4b49a521110461aa7ea2dde4fc78 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -45,7 +45,7 @@ entity operativeUnit is
         I_incrAddress    : in  std_logic;                     -- Control signal to increment register read address
         I_initSum        : in  std_logic;                     -- Control signal to initialize the MAC register
         I_loadSum        : in  std_logic;                     -- Control signal to load the MAC register;
-        I_loadY          : in  std_logic;                     -- Control signal to load Y register
+        I_loadOutput     : in  std_logic;                     -- Control signal to load Y register
         O_processingDone : out std_logic;                     -- Indicate that processing is done
         O_filteredSample : out std_logic_vector(15 downto 0)   -- filtered sample
         );
@@ -118,33 +118,40 @@ begin
     begin  -- process shift
         if I_reset = '1' then           -- asynchronous reset (active high)
             SR_shiftRegister <= (others => (others => '0'));
-        elsif I_loadShift = '1' and rising_edge(I_clock) then
-            SR_shiftRegister(1 downto 15) <= SR_shiftRegister(0 downto 14);
-            SR_shiftRegister(0) <= I_inputSample;
-        end if;
+       elsif rising_edge(I_clock) then
+           if I_loadShift = '1' then 
+            SR_shiftRegister(1 to 15) <= SR_shiftRegister(0 to 14);
+            SR_shiftRegister(0) <= signed(I_inputSample);
+           end if;
+        end if; 
 
     end process shift;
 
     -- Process to describe the counter providing the selection adresses
     -- of the multiplexers
-    incr_address : process (I_clock) is
+    incr_address : process (I_reset, I_clock) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_readAddress <= 0;
-        elsif I_initAddress = '1' and rising_edge(I_clock) then
-            SR_readAddress <= 0;
-        elsif I_incrAddress = '1' and rising_edge(I_clock)  then
-            SR_readAddress <= SR_readAddress + 1;
-        end if;
+        elsif rising_edge(I_clock) then
+             if I_initAddress = '1' then
+               SR_readAddress <= 0;
+             elsif I_incrAddress = '1' then
+               if SR_readAddress < 15 then 
+                 SR_readAddress <= SR_readAddress + 1;
+               end if ; 
+             end if;
+        
+             end if; 
     end process incr_address;
 
     -- Signal detecting that the next cycle will be the one
     -- providing the last product used to compute the convolution
-    O_processingDone <= '1' when SR_readAddress = 15;
+    O_processingDone <= '1' when SR_readAddress = 15 else '0';
 
     -- Signals connected with multiplexers (SIMPLY inferred with table indices)
     SC_multOperand1 <= SR_shiftRegister(SR_readAddress);             -- 16 bits
-    SC_multOperand2 <= SR_shiftRegister(15 - SR_readAddress);             -- 16 bits
+    SC_multOperand2 <= SR_coefRegister(SR_readAddress);             -- 16 bits
 
     -- Multiplication of the operands
     SC_MultResult   <= SC_multOperand1*SC_multOperand2;             -- 32 bits
@@ -155,18 +162,34 @@ begin
     -- Register to store the accumulated value if the loadSum is active
     -- It also reduces the width of the sum to fit to the input and output
     -- signal widths (be careful with truncating/rounding)
-    sum_acc : process (_BLANK_) is
+    sum_acc : process (I_reset, I_clock) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_sum <= (others => '0');
-        elsif _BLANK_
+        elsif rising_edge(I_clock) then
+            if I_initSum = '1' then
+                SR_sum <= (others => '0');
+            elsif I_loadSum = '1' then
+                SR_sum <= SC_addResult;
+            end if;
         end if;
     end process sum_acc;
 
     -- Register to store the final result if the loadOuput is active
-    store_result : process (_BLANK_) is
+    store_result : process (I_reset, I_clock) is
     begin
-        _BLANK_
+        if I_reset = '1' then
+            SR_filteredSample <= (others => '0');
+        elsif rising_edge(I_clock) then
+                if I_loadOutput = '1' then
+                   if SR_sum(14) = '1' then         
+                       SR_filteredSample <= SR_sum(30 downto 15)+1;
+                   else 
+                       SR_filteredSample <= SR_sum(30 downto 15);
+                   end if;
+                end if;
+        end if;
+            
 
     end process store_result;