From 3b12bd25c24b8136aebc9becacc29a38631f2294 Mon Sep 17 00:00:00 2001
From: Jean-Noel Bazin <jn.bazin@imt-atlantique.fr>
Date: Thu, 24 Apr 2025 10:08:29 +0200
Subject: [PATCH] 1st version of working synthe
---
.gitignore | 3 +
README.md | 103 +-
docs/wave_generator.drawio | 52 +
proj/cleanup.cmd | 22 +
proj/cleanup.sh | 16 +
proj/create_project.tcl | 138 +
proj/tb_wave_generator_behav.wcfg | 148 +
src/constraints/NexysVideo_Master.xdc | 365 ++
src/hdl/ADSR_module.vhd | 97 +
src/hdl/PS2Receiver.v | 84 +
src/hdl/TWICtl.vhd | 571 ++
src/hdl/audioProc.v | 285 +
src/hdl/audio_init.v | 246 +
src/hdl/debounce.v | 108 +
src/hdl/debouncer.v | 42 +
src/hdl/i2s_ctl.vhd | 296 +
src/hdl/module_A.vhd | 58 +
src/hdl/module_B.vhd | 47 +
src/hdl/module_C.vhd | 45 +
src/hdl/module_D.vhd | 45 +
src/hdl/module_E.vhd | 42 +
src/hdl/module_F.vhd | 30 +
src/hdl/module_G.vhd | 23 +
src/hdl/module_H.vhd | 25 +
src/hdl/module_I.vhd | 36 +
src/hdl/synthesizer.vhd | 80 +
src/hdl/tb_ADSR_module.vhd | 94 +
src/hdl/tb_module_B.vhd | 93 +
src/hdl/tb_module_C.vhd | 96 +
src/hdl/tb_module_D.vhd | 96 +
src/hdl/tb_module_E.vhd | 96 +
src/hdl/tb_module_F.vhd | 40 +
src/hdl/tb_module_G.vhd | 66 +
src/hdl/tb_module_H.vhd | 36 +
src/hdl/tb_module_I.vhd | 49 +
src/hdl/tb_wave_generator.vhd | 73 +
src/hdl/tone_generator.vhd | 85 +
src/hdl/wave_generator.vhd | 161 +
src/hdl/wave_package.vhd | 71 +
src/ip/clk_wiz_0/clk_wiz_0.dcp | Bin 0 -> 12528 bytes
src/ip/clk_wiz_0/clk_wiz_0.upgrade_log | 332 ++
src/ip/clk_wiz_0/clk_wiz_0.v | 100 +
src/ip/clk_wiz_0/clk_wiz_0.vho | 103 +
src/ip/clk_wiz_0/clk_wiz_0.xci | 525 ++
src/ip/clk_wiz_0/clk_wiz_0.xdc | 59 +
src/ip/clk_wiz_0/clk_wiz_0.xml | 4933 +++++++++++++++++
src/ip/clk_wiz_0/clk_wiz_0_board.xdc | 2 +
src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 215 +
src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc | 56 +
src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v | 278 +
src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl | 218 +
src/ip/clk_wiz_0/clk_wiz_0_stub.v | 24 +
src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 33 +
.../clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt | 115 +
54 files changed, 10969 insertions(+), 87 deletions(-)
create mode 100644 .gitignore
create mode 100644 docs/wave_generator.drawio
create mode 100644 proj/cleanup.cmd
create mode 100644 proj/cleanup.sh
create mode 100644 proj/create_project.tcl
create mode 100644 proj/tb_wave_generator_behav.wcfg
create mode 100644 src/constraints/NexysVideo_Master.xdc
create mode 100644 src/hdl/ADSR_module.vhd
create mode 100644 src/hdl/PS2Receiver.v
create mode 100644 src/hdl/TWICtl.vhd
create mode 100644 src/hdl/audioProc.v
create mode 100644 src/hdl/audio_init.v
create mode 100644 src/hdl/debounce.v
create mode 100644 src/hdl/debouncer.v
create mode 100644 src/hdl/i2s_ctl.vhd
create mode 100644 src/hdl/module_A.vhd
create mode 100644 src/hdl/module_B.vhd
create mode 100644 src/hdl/module_C.vhd
create mode 100644 src/hdl/module_D.vhd
create mode 100644 src/hdl/module_E.vhd
create mode 100644 src/hdl/module_F.vhd
create mode 100644 src/hdl/module_G.vhd
create mode 100644 src/hdl/module_H.vhd
create mode 100644 src/hdl/module_I.vhd
create mode 100644 src/hdl/synthesizer.vhd
create mode 100644 src/hdl/tb_ADSR_module.vhd
create mode 100644 src/hdl/tb_module_B.vhd
create mode 100644 src/hdl/tb_module_C.vhd
create mode 100644 src/hdl/tb_module_D.vhd
create mode 100644 src/hdl/tb_module_E.vhd
create mode 100644 src/hdl/tb_module_F.vhd
create mode 100644 src/hdl/tb_module_G.vhd
create mode 100644 src/hdl/tb_module_H.vhd
create mode 100644 src/hdl/tb_module_I.vhd
create mode 100644 src/hdl/tb_wave_generator.vhd
create mode 100644 src/hdl/tone_generator.vhd
create mode 100644 src/hdl/wave_generator.vhd
create mode 100644 src/hdl/wave_package.vhd
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.dcp
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.upgrade_log
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.v
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.vho
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.xci
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.xdc
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0.xml
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_board.xdc
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_stub.v
create mode 100644 src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
create mode 100644 src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..fd3734b
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+# Ignore vivado project files
+proj/Synthe*
+proj/.Xil
diff --git a/README.md b/README.md
index 62ea166..d0e95f5 100644
--- a/README.md
+++ b/README.md
@@ -1,93 +1,22 @@
-# tp-synthe-etudiant
-
-
-
-## Getting started
-
-To make it easy for you to get started with GitLab, here's a list of recommended next steps.
-
-Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
-
-## Add your files
-
-- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
-- [ ] [Add files using the command line](https://docs.gitlab.com/topics/git/add_files/#add-files-to-a-git-repository) or push an existing Git repository with the following command:
-
-```
-cd existing_repo
-git remote add origin https://gitlab.imt-atlantique.fr/tp-vhdl/tp-synthe-etudiant.git
-git branch -M main
-git push -uf origin main
-```
-
-## Integrate with your tools
-
-- [ ] [Set up project integrations](https://gitlab.imt-atlantique.fr/tp-vhdl/tp-synthe-etudiant/-/settings/integrations)
-
-## Collaborate with your team
-
-- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
-- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
-- [ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically)
-- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/)
-- [ ] [Set auto-merge](https://docs.gitlab.com/user/project/merge_requests/auto_merge/)
-
-## Test and Deploy
-
-Use the built-in continuous integration in GitLab.
-
-- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/)
-- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing (SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
-- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
-- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
-- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
-
-***
-
-# Editing this README
-
-When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thanks to [makeareadme.com](https://www.makeareadme.com/) for this template.
-
-## Suggestions for a good README
-
-Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information.
-
-## Name
-Choose a self-explaining name for your project.
+# Synthe
## Description
-Let people know what your project can do specifically. Provide context and add a link to any reference visitors might be unfamiliar with. A list of Features or a Background subsection can also be added here. If there are alternatives to your project, this is a good place to list differentiating factors.
-
-## Badges
-On some READMEs, you may see small images that convey metadata, such as whether or not all the tests are passing for the project. You can use Shields to add some to your README. Many services also have instructions for adding a badge.
-
-## Visuals
-Depending on what you are making, it can be a good idea to include screenshots or even a video (you'll frequently see GIFs rather than actual videos). Tools like ttygif can help, but check out Asciinema for a more sophisticated method.
-
-## Installation
-Within a particular ecosystem, there may be a common way of installing things, such as using Yarn, NuGet, or Homebrew. However, consider the possibility that whoever is reading your README is a novice and would like more guidance. Listing specific steps helps remove ambiguity and gets people to using your project as quickly as possible. If it only runs in a specific context like a particular programming language version or operating system or has dependencies that have to be installed manually, also add a Requirements subsection.
-
-## Usage
-Use examples liberally, and show the expected output if you can. It's helpful to have inline the smallest example of usage that you can demonstrate, while providing links to more sophisticated examples if they are too long to reasonably include in the README.
-
-## Support
-Tell people where they can go to for help. It can be any combination of an issue tracker, a chat room, an email address, etc.
-
-## Roadmap
-If you have ideas for releases in the future, it is a good idea to list them in the README.
-
-## Contributing
-State if you are open to contributions and what your requirements are for accepting them.
-
-For people who want to make changes to your project, it's helpful to have some documentation on how to get started. Perhaps there is a script that they should run or some environment variables that they need to set. Make these steps explicit. These instructions could also be useful to your future self.
+Project to build a digital synthesizer in VHDL.
+4 types of waveform can be played: sine, square, triangle, saw-tooth.
-You can also document commands to lint the code or run tests. These steps help to ensure high code quality and reduce the likelihood that the changes inadvertently break something. Having instructions for running tests is especially helpful if it requires external setup, such as starting a Selenium server for testing in a browser.
+## Play with USB keyboard
+Keys A Z E R T are used to play 5 tones:
+- A = Sol : 392 Hz
+- Z = Si-b : 466 Hz
+- E = Do : 523 Hz
+- R = Mi : 659 Hz
+- T = Fa : 698 Hz
-## Authors and acknowledgment
-Show your appreciation to those who have contributed to the project.
+You can play the famous part of "Funky town" by Lipps Inc.
-## License
-For open source projects, say how it is licensed.
+Do Do Si-b Do Sol Sol Do Fa Mi Do
+E E Z E A A E T R E
-## Project status
-If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers.
+The switches are use to configure the waveform:
+- sw1 sw0 : selects the fundamental waveform
+- sw
diff --git a/docs/wave_generator.drawio b/docs/wave_generator.drawio
new file mode 100644
index 0000000..6d65d82
--- /dev/null
+++ b/docs/wave_generator.drawio
@@ -0,0 +1,52 @@
+<mxfile host="Electron" agent="Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/26.2.2 Chrome/134.0.6998.178 Electron/35.1.2 Safari/537.36" version="26.2.2">
+ <diagram name="Page-1" id="ZRCvXX_TBlFcA-i0oMmK">
+ <mxGraphModel dx="3237" dy="1203" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
+ <root>
+ <mxCell id="0" />
+ <mxCell id="1" parent="0" />
+ <mxCell id="liv1zIGuVtiVySRaDl_v-15" value="" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#f5f5f5;fontColor=#333333;strokeColor=#666666;arcSize=3;" parent="1" vertex="1">
+ <mxGeometry y="40" width="1320" height="720" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-1" value="A" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="160" y="80" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-2" value="D" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="160" y="320" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-3" value="B" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="520" y="80" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-4" value="I" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="880" y="560" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-5" value="F" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="880" y="320" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-6" value="C" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="880" y="80" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-7" value="G" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="160" y="560" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-8" value="H" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="520" y="560" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-9" value="E" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
+ <mxGeometry x="520" y="320" width="280" height="160" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-10" value="I_clk" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
+ <mxGeometry x="-40" y="120" width="160" height="40" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-11" value="I_rst" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
+ <mxGeometry x="-40" y="200" width="160" height="40" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-12" value="I_wave_sel" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
+ <mxGeometry x="-40" y="280" width="160" height="40" as="geometry" />
+ </mxCell>
+ <mxCell id="liv1zIGuVtiVySRaDl_v-14" value="O_wav" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
+ <mxGeometry x="1200" y="120" width="160" height="40" as="geometry" />
+ </mxCell>
+ </root>
+ </mxGraphModel>
+ </diagram>
+</mxfile>
diff --git a/proj/cleanup.cmd b/proj/cleanup.cmd
new file mode 100644
index 0000000..3863d4a
--- /dev/null
+++ b/proj/cleanup.cmd
@@ -0,0 +1,22 @@
+@echo off
+rem delete all files from subfolders
+for /d /r %%i in (*) do del /f /q %%i\*
+rem delete all subfolders
+for /d %%i in (*) do rd /S /Q %%i
+
+rem unmark read only from all files
+attrib -R .\* /S
+
+rem mark read only those we wish to keep
+attrib +R .\create_project.tcl
+attrib +R .\cleanup.sh
+attrib +R .\cleanup.cmd
+attrib +R .\.gitignore
+attrib +R .\_READ_ME_.txt
+attrib +R .\tb_wave_generator_behav.wcfg
+
+rem delete all non read-only
+del /Q /A:-R .\*
+
+rem unmark read-only
+attrib -R .\*
diff --git a/proj/cleanup.sh b/proj/cleanup.sh
new file mode 100644
index 0000000..aff62f3
--- /dev/null
+++ b/proj/cleanup.sh
@@ -0,0 +1,16 @@
+# This script is useful for cleaning up the 'project'
+# directory of a Digilent Vivado-project git repository
+###
+# Run the following command to change permissions of
+# this 'cleanup' file if needed:
+# chmod u+x cleanup.sh
+###
+# Remove directories/subdirectories
+find . -mindepth 1 -type d -exec rm -rf {} +
+# Remove any other files than:
+find . -type f ! -name 'cleanup.sh' \
+ ! -name 'cleanup.cmd' \
+ ! -name 'create_project.tcl' \
+ ! -name '.gitignore' \
+ ! -name 'tb_wave_generator_behav.wcfg' \
+ -exec rm -rf {} +
diff --git a/proj/create_project.tcl b/proj/create_project.tcl
new file mode 100644
index 0000000..0460097
--- /dev/null
+++ b/proj/create_project.tcl
@@ -0,0 +1,138 @@
+# Run this script to create the Vivado project files in the WORKING DIRECTORY
+# If ::create_path global variable is set, the project is created under that path instead of the working dir
+
+if {[info exists ::create_path]} {
+ set dest_dir $::create_path
+} else {
+ set dest_dir [pwd]
+}
+puts "INFO: Creating new project in $dest_dir"
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set proj_name "Synthe"
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir ".."
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+
+set src_dir $origin_dir/src
+set repo_dir $origin_dir/repo
+
+# Set the board part number
+set part_num "xc7a200tsbg484-1"
+
+# Create project
+create_project $proj_name $dest_dir
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [get_projects $proj_name]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "part" "$part_num" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+ create_fileset -srcset sources_1
+}
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+ create_fileset -constrset constrs_1
+}
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
+
+
+# Add IPs
+add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
+
+# Add constraints
+add_files -fileset constrs_1 -quiet $src_dir/constraints
+
+# Add conventional sources
+add_files -quiet $src_dir/hdl
+
+# Set all VHDL files to 2008
+set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
+
+# Set testbenches as simulation only
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_wave_generator.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_ADSR_module.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_B.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_C.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_D.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_E.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_F.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_G.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_H.vhd]
+set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_I.vhd]
+
+#Set TOP module as not used in simulation
+set_property used_in_simulation false [get_files $src_dir/hdl/audioProc.v]
+
+
+# Refresh IP Repositories
+#update_ip_catalog
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+ create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
+} else {
+ set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
+ set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property "part" "$part_num" $obj
+set_property "steps.synth_design.args.fanout_limit" "400" $obj
+set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
+set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
+set_property "steps.synth_design.args.resource_sharing" "off" $obj
+set_property "steps.synth_design.args.no_lc" "1" $obj
+set_property "steps.synth_design.args.shreg_min_size" "5" $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+ create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+} else {
+ set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+ set_property flow "Vivado Implementation 2014" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property "part" "$part_num" $obj
+set_property "steps.write_bitstream.args.bin_file" "1" $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+# set tb_wave_generator as default test bench
+set_property top tb_module_B [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+update_compile_order -fileset sources_1
+
+
+
+#puts "INFO: Project created:$proj_name"
+
+# Comment the following section, if there is no block design
+# Create block design
+#source $origin_dir/src/bd/bt_gpio.tcl
+
+# Generate the wrapper
+#set design_name [get_bd_designs]
+#make_wrapper -files [get_files $design_name.bd] -top -import
+
+#set obj [get_filesets sources_1]
+#set_property "top" "bt_gpio_top" $obj
+
+#puts "INFO: Block design created: $design_name.bd"
diff --git a/proj/tb_wave_generator_behav.wcfg b/proj/tb_wave_generator_behav.wcfg
new file mode 100644
index 0000000..507a07b
--- /dev/null
+++ b/proj/tb_wave_generator_behav.wcfg
@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="tb_wave_generator_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="tb_wave_generator" />
+ <top_module name="wave_package" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000000 us"></ZoomStartTime>
+ <ZoomEndTime time="16.000001 us"></ZoomEndTime>
+ <Cursor1Time time="16.000000 us"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="276"></NameColumnWidth>
+ <ValueColumnWidth column_width="112"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="29" />
+ <wvobject type="logic" fp_name="/tb_wave_generator/clk">
+ <obj_property name="ElementShortName">clk</obj_property>
+ <obj_property name="ObjectShortName">clk</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/rst">
+ <obj_property name="ElementShortName">rst</obj_property>
+ <obj_property name="ObjectShortName">rst</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/wave_sel">
+ <obj_property name="ElementShortName">wave_sel[1:0]</obj_property>
+ <obj_property name="ObjectShortName">wave_sel[1:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/wav">
+ <obj_property name="ElementShortName">wav[7:0]</obj_property>
+ <obj_property name="ObjectShortName">wav[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/N">
+ <obj_property name="ElementShortName">N</obj_property>
+ <obj_property name="ObjectShortName">N</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/f0">
+ <obj_property name="ElementShortName">f0</obj_property>
+ <obj_property name="ObjectShortName">f0</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/fs">
+ <obj_property name="ElementShortName">fs</obj_property>
+ <obj_property name="ObjectShortName">fs</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/clk_period">
+ <obj_property name="ElementShortName">clk_period</obj_property>
+ <obj_property name="ObjectShortName">clk_period</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/uut/I_clk">
+ <obj_property name="ElementShortName">I_clk</obj_property>
+ <obj_property name="ObjectShortName">I_clk</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/uut/I_rst">
+ <obj_property name="ElementShortName">I_rst</obj_property>
+ <obj_property name="ObjectShortName">I_rst</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/I_wave_sel">
+ <obj_property name="ElementShortName">I_wave_sel[1:0]</obj_property>
+ <obj_property name="ObjectShortName">I_wave_sel[1:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/O_wav">
+ <obj_property name="ElementShortName">O_wav[7:0]</obj_property>
+ <obj_property name="ObjectShortName">O_wav[7:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+ <obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
+ <obj_property name="CellHeight">400</obj_property>
+ <obj_property name="AnalogYRangeType">ANALOG_YRANGETYPE_AUTO</obj_property>
+ <obj_property name="AnalogYRangeMin">0.000000</obj_property>
+ <obj_property name="AnalogYRRangeMax">0.000000</obj_property>
+ <obj_property name="AnalogInterpolation">ANALOG_INTERPOLATION_HOLD</obj_property>
+ <obj_property name="AnalogOffscale">ANALOG_OFFSCALE_HIDE</obj_property>
+ <obj_property name="AnalogHorizLine">0.000000</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_addr">
+ <obj_property name="ElementShortName">S_addr[5:0]</obj_property>
+ <obj_property name="ObjectShortName">S_addr[5:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_sine_out_lut">
+ <obj_property name="ElementShortName">S_sine_out_lut[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_sine_out_lut[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_square">
+ <obj_property name="ElementShortName">S_square[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_square[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_triangle_out_lut">
+ <obj_property name="ElementShortName">S_triangle_out_lut[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_triangle_out_lut[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_saw_tooth_out_lut">
+ <obj_property name="ElementShortName">S_saw_tooth_out_lut[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_saw_tooth_out_lut[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_opposite_wave_sample">
+ <obj_property name="ElementShortName">S_opposite_wave_sample[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_opposite_wave_sample[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_wave_value">
+ <obj_property name="ElementShortName">S_wave_value[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_wave_value[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_wave_generator/uut/S_wave_sample">
+ <obj_property name="ElementShortName">S_wave_sample[7:0]</obj_property>
+ <obj_property name="ObjectShortName">S_wave_sample[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/uut/S_last">
+ <obj_property name="ElementShortName">S_last</obj_property>
+ <obj_property name="ObjectShortName">S_last</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/uut/S_middle">
+ <obj_property name="ElementShortName">S_middle</obj_property>
+ <obj_property name="ObjectShortName">S_middle</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/uut/S_u_d">
+ <obj_property name="ElementShortName">S_u_d</obj_property>
+ <obj_property name="ObjectShortName">S_u_d</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_wave_generator/uut/S_sign_sel">
+ <obj_property name="ElementShortName">S_sign_sel</obj_property>
+ <obj_property name="ObjectShortName">S_sign_sel</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/uut/G_N">
+ <obj_property name="ElementShortName">G_N</obj_property>
+ <obj_property name="ObjectShortName">G_N</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/uut/G_f0">
+ <obj_property name="ElementShortName">G_f0</obj_property>
+ <obj_property name="ObjectShortName">G_f0</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/uut/G_fs">
+ <obj_property name="ElementShortName">G_fs</obj_property>
+ <obj_property name="ObjectShortName">G_fs</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/uut/C_addr_half_w">
+ <obj_property name="ElementShortName">C_addr_half_w</obj_property>
+ <obj_property name="ObjectShortName">C_addr_half_w</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_wave_generator/uut/A_inst/state_reg">
+ <obj_property name="ElementShortName">state_reg</obj_property>
+ <obj_property name="ObjectShortName">state_reg</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/src/constraints/NexysVideo_Master.xdc b/src/constraints/NexysVideo_Master.xdc
new file mode 100644
index 0000000..d3bfcc7
--- /dev/null
+++ b/src/constraints/NexysVideo_Master.xdc
@@ -0,0 +1,365 @@
+### This file is a general .xdc for the Nexys Video Rev. A
+### To use it in a project:
+### - uncomment the lines corresponding to used pins
+### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+
+##Clock Signal
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
+
+
+##LEDs
+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports { led0 }];#[get_ports {LED[0]}]
+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports { led1 }];#[get_ports {LED[1]}]
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports { led2 }];#[get_ports {LED[2]}]
+set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports { led3 }];#[get_ports {LED[3]}]
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports { led4 }];#[get_ports {LED[4]}]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports { led5 }];#[get_ports {LED[5]}]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports { led6 }];#[get_ports {LED[6]}]
+set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports { led7 }];#[get_ports {LED[7]}]
+
+
+## Buttons
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports BTNC]
+set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports BTND]
+set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports BTNL]
+set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports BTNR]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports BTNU]
+set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports rstn]
+
+
+##Switches
+set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports { sw0 }];
+set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports { sw1 }]; #IO_25_16 Sch=sw[1]
+set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports { sw2 }]; #IO_L24P_T3_16 Sch=sw[2]
+set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports { sw3 }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports { sw4 }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports { sw5 }]; #IO_0_15 Sch=sw[5]
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { sw6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { sw7 }]; #IO_25_15 Sch=sw[7]
+
+
+##OLED Display
+#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { oled_dc }]; #IO_L7N_T1_D10_14 Sch=oled_dc
+#set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { oled_res }]; #IO_L4N_T0_D05_14 Sch=oled_res
+#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { oled_sclk }]; #IO_L7P_T1_D09_14 Sch=oled_sclk
+#set_property -dict { PACKAGE_PIN Y22 IOSTANDARD LVCMOS33 } [get_ports { oled_sdin }]; #IO_L9N_T1_DQS_D13_14 Sch=oled_sdin
+#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_0_14 Sch=oled_vbat
+#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { oled_vdd }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=oled_vdd
+
+
+##HDMI in
+#set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
+#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
+#set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
+#set_property -dict { PACKAGE_PIN AA3 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN Y3 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN Y2 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
+
+
+##HDMI out
+#set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
+#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
+#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
+#set_property -dict { PACKAGE_PIN Y1 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN W1 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN AA1 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
+
+
+##Display Port
+#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVDS } [get_ports { dp_tx_aux_n }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
+#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVDS } [get_ports { dp_tx_aux_n }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
+#set_property -dict { PACKAGE_PIN AA9 IOSTANDARD LVDS } [get_ports { dp_tx_aux_p }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
+#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVDS } [get_ports { dp_tx_aux_p }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
+#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { dp_tx_hpd }]; #IO_25_14 Sch=dp_tx_hpd
+
+
+##Audio Codec
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ac_adc_sdata]
+set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ac_bclk]
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ac_dac_sdata]
+set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ac_lrclk]
+set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ac_mclk]
+
+
+##Pmod header JA
+#set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports JA1]
+#set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { JA2 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { JA3 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { JA4 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { JA5 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { JA6 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
+
+
+##Pmod header JB
+#set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports LED17_B]
+#set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports LED17_G]
+#set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports LED16_R]
+#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L19P_T3_34 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L24N_T3_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L24P_T3_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L23N_T3_34 Sch=jb_n[4]
+#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L23P_T3_34 Sch=jb_p[4]
+
+
+##Pmod header JC
+#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18N_T2_34 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18P_T2_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22P_T3_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L17N_T2_34 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L17P_T2_34 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L20N_T3_34 Sch=jc_n[4]
+#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_34 Sch=jc_p[4]
+
+
+##XADC Header
+#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
+
+
+##UART
+#set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
+#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
+
+
+##Ethernet
+#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
+#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
+#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_25_34 Sch=eth_rst_b
+#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
+#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
+#set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN AB11 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
+#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
+#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
+
+
+##Fan PWM
+#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
+
+
+##DPTI/DSPI
+#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
+#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { prog_d[0]}]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
+#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
+#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[3]}]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
+#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
+#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
+#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
+#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
+#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
+#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
+#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
+#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { prog_siwun }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=prog_siwun
+#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { prog_spien }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=prog_spien
+#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { prog_txen }]; #IO_L13N_T2_MRCC_14 Sch=prog_txen
+#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { prog_wrn }]; #IO_L5N_T0_D07_14 Sch=prog_wrn
+
+
+##HID port
+set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { PS2Clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
+set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { PS2Data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data
+
+
+##QSPI
+#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports scl]
+set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports sda]
+
+##SD card
+#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cclk }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
+#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
+#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
+#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
+#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
+#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
+
+
+
+
+##Voltage Adjust
+#set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
+#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]
+#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
+
+
+##DDR3
+#set_property -dict {PACKAGE_PIN M2} [get_ports {ddr3_addr[0]}]
+#set_property -dict {PACKAGE_PIN M5} [get_ports {ddr3_addr[1]}]
+#set_property -dict {PACKAGE_PIN M3} [get_ports {ddr3_addr[2]}]
+#set_property -dict {PACKAGE_PIN M1} [get_ports {ddr3_addr[3]}]
+#set_property -dict {PACKAGE_PIN L6} [get_ports {ddr3_addr[4]}]
+#set_property -dict {PACKAGE_PIN P1} [get_ports {ddr3_addr[5]}]
+#set_property -dict {PACKAGE_PIN N3} [get_ports {ddr3_addr[6]}]
+#set_property -dict {PACKAGE_PIN N2} [get_ports {ddr3_addr[7]}]
+#set_property -dict {PACKAGE_PIN M6} [get_ports {ddr3_addr[8]}]
+#set_property -dict {PACKAGE_PIN R1} [get_ports {ddr3_addr[9]}]
+#set_property -dict {PACKAGE_PIN L5} [get_ports {ddr3_addr[10]}]
+#set_property -dict {PACKAGE_PIN N5} [get_ports {ddr3_addr[11]}]
+#set_property -dict {PACKAGE_PIN N4} [get_ports {ddr3_addr[12]}]
+#set_property -dict {PACKAGE_PIN P2} [get_ports {ddr3_addr[13]}]
+#set_property -dict {PACKAGE_PIN P6} [get_ports {ddr3_addr[14]}]
+#set_property -dict {PACKAGE_PIN L3} [get_ports {ddr3_ba[0]}]
+#set_property -dict {PACKAGE_PIN K6} [get_ports {ddr3_ba[1]}]
+#set_property -dict {PACKAGE_PIN L4} [get_ports {ddr3_ba[2]}]
+#set_property -dict {PACKAGE_PIN K3} [get_ports ddr3_cas_n]
+#set_property -dict {PACKAGE_PIN J6} [get_ports ddr3_cke]
+#set_property -dict {PACKAGE_PIN P4} [get_ports ddr3_ck_n]
+#set_property -dict {PACKAGE_PIN P5} [get_ports ddr3_ck_p]
+#set_property -dict {PACKAGE_PIN G3} [get_ports {ddr3_dm[0]}]
+#set_property -dict {PACKAGE_PIN F1} [get_ports {ddr3_dm[1]}]
+#set_property -dict {PACKAGE_PIN G2} [get_ports {ddr3_dq[0]}]
+#set_property -dict {PACKAGE_PIN H4} [get_ports {ddr3_dq[1]}]
+#set_property -dict {PACKAGE_PIN H5} [get_ports {ddr3_dq[2]}]
+#set_property -dict {PACKAGE_PIN J1} [get_ports {ddr3_dq[3]}]
+#set_property -dict {PACKAGE_PIN K1} [get_ports {ddr3_dq[4]}]
+#set_property -dict {PACKAGE_PIN H3} [get_ports {ddr3_dq[5]}]
+#set_property -dict {PACKAGE_PIN H2} [get_ports {ddr3_dq[6]}]
+#set_property -dict {PACKAGE_PIN J5} [get_ports {ddr3_dq[7]}]
+#set_property -dict {PACKAGE_PIN E3} [get_ports {ddr3_dq[8]}]
+#set_property -dict {PACKAGE_PIN B2} [get_ports {ddr3_dq[9]}]
+#set_property -dict {PACKAGE_PIN F3} [get_ports {ddr3_dq[10]}]
+#set_property -dict {PACKAGE_PIN D2} [get_ports {ddr3_dq[11]}]
+#set_property -dict {PACKAGE_PIN C2} [get_ports {ddr3_dq[12]}]
+#set_property -dict {PACKAGE_PIN A1} [get_ports {ddr3_dq[13]}]
+#set_property -dict {PACKAGE_PIN E2} [get_ports {ddr3_dq[14]}]
+#set_property -dict {PACKAGE_PIN B1} [get_ports {ddr3_dq[15]}]
+#set_property -dict {PACKAGE_PIN J2} [get_ports {ddr3_dqs_n[0]}]
+#set_property -dict {PACKAGE_PIN K2} [get_ports {ddr3_dqs_p[0]}]
+#set_property -dict {PACKAGE_PIN D1} [get_ports {ddr3_dqs_n[1]}]
+#set_property -dict {PACKAGE_PIN E1} [get_ports {ddr3_dqs_p[1]}]
+#set_property -dict {PACKAGE_PIN K4} [get_ports ddr3_odt]
+#set_property -dict {PACKAGE_PIN J4} [get_ports ddr3_ras_n]
+#set_property -dict { PACKAGE_PIN G1 } [get_ports { ddr3_reset_n }]; #IO_L5P_T0_AD13P_35 Sch=ddr3_reset
+#set_property -dict {PACKAGE_PIN L1} [get_ports ddr3_we_n]
+
+
+##FMC
+#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
+#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk1_m2c_n }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
+#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk1_m2c_p }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
+#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la01_cc_n }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
+#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la01_cc_p }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
+#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN K22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la17_cc_n }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
+#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la17_cc_p }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
+#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la18_cc_n }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
+#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la18_cc_p }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
+#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
+
+#set_property -dict { PACKAGE_PIN D15 } [get_ports { vrefa_m2c }]; #IO_L6N_T0_VREF_16 Sch=vrefa_m2c
+#set_property -dict { PACKAGE_PIN K14 } [get_ports { vrefa_m2c }]; #IO_L19N_T3_A21_VREF_15 Sch=vrefa_m2c
+#set_property -dict { PACKAGE_PIN H18 } [get_ports { vrefa_m2c }]; #IO_L6N_T0_VREF_15 Sch=vrefa_m2c
+#set_property -dict { PACKAGE_PIN C20 } [get_ports { vrefa_m2c }]; #IO_L19N_T3_VREF_16 Sch=vrefa_m2c
+
+#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { prsnt_m2c }]; #IO_L22N_T3_A04_D20_14 Sch=prsnt_m2c
+
+
+##???????????
+##set_property PACKAGE_PIN D16 [get_ports {netic20_d16}]; #IO_L5N_T0_16
+##set_property PACKAGE_PIN D20 [get_ports {netic20_d20}]; #IO_L19P_T3_16
+##set_property PACKAGE_PIN E16 [get_ports {netic20_e16}]; #IO_L5P_T0_16
+##set_property PACKAGE_PIN F4 [get_ports {netic20_f4}]; #IO_0_35
+##set_property PACKAGE_PIN T3 [get_ports {netic20_t3}]; #IO_0_34
+##set_property PACKAGE_PIN Y17 [get_ports {netic20_y17}]; #IO_0_13
+
+#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { pic_ss_b }]; #IO_L3N_T0_DQS_34 Sch=pic_ss_b
diff --git a/src/hdl/ADSR_module.vhd b/src/hdl/ADSR_module.vhd
new file mode 100644
index 0000000..ffa5e69
--- /dev/null
+++ b/src/hdl/ADSR_module.vhd
@@ -0,0 +1,97 @@
+-- Attack (0-100%) - Decay (100-70%) -- Sustain (70%) -- Release (70-0%) (ADSR) module
+-- made up of
+-- a finite-state machine to control the ADSR sequence
+-- a time counter to measure time
+-- a gain that varies linearily and will be multiplied by the tone
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+entity ADSR_module is
+ generic (
+ N: natural := 8; -- number of bits in the output signal
+ N_t: natural := 16; --number of bits to count the time
+ A_t: real := 20.0; -- length of the attack in ms
+ D_t: real := 5.0; -- length of the decay in ms
+ R_t: real := 700.0; -- length of the release in ms
+ fs: real := 48000.0 -- sampling frequency
+ );
+ port (
+ clk: in std_logic;
+ rst: in std_logic;
+ key: in std_logic ; -- key input
+ gain: out std_logic_vector(N-1 downto 0) -- unsigned value
+ );
+end ADSR_module;
+
+architecture archi of ADSR_module is
+
+ -- constants for the time calculations
+ constant A_cycles: unsigned(N_t-1 downto 0) := to_unsigned(integer(A_t * fs / 1000.0), N_t);
+ constant D_cycles: unsigned(N_t-1 downto 0) := to_unsigned(integer(D_t * fs / 1000.0), N_t);
+ constant R_cycles: unsigned(N_t-1 downto 0) := to_unsigned(integer(R_t * fs / 1000.0), N_t);
+
+ constant A_coeff : unsigned(N_t-1 downto 0) := to_unsigned(integer(real(2**N-1)/(A_t * fs / 1000.0)*real(2**N_t-1)), N_t);
+ constant D_coeff : unsigned(N_t-1 downto 0) := to_unsigned(integer(0.3*real(2**N-1)/(D_t * fs / 1000.0)*real(2**N_t-1)), N_t);
+ constant R_coeff : unsigned(N_t-1 downto 0) := to_unsigned(integer(real(2**N-1)/(R_t * fs / 1000.0)*real(2**N_t-1)), N_t);
+
+-- states of the FSM
+-- key_off, attack, decay, sustain, release
+type state_type is (key_off, attack, decay, sustain, release_st );
+signal state: state_type := key_off;
+signal counter: unsigned(N_t-1 downto 0) := (others =>'0'); -- time counter
+signal gain_u : signed(2*N_t downto 0) := (others =>'0');
+
+begin
+
+ -- When the key is pressed, the cycles begins
+ process(clk, rst)
+ -- counter for the time
+ begin
+ if rst = '1' then
+ state <= key_off;
+ gain_u <= (others => '0');
+ counter <= (others =>'0');
+ elsif rising_edge(clk) then
+ case state is
+ when key_off =>
+ if key = '1' then
+ state <= attack;
+ counter <= (others =>'0');
+ end if;
+ when attack =>
+ if counter < A_cycles then
+ gain_u <= signed('0'&(counter*A_coeff));
+ counter <= counter + 1;
+ else
+ state <= decay;
+ counter <= (others =>'0');
+ end if;
+ when decay =>
+ if counter < D_cycles then
+ gain_U <= signed('0'&(A_cycles*A_coeff)) - signed('0'&(counter * D_coeff));
+ counter <= counter + 1;
+ else
+ state <= sustain;
+ end if;
+ when sustain =>
+ if key = '0' then
+ state <= release_st;
+ counter <= (others =>'0');
+ end if;
+ when release_st =>
+ if counter < R_cycles then
+ gain_u <= signed('0'&(A_cycles*A_coeff)) - signed('0'&(D_cycles * D_coeff)) - signed('0'&(R_cycles*counter));
+ counter <= counter + 1;
+ else
+ state <= key_off;
+ gain_u <= (others => '0');
+ end if;
+ end case;
+ end if;
+ end process;
+
+ gain <= std_logic_vector(gain_u(N_t+N-1 downto N_t)) when gain_u>0 else (others => '0');
+end archi ;
diff --git a/src/hdl/PS2Receiver.v b/src/hdl/PS2Receiver.v
new file mode 100644
index 0000000..11eb429
--- /dev/null
+++ b/src/hdl/PS2Receiver.v
@@ -0,0 +1,84 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Digilent Inc.
+// Engineer: Thomas Kappenman
+//
+// Create Date: 03/03/2015 09:33:36 PM
+// Design Name:
+// Module Name: PS2Receiver
+// Project Name: Nexys4DDR Keyboard Demo
+// Target Devices: Nexys4DDR
+// Tool Versions:
+// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module PS2Receiver(
+ input clk,
+ input kclk,
+ input kdata,
+ output reg [15:0] keycode=0,
+ output reg oflag
+ );
+
+ wire kclkf, kdataf;
+ reg [7:0]datacur=0;
+ reg [7:0]dataprev=0;
+ reg [3:0]cnt=0;
+ reg flag=0;
+
+debouncer #(
+ .COUNT_MAX(19),
+ .COUNT_WIDTH(5)
+) db_clk(
+ .clk(clk),
+ .I(kclk),
+ .O(kclkf)
+);
+debouncer #(
+ .COUNT_MAX(19),
+ .COUNT_WIDTH(5)
+) db_data(
+ .clk(clk),
+ .I(kdata),
+ .O(kdataf)
+);
+
+always@(negedge(kclkf))begin
+ case(cnt)
+ 0:;//Start bit
+ 1:datacur[0]<=kdataf;
+ 2:datacur[1]<=kdataf;
+ 3:datacur[2]<=kdataf;
+ 4:datacur[3]<=kdataf;
+ 5:datacur[4]<=kdataf;
+ 6:datacur[5]<=kdataf;
+ 7:datacur[6]<=kdataf;
+ 8:datacur[7]<=kdataf;
+ 9:flag<=1'b1;
+ 10:flag<=1'b0;
+
+ endcase
+ if(cnt<=9) cnt<=cnt+1;
+ else if(cnt==10) cnt<=0;
+end
+
+reg pflag;
+always@(posedge clk) begin
+ if (flag == 1'b1 && pflag == 1'b0) begin
+ keycode <= {dataprev, datacur};
+ oflag <= 1'b1;
+ dataprev <= datacur;
+ end else
+ oflag <= 'b0;
+ pflag <= flag;
+end
+
+endmodule
diff --git a/src/hdl/TWICtl.vhd b/src/hdl/TWICtl.vhd
new file mode 100644
index 0000000..e0dad08
--- /dev/null
+++ b/src/hdl/TWICtl.vhd
@@ -0,0 +1,571 @@
+----------------------------------------------------------------------------------
+-- Company: Digilent Ro
+-- Engineer: Elod Gyorgy
+--
+-- Create Date: 14:55:31 04/07/2011
+-- Design Name:
+-- Module Name: TWIUtils - Package
+-- Project Name: TWI Master Controller Reference Design
+-- Target Devices:
+-- Tool versions:
+-- Description: This package provides enumeration types for TWI (Two-Wire
+-- Interface) bus status and error conditions.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+package TWIUtils is
+ type busState_type is (busUnknown, busBusy, busFree);
+ type error_type is (errArb, errNAck);
+end TWIUtils;
+
+package body TWIUtils is
+end TWIUtils;
+
+----------------------------------------------------------------------------------
+-- Company: Digilent Ro
+-- Engineer: Elod Gyorgy
+--
+-- Create Date: 14:55:31 04/07/2011
+-- Design Name:
+-- Module Name: TWICtl - Behavioral
+-- Project Name: TWI Master Controller Reference Design
+-- Target Devices:
+-- Tool versions:
+-- Description: TWICtl is a reusabled Master Controller implementation of the
+-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
+-- FAST mode should also be theoretically possible, although it has not been
+-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
+-- buses. Slave-wait is also supported.
+--
+--
+-- Dependencies: digilent.TWIUtils package - TWICtl.vhd
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.math_real.all;
+
+library digilent;
+--use digilent.TWIUtils.ALL;
+
+entity TWICtl is
+----------------------------------------------------------------------------------
+-- Title : Mode of operation
+-- Description: The controller can be instructed to initiate/continue/stop a
+-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
+-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
+-- signals are synchronous to CLK and input signals must also be synchronous to
+-- CLK. Signals are active-high.
+-- Fast-track instructions (single byte transfer):
+-- -put the TWI address on A_I
+-- -if data is written put it on D_I
+-- -assert STB_I
+-- -when DONE_O pulse arrives, read data is present on D_O, if any
+-- -repeat, or deassert STB_I
+-- Detailed data transfer flow:
+-- -when DONE_O is low, the controller is ready to accept commands
+-- -data transfer can be initiated by putting a TWI slave address on the A_I
+-- bus and providing a strobe (STB_I)
+-- -the direction of data transfer (read/write) is determined by the LSB of the
+-- address (0-write, 1-read)
+-- -in case of a 'write' the data byte should also be present on the D_I bus
+-- prior to the arrival of the strobe (STB_I)
+-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
+-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
+-- together with DONE_I high indicates success
+-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
+-- strobe can be sent; this is useful, when multiple bytes are sent/received
+-- in a single transfer packet; for ex. for write transfers, a new byte can
+-- be put on the D_I and STB_I provided;
+-- -if no new strobe is provided, the transfer will end
+-- -if a new strobe is provided, but the address changed, the current transfer
+-- will end and a new will begin
+-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
+-- a strobe, the data byte will be written/read in a new packet; the advantage
+-- of this is relevant only in multi-master buses: rather than waiting for the
+-- current transfer to end and the bus to be released, a new transfer can be
+-- initiated without giving up the control over the bus
+----------------------------------------------------------------------------------
+ generic (CLOCKFREQ : natural := 50); -- input CLK frequency in MHz
+ port (
+ MSG_I : in STD_LOGIC; --new message
+ STB_I : in STD_LOGIC; --strobe
+ A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
+ D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
+ D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
+ DONE_O : out STD_LOGIC; --done status signal
+ ERR_O : out STD_LOGIC; --error status
+ CLK : in std_logic;
+ SRST : in std_logic;
+----------------------------------------------------------------------------------
+-- TWI bus signals
+----------------------------------------------------------------------------------
+ SDA : inout std_logic; --TWI SDA
+ SCL : inout std_logic --TWI SCL
+ );
+end TWICtl;
+
+architecture Behavioral of TWICtl is
+ attribute fsm_encoding: string;
+
+ constant FSCL : natural := 400_000; --in Hz SCL clock frequency
+ constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
+ constant TSCL_CYCLES : natural :=
+ natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
+ constant TIMEOUT_CYCLES : natural :=
+ natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
+
+ type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
+ stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
+ type busState_type is (busUnknown, busFree, busBusy);
+ type error_type is (errNAck, errArb);
+ signal state, nstate : state_type;
+ attribute fsm_encoding of state: signal is "gray";
+
+ signal dSda, ddSda, dScl, ddScl : std_logic;
+ signal fStart, fStop : std_logic;
+ signal busState : busState_type := busUnknown;
+ signal errTypeR, errType : error_type;
+ signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
+ signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
+ signal slaveWait, arbLost : std_logic;
+ signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
+ signal rSda, rScl : std_logic := '1';
+ signal subState : std_logic_vector(1 downto 0) := "00";
+ signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
+ signal bitCount : natural range 0 to 7 := 7;
+ signal int_Rst : std_logic := '0';
+begin
+
+----------------------------------------------------------------------------------
+--Bus State detection
+----------------------------------------------------------------------------------
+SYNC_FFS: process(CLK)
+ begin
+ if Rising_Edge(CLK) then
+ dSda <= SDA;
+ ddSda <= dSda;
+ dScl <= SCL;
+ end if;
+ end process;
+
+ fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
+ fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
+
+TWISTATE: process(CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (int_Rst = '1') then
+ busState <= busUnknown;
+ elsif (fStart = '1') then --If START condition detected, bus is busy
+ busState <= busBusy;
+ elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
+ busState <= busFree;
+ end if;
+ end if;
+ end process;
+
+TBUF_CNT: process(CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
+ busFreeCnt <= TSCL_CYCLES;
+ elsif (dSCL = '1' and dSDA = '1') then
+ busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+--Slave devices can insert wait states by keeping SCL low
+----------------------------------------------------------------------------------
+ slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
+ '0';
+----------------------------------------------------------------------------------
+--If the SDA line does not correspond to the transmitted data while the SCL line
+--is at the HIGH level the master lost an arbitration to another master.
+----------------------------------------------------------------------------------
+ arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
+ '0';
+
+----------------------------------------------------------------------------------
+-- Internal reset signal
+----------------------------------------------------------------------------------
+ RST_PROC: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (state = stIdle and SRST = '0') then
+ int_Rst <= '0';
+ elsif (SRST = '1') then
+ int_Rst <= '1';
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+-- SCL period counter
+----------------------------------------------------------------------------------
+SCL_CNT: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (sclCnt = 0 or state = stIdle) then
+ sclCnt <= TSCL_CYCLES/4;
+ elsif (slaveWait = '0') then -- clock synchronization with other masters
+ sclCnt <= sclCnt - 1;
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+-- SCL period counter
+----------------------------------------------------------------------------------
+TIMEOUT_CNT: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (timeOutCnt = 0 or slaveWait = '0') then
+ timeOutCnt <= TIMEOUT_CYCLES;
+ elsif (slaveWait = '1') then -- count timeout on wait period inserted by slave
+ timeOutCnt <= timeOutCnt - 1;
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+-- Title: Data byte shift register
+-- Description: Stores the byte to be written or the byte read depending on the
+-- transfer direction.
+----------------------------------------------------------------------------------
+DATABYTE_SHREG: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
+ dataByte <= loadByte; --latch address/data
+ bitCount <= 7;
+ --set flag so that we now what is the byte we are sending
+ if (latchData = '1') then
+ addrNData <= '0';
+ else
+ addrNData <= '1';
+ end if;
+ elsif (shiftBit = '1' and sclCnt = 0) then
+ dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
+ bitCount <= bitCount - 1;
+ end if;
+ end if;
+ end process;
+
+ loadByte <= A_I when latchAddr = '1' else
+ D_I;
+ dataBitOut <= dataByte(dataByte'high);
+
+ D_O <= dataByte;
+
+----------------------------------------------------------------------------------
+-- Title: Current address register
+-- Description: Stores the TWI slave address
+----------------------------------------------------------------------------------
+CURRADDR_REG: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (latchAddr = '1') then
+ currAddr <= A_I; --latch address/data
+ end if;
+ end if;
+ end process;
+
+ rwBit <= currAddr(0);
+----------------------------------------------------------------------------------
+-- Title: Substate counter
+-- Description: Divides each state into 4, to respect the setup and hold times of
+-- the TWI bus.
+----------------------------------------------------------------------------------
+SUBSTATE_CNT: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (state = stIdle) then
+ subState <= "00";
+ elsif (sclCnt = 0) then
+ subState <= subState + 1;
+ end if;
+ end if;
+ end process;
+
+SYNC_PROC: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ state <= nstate;
+
+ rSda <= iSda;
+ rScl <= iScl;
+ DONE_O <= iDone;
+ ERR_O <= iErr;
+ errTypeR <= errType;
+ end if;
+ end process;
+
+OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
+ sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
+ begin
+ iSda <= rSda; --no change by default
+ iScl <= rScl;
+ iDone <= '0';
+ iErr <= '0';
+ errType <= errTypeR; --keep error type
+ shiftBit <= '0';
+ latchAddr <= '0';
+ latchData <= '0';
+
+ if (state = stStart) then
+ case (subState) is
+ when "00" =>
+ iSda <= '1';
+ --keep SCL
+ when "01" =>
+ iSda <= '1';
+ iScl <= '1';
+ when "10" =>
+ iSda <= '0';
+ iScl <= '1';
+ when "11" =>
+ iSda <= '0';
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stStop or state = stStopError) then
+ case (subState) is
+ when "00" =>
+ iSda <= '0';
+ --keep SCL
+ when "01" =>
+ iSda <= '0';
+ iScl <= '1';
+ when "10" =>
+ iSda <= '1';
+ iScl <= '1';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stRead or state = stSAck) then
+ case (subState) is
+ when "00" =>
+ iSda <= '1'; --this will be 'Z' on SDA
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stWrite) then
+ case (subState) is
+ when "00" =>
+ iSda <= dataBitOut;
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stMAck) then
+ case (subState) is
+ when "00" =>
+ iSda <= '0'; -- acknowledge by writing 0
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stMNAckStop or state = stMNAckStart) then
+ case (subState) is
+ when "00" =>
+ iSda <= '1'; -- not acknowledge by writing 1
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stSAck and sclCnt = 0 and subState = "01") then
+ if (dSda = '1') then
+ iDone <= '1';
+ iErr <= '1'; --not acknowledged
+ errType <= errNAck;
+ elsif (addrNData = '0') then
+ --we are done only when the data is sent too after the address
+ iDone <= '1';
+ end if;
+ end if;
+
+ if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
+ iDone <= '1'; --read done
+ end if;
+
+ if (state = stWrite and arbLost = '1') then
+ iDone <= '1'; --write done
+ iErr <= '1'; --we lost the arbitration
+ errType <= errArb;
+ end if;
+
+ if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
+ ((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
+ shiftBit <= '1';
+ end if;
+
+ if (state = stStart) then
+ latchAddr <= '1';
+ end if;
+
+ if (state = stSAck and subState = "11") then --get the data byte for the next write
+ latchData <= '1';
+ end if;
+
+ end process;
+
+NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I,
+SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
+ begin
+
+ nstate <= state; --default is to stay in current state
+
+ case (state) is
+ when stIdle =>
+ if (STB_I = '1' and busState = busFree and SRST = '0') then
+ nstate <= stStart;
+ end if;
+
+ when stStart =>
+ if (subState = "11" and sclCnt = 0) then
+ nstate <= stWrite;
+ end if;
+
+ when stWrite =>
+ if (arbLost = '1') then
+ nstate <= stIdle;
+ elsif (subState = "11" and sclCnt = 0 and bitCount = 0) then
+ nstate <= stSAck;
+ end if;
+
+ when stSAck =>
+ if (subState = "11" and sclCnt = 0) then
+ if (int_Rst = '1' or dataByte(0) = '1') then
+ nstate <= stStop;
+ else
+ if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
+ if (rwBit = '1') then
+ nstate <= stRead;
+ else
+ nstate <= stWrite;
+ end if;
+ elsif (STB_I = '1') then
+ if (MSG_I = '1' or currAddr /= A_I) then
+ nstate <= stStart;
+ else
+ if (rwBit = '1') then
+ nstate <= stRead;
+ else
+ nstate <= stWrite;
+ end if;
+ end if;
+ else
+ nstate <= stStop;
+ end if;
+ end if;
+ end if;
+
+ when stStop =>
+ if (subState = "10" and sclCnt = 0) then
+ nstate <= stIdle;
+ end if;
+
+ when stRead =>
+ if (subState = "11" and sclCnt = 0 and bitCount = 7) then --bitCount will underflow
+ if (int_Rst = '0' and STB_I = '1') then
+ if (MSG_I = '1' or currAddr /= A_I) then
+ nstate <= stMNAckStart;
+ else
+ nstate <= stMAck;
+ end if;
+ else
+ nstate <= stMNAckStop;
+ end if;
+ end if;
+
+ when stMAck =>
+ if (subState = "11" and sclCnt = 0) then
+ nstate <= stRead;
+ end if;
+
+ when stMNAckStart =>
+ if (arbLost = '1') then
+ nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
+ elsif (subState = "11" and sclCnt = 0) then
+ nstate <= stStart;
+ end if;
+
+ when stMNAckStop =>
+ if (arbLost = '1') then
+ nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
+ elsif (subState = "11" and sclCnt = 0) then
+ nstate <= stStop;
+ end if;
+
+ when others =>
+ nstate <= stIdle;
+ end case;
+ end process;
+
+----------------------------------------------------------------------------------
+-- Open-drain outputs for bi-directional SDA and SCL
+----------------------------------------------------------------------------------
+ SDA <= 'Z' when rSDA = '1' else
+ '0';
+ SCL <= 'Z' when rSCL = '1' else
+ '0';
+
+end Behavioral;
\ No newline at end of file
diff --git a/src/hdl/audioProc.v b/src/hdl/audioProc.v
new file mode 100644
index 0000000..da828f3
--- /dev/null
+++ b/src/hdl/audioProc.v
@@ -0,0 +1,285 @@
+// -*- Mode: Verilog -*-
+// Filename : audioProc.v
+// Description : Audio processing project for IMTA A1S2 Labs in digital electronics, based on looper project by Digilent Inc.
+// Author : Matthieu Arzel
+// Created On : Fri Feb 8 11:16:35 2019
+// Last Modified By: Matthieu Arzel
+// Last Modified On: Fri Feb 8 11:16:35 2019
+// Update Count : 0
+// Status : Unknown, Use with caution!
+
+`timescale 1ns / 1ps
+
+module audioProc(
+
+
+ input BTNL,
+ input BTNR,
+ input BTND,
+ input BTNC,
+ input BTNU,
+ // input JA1,
+ // input JA2,
+ // input JA3,
+ // input JA4,
+
+ input CLK100MHZ,
+ input rstn,
+ input sw0,
+ input sw1,
+ input sw2,
+ input sw3,
+ input sw4,
+ input sw5,
+ input sw6,
+ input sw7,
+
+
+ input PS2Data,
+ input PS2Clk,
+
+ output led0,
+ output led1,
+ output led2,
+ output led3,
+ output led4,
+ output led5,
+ output led6,
+ output led7,
+
+ inout scl,
+ inout sda,
+
+ output ac_mclk,
+ input ac_adc_sdata,
+ output ac_dac_sdata,
+ output ac_bclk,
+ output ac_lrclk
+
+ );
+
+ wire rst;
+ assign rst = ~rstn;
+ wire clk50;
+ parameter tenhz = 10000000;
+
+
+
+ wire [4:0] buttons_i;
+ assign buttons_i = {BTNU, BTNR, BTNC, BTND, BTNL};
+
+ reg [21:0] max_block=0;
+
+ wire set_max;
+ wire reset_max;
+
+
+ wire [4:0] buttons_db;//Debounced buttons
+
+ wire data_flag;
+ reg [23:0] sound_dataL;
+ reg [23:0] sound_dataR;
+ wire data_ready;
+
+ wire mix_data;
+ wire [21:0] block48KHz;
+
+ wire clk_out_100MHZ;
+ wire clk_out_200MHZ;
+
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+ //// clk_wiz instantiation and wiring
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+ clk_wiz_0 clk_1
+ (
+ // Clock in ports
+ .clk_in1(CLK100MHZ),
+ // Clock out ports
+ .clk_out1(clk_out_100MHZ),
+ .clk_out2(clk_out_200MHZ),
+ .clk_out3(ac_mclk),
+ .clk_out4(clk50),
+ // Status and control signals
+ .locked()
+ );
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+ //// Audio Initialization via TWI
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ audio_init initialize_audio
+ (
+ .clk(clk50),
+ .rst(rst),
+ .sda(sda),
+ .scl(scl)
+ );
+
+
+ wire [23:0] mixL;
+ wire [23:0] mixR;
+
+
+ debounce dbuttons(
+ .clock(clk_out_100MHZ),
+ .reset(rst),
+ .button(buttons_i),
+ .out(buttons_db)
+ );
+
+ /////////////
+ /// USB keyboard
+ /////////////////
+
+
+ reg [15:0] keycodev=0;
+ wire [15:0] keycode;
+ reg [ 2:0] bcount=0;
+ wire flag;
+ reg cn=0;
+ wire key_A;
+ reg start;
+
+
+ PS2Receiver uut (
+ .clk(clk50),
+ .kclk(PS2Clk),
+ .kdata(PS2Data),
+ .keycode(keycode),
+ .oflag(flag)
+ );
+
+
+ always@(keycode, keycodev)
+ if (keycode[7:0] == 8'hf0) begin
+ cn <= 1'b0;
+ bcount <= 3'd0;
+ end else if (keycode[15:8] == 8'hf0) begin
+ cn <= keycode != keycodev;
+ bcount <= 3'd5;
+ end else begin
+ cn <= keycode[7:0] != keycodev[7:0] || keycodev[15:8] == 8'hf0;
+ bcount <= 3'd2;
+ end
+
+ always@(posedge clk_out_100MHZ)
+ if (flag == 1'b1 && cn == 1'b1) begin
+ start <= 1'b1;
+ keycodev <= keycode;
+ end else
+ start <= 1'b0;
+
+
+ //assign key_A at 1 when keycodev is equal to 1C (key 'A')
+ // assign key_A = ((keycodev[7:0] == 8'h1C) && (keycodev[15:8] != 8'hf0)) ? 1'b1 : 1'b0;
+ // always@(keycodev)
+
+ // key_A
+
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Audio input and output
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ wire [23:0] in_audioL;
+ wire [23:0] in_audioR;
+ wire [23:0] out_audioL;
+ wire [23:0] out_audioR;
+
+ i2s_ctl audio_inout(
+ .CLK_I(clk_out_100MHZ), //Sys clk
+ .RST_I(rst), //Sys rst
+ .EN_TX_I(1), // Transmit Enable (push sound data into chip)
+ .EN_RX_I(1), //Receive enable (pull sound data out of chip)
+ .FS_I(4'b0101), //Sampling rate selector
+ .MM_I(0), //Audio controller Master mode select
+ .D_L_I(mixL), //Left channel data input from mix (mixed audio output)
+ .D_R_I(mixR), //Right channel data input from mix
+ .D_L_O(in_audioL), // Left channel data (input from mic input)
+ .D_R_O(in_audioR), // Right channel data (input from mic input)
+ .BCLK_O(ac_bclk), // serial CLK
+ .LRCLK_O(ac_lrclk), // channel CLK
+ .SDATA_O(ac_dac_sdata), // Output serial data
+ .SDATA_I(ac_adc_sdata) // Input serial data
+ );
+
+ reg lrclkD1=0;
+ reg lrclkD2=0;
+
+ always@(posedge(clk_out_100MHZ))begin
+ lrclkD1<=ac_lrclk;
+ lrclkD2<=lrclkD1;
+ end
+
+ reg pulse48kHz;
+ wire lrclkrise;
+ assign lrclkrise = lrclkD1 & ~lrclkD2;
+ reg[3:0] lrclkcnt=0;
+
+ always@(posedge(clk_out_100MHZ))begin
+ if (lrclkcnt==15)begin
+ pulse48kHz<=1;
+ lrclkcnt<=0;
+ end
+ else
+ pulse48kHz<=0;
+ if (lrclkrise)lrclkcnt<=lrclkcnt+1;
+ end
+ //////////////////////////////
+ // Synthe
+ // Marz
+ /////////////////////////////
+ wire [23:0] inputLeftSample, inputRightSample,outputLeftSample,outputRightSample;
+ wire [4:0] configSw;
+ wire [1:0] waveSw;
+
+ assign inputLeftSample = in_audioL;
+ assign inputRightSample = in_audioR;
+ assign waveSw[0]=sw0;
+ assign waveSw[1]=sw1;
+ assign configSw[0]=sw2;
+ assign configSw[1]=sw3;
+ assign configSw[2]=sw4;
+ assign configSw[3]=sw5;
+ assign configSw[4]=sw6;
+
+ assign led0=sw0;
+ assign led1=sw1;
+ assign led2=sw2;
+ assign led3=sw3;
+ assign led4=sw4;
+ assign led5=sw5;
+ assign led6=sw6;
+ assign led7=sw7;
+
+
+ synthesizer synthe
+ (
+ pulse48kHz, // : in std_logic;
+ rst,// : in std_logic;
+ waveSw[1:0],
+ configSw[3:0],
+ keycodev, //buttons_db[0],
+ outputLeftSample
+ // : in std_logic; -- signal de validation de din a la frequence des echantillons audio
+ );
+
+
+assign mixL = buttons_db[2] ? in_audioL : outputLeftSample;
+ assign mixR = buttons_db[2] ? in_audioR : outputLeftSample;
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+ //// Data in latch
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ //Latch audio data input when data_flag goes high
+ always@(posedge(clk_out_100MHZ))begin
+ if (data_flag==1)begin
+ sound_dataL<=in_audioL;
+ sound_dataR<=in_audioR;
+ end
+ end
+
+
+endmodule
diff --git a/src/hdl/audio_init.v b/src/hdl/audio_init.v
new file mode 100644
index 0000000..0f33184
--- /dev/null
+++ b/src/hdl/audio_init.v
@@ -0,0 +1,246 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 07/08/2015 06:07:53 PM
+// Design Name:
+// Module Name: audio_init
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+
+module audio_init(
+ input clk,
+ input rst,
+ inout sda,
+ inout scl
+ );
+ parameter stRegAddr1 = 4'b0000;
+ parameter stRegAddr2 = 4'b0001;
+ parameter stData1 = 4'b0010;
+ parameter stData2 = 4'b0011;
+ parameter stError = 4'b0100;
+ parameter stDone = 4'b0101;
+ parameter stIdle = 4'b0110;
+ parameter stDelay = 4'b0111;
+ parameter stPLLsecond = 4'b1111;
+
+ parameter INIT_VECTORS = 35;
+ parameter IRD = 1'b1;//init read
+ parameter IWR = 1'b0;//init write
+ parameter delay = 1000*24;
+
+ reg [3:0] state=stIdle;//State machine
+ reg [32:0] initWord;
+ reg initFbWe;
+ reg initEn;
+ reg [6:0]initA=0;
+ always @(posedge(clk))begin
+ case (initA)
+ 0: initWord <= {IWR,31'h40150100};
+ 1: initWord <= {IWR,31'h40160000};
+ 2: initWord <= {IWR,31'h40170000};
+ 3: initWord <= {IWR,31'h40F80000};
+ 4: initWord <= {IWR,31'h40191300};
+ 5: initWord <= {IWR,31'h402A0300};
+ 6: initWord <= {IWR,31'h40290300};
+ 7: initWord <= {IWR,31'h40F20100};
+ 8: initWord <= {IWR,31'h40F97F00};
+ 9: initWord <= {IWR,31'h40FA0300};
+
+ 10: initWord <= {IWR,31'h40200300};
+ 11: initWord <= {IWR,31'h40220100};
+ 12: initWord <= {IWR,31'h40210900};
+ 13: initWord <= {IWR,31'h4025E600};
+ 14: initWord <= {IWR,31'h4026E600};
+ 15: initWord <= {IWR,31'h40270300};
+ 16: initWord <= {IWR,31'h40100100};
+ 17: initWord <= {IWR,31'h40280000};
+ 18: initWord <= {IWR,31'h4023E600};
+ 19: initWord <= {IWR,31'h4024E600};
+
+ 20: initWord <= {IWR,31'h400A0100};
+ 21: initWord <= {IWR,31'h400B0500};
+ 22: initWord <= {IWR,31'h400C0100};
+ 23: initWord <= {IWR,31'h400D0500};
+ 24: initWord <= {IWR,31'h400E0300};
+ 25: initWord <= {IWR,31'h400F0300};
+ 26: initWord <= {IWR,31'h401C2100};
+ 27: initWord <= {IWR,31'h401D0000};
+ 28: initWord <= {IWR,31'h401E4100};
+ 29: initWord <= {IWR,31'h401F0000};
+ 30: initWord <= {IWR,31'h40F30100};
+ 31: initWord <= {IWR,31'h40F40000};
+ 32: initWord <= {IWR,31'h40000F00};
+ 33: initWord <= {IWR,31'h4002007D};//This sends the address of the PLL reg and the first config bits
+ 34: initWord <= {IWR,31'h000C2101}; //These are the config bytes for the PLL reg
+ endcase
+ end
+ reg msg;//New message signal
+ reg stb;//Strobe signal
+ reg [7:0] data_i;//Data into TWI controller
+ wire [7:0] data_o;//Data out of TWI controller
+ wire done;
+ wire error;
+ wire errortype;
+ wire [7:0] twiAddr;//Address of device on TWI
+ reg [7:0] regData1;
+
+ reg delayEn=0;
+ integer delaycnt;
+
+
+ assign twiAddr[7:1] = 7'b0111011;
+
+ assign twiAddr[0] = 0;
+
+ TWICtl twi_controller(
+ .MSG_I(msg),
+ .STB_I(stb),
+ .A_I(twiAddr),
+ .D_I(data_i),
+ .D_O(data_o),
+ .DONE_O(done),
+ .ERR_O(error),
+ .CLK(clk),
+ .SRST(rst),
+ .SDA(sda),
+ .SCL(scl)
+ );
+
+
+
+always @(posedge(clk))begin
+ if (delayEn==1)
+ delaycnt<=delaycnt-1;
+ else
+ delaycnt<=delay;
+end
+
+
+always @(posedge(clk))begin
+ if (state == stData1 && done == 1 && error != 1)
+ regData1 <= data_o;
+end
+
+
+always @(posedge(clk))begin
+ if (rst==1)begin
+ state<= stIdle;
+ delayEn <= 0;
+ initA <=0;
+ end
+ else begin
+ data_i <= "--------";
+ stb <= 0;
+ msg <= 0;
+
+ initFbWe <= 0;
+ case (state)
+ stRegAddr1: begin// Sends x40
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else
+ state <= stRegAddr2;
+ end
+ data_i <= initWord[31:24];
+ stb <= 1;
+ msg <= 1;
+ end
+ stRegAddr2: begin //Sends register address x40(XX)
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else
+ state <= stData1;
+ end
+ data_i <= initWord[23:16];
+ stb <= 1;
+ end
+ stData1: begin
+ if (done == 1) begin
+ if (error == 1)
+ state <= stError;
+ else begin
+ if (initWord[7:0]!=0)//If there is another byte, send it
+ state <= stData2;
+ else begin//no more bytes to send
+ initEn <= 1;
+
+ if (initA == INIT_VECTORS-1)//Done with all instructions
+ state <= stDone;
+ else //Only 3 bytes to send
+ state <= stDelay;
+ end
+ end
+ end
+ if (initWord[32] == 1) msg <= 1;
+ data_i <= initWord[15:8];
+ stb <= 1;
+ end
+ stData2: begin
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else begin
+ initEn<=1;
+ if (initWord[32] == 1) initFbWe <= 1;
+ if (initWord[23:16]== 8'h02)begin//If its the PLL register
+ initA<=initA+1;//Move initWord to the remaining PLL config bits
+ state <= stPLLsecond;//And send them
+ end
+ else if (initA == INIT_VECTORS-1)
+ state <= stDone;
+ else
+ state <= stDelay;
+ end
+ end
+ data_i <= initWord[7:0];
+ stb <= 1;
+ end
+ stPLLsecond:begin
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else
+ state <= stRegAddr2;
+ end
+ data_i <= initWord[31:24];
+ stb <= 1;
+ end
+ stError: begin
+ state <= stRegAddr1;
+ end
+ stDone: begin
+ end
+ stIdle:begin
+ state <= stRegAddr1;
+ end
+ stDelay:begin
+ delayEn <= 1;
+ if (delaycnt==0)begin
+ delayEn<=0;
+ if (initEn)begin
+ initA<=initA+1;
+ initEn <= 0;
+ end
+ state<=stRegAddr1;
+ end
+ end
+ endcase
+ end
+end
+endmodule
diff --git a/src/hdl/debounce.v b/src/hdl/debounce.v
new file mode 100644
index 0000000..033a4fb
--- /dev/null
+++ b/src/hdl/debounce.v
@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 05/13/2015 09:14:14 PM
+// Design Name:
+// Module Name: debounce
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module debounce(
+ input clock,//100MHz clock
+ input reset,
+ input [4:0] button,//Buttons to debounce
+ output reg [4:0]out
+);
+
+reg [12:0] cnt0=0, cnt1=0, cnt2=0, cnt3=0, cnt4;
+reg [4:0] IV = 0;
+
+//parameter dbTime = 19;
+parameter dbTime = 4000;
+
+always @ (posedge(clock))begin
+ if(reset==1)begin
+ cnt0<=0;
+ cnt1<=0;
+ cnt2<=0;
+ cnt3<=0;
+ cnt4<=0;
+ out<=0;
+ end
+ else begin
+ if(button[0]==IV[0]) begin
+ if (cnt0==dbTime) begin
+ out[0]<=IV[0];
+ end
+ else begin
+ cnt0<=cnt0+1;
+ end
+ end
+ else begin
+ cnt0<=0;
+ IV[0]<=button[0];
+ end
+ if(button[1]==IV[1]) begin
+ if (cnt1==dbTime) begin
+ out[1]<=IV[1];
+ end
+ else begin
+ cnt1<=cnt1+1;
+ end
+ end
+ else begin
+ cnt1<=0;
+ IV[1]<=button[1];
+ end
+ if(button[2]==IV[2]) begin
+ if (cnt2==dbTime) begin
+ out[2]<=IV[2];
+ end
+ else begin
+ cnt2<=cnt2+1;
+ end
+ end
+ else begin
+ cnt2<=0;
+ IV[2]<=button[2];
+ end
+ if(button[3]==IV[3]) begin
+ if (cnt3==dbTime) begin
+ out[3]<=IV[3];
+ end
+ else begin
+ cnt3<=cnt3+1;
+ end
+ end
+ else begin
+ cnt3<=0;
+ IV[3]<=button[3];
+ end
+ if(button[4]==IV[4]) begin
+ if (cnt4==dbTime) begin
+ out[4]<=IV[4];
+ end
+ else begin
+ cnt4<=cnt4+1;
+ end
+ end
+ else begin
+ cnt4<=0;
+ IV[4]<=button[4];
+ end
+ end
+end
+endmodule
\ No newline at end of file
diff --git a/src/hdl/debouncer.v b/src/hdl/debouncer.v
new file mode 100644
index 0000000..7e2078c
--- /dev/null
+++ b/src/hdl/debouncer.v
@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 07/27/2016 02:04:22 PM
+// Design Name:
+// Module Name: debouncer
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module debouncer(
+ input clk,
+ input I,
+ output reg O
+ );
+ parameter COUNT_MAX=255, COUNT_WIDTH=8;
+ reg [COUNT_WIDTH-1:0] count;
+ reg Iv=0;
+ always@(posedge clk)
+ if (I == Iv) begin
+ if (count == COUNT_MAX)
+ O <= I;
+ else
+ count <= count + 1'b1;
+ end else begin
+ count <= 'b0;
+ Iv <= I;
+ end
+
+endmodule
diff --git a/src/hdl/i2s_ctl.vhd b/src/hdl/i2s_ctl.vhd
new file mode 100644
index 0000000..1b608ad
--- /dev/null
+++ b/src/hdl/i2s_ctl.vhd
@@ -0,0 +1,296 @@
+-------------------------------------------------------------------------------
+--
+-- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
+--
+-------------------------------------------------------------------------------
+-- FILE NAME : i2s_ctl.vhd
+-- MODULE NAME : I2S Control
+-- AUTHOR : Mihaita Nagy
+-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
+-------------------------------------------------------------------------------
+-- REVISION HISTORY
+-- VERSION DATE AUTHOR DESCRIPTION
+-- 1.0 2012-25-01 Mihaita Nagy Created
+-- 2.0 2012-02-04 Mihaita Nagy Remade the i2s_transmitter.vhd and
+-- i2s_receiver.vhd into one new module.
+-- 3.0 2014-12-02 HegbeliC Implemented edge detection for the
+-- master mode and the division rate
+-- for the different sampling rates
+-------------------------------------------------------------------------------
+-- KEYWORDS : I2S
+-------------------------------------------------------------------------------
+-- DESCRIPTION : This module implements the I2S transmitter and receiver
+-- interface, with a 32-bit Stereo data transmission. Parameter
+-- C_DATA_WIDTH sets the width of the data to be transmitted,
+-- with a maximum value of 32 bits. If a smaller width size is
+-- used (i.e. 24) than the remaining bits that needs to be
+-- transmitted to complete the 32-bit length, are automaticaly
+-- set to 0.
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+------------------------------------------------------------------------
+-- Module Declaration
+------------------------------------------------------------------------
+entity i2s_ctl is
+ generic (
+ -- Width of one Slot (24/20/18/16-bit wide)
+ C_DATA_WIDTH: integer := 24
+ );
+ port (
+ CLK_I : in std_logic; -- System clock (100 MHz)
+ RST_I : in std_logic; -- System reset
+ EN_TX_I : in std_logic; -- Transmit enable
+ EN_RX_I : in std_logic; -- Receive enable
+ FS_I : in std_logic_vector(3 downto 0); -- Sampling rate slector
+ MM_I : in std_logic; -- Audio controler Master Mode delcetor
+ D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
+ D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
+-- OE_L_O : out std_logic; -- Left channel data output enable pulse
+-- OE_R_O : out std_logic; -- Right channel data output enable pulse
+-- WE_L_O : out std_logic; -- Left channel data write enable pulse
+-- WE_R_O : out std_logic; -- Right channel data write enable pulse
+ D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
+ D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
+ BCLK_O : out std_logic; -- serial CLK
+ LRCLK_O : out std_logic; -- channel CLK
+ SDATA_O : out std_logic; -- Output serial data
+ SDATA_I : in std_logic -- Input serial data
+ );
+end i2s_ctl;
+
+architecture Behavioral of i2s_ctl is
+
+------------------------------------------------------------------------
+-- Signal Declarations
+------------------------------------------------------------------------
+-- Counter for the clock divider
+signal Cnt_Bclk : integer range 0 to 31;
+
+-- Counter for the L/R clock divider
+signal Cnt_Lrclk : integer range 0 to 31;
+
+-- Rising and Falling edge impulses of the serial clock
+signal BCLK_Fall, BCLK_Rise : std_logic;
+signal BCLK_Fall_int, BCLK_Rise_int : std_logic;
+--signal BCLK_Fall_shot, BCLK_Rise_shot : std_logic;
+
+-- Synchronisation signals for Rising and Falling edge
+signal Q1R, Q2R, Q3R : std_logic;
+signal Q1F, Q2F, Q3F : std_logic;
+
+-- Internal synchronous BCLK signal
+signal BCLK_int : std_logic;
+
+-- Internal synchronous LRCLK signal
+signal LRCLK_int : std_logic;
+signal LRCLK : std_logic;
+
+--
+signal Data_Out_int : std_logic_vector(31 downto 0);
+
+--
+signal Data_In_int : std_logic_vector(31 downto 0);
+
+--
+signal D_L_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
+
+--
+signal D_R_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
+
+--Internal synchronous OE signals
+signal OE_R_int, OE_L_int : std_logic;
+
+--Internal synchronous WE signals
+signal WE_R_int, WE_L_int : std_logic;
+
+-- Division rate for the BCLK and LRCLK
+signal DIV_RATE : natural := 4;
+
+------------------------------------------------------------------------
+-- Module Implementation
+------------------------------------------------------------------------
+
+begin
+
+------------------------------------------------------------------------
+-- Sampling frequency and data width decoder (DIV_RATE, C_DATA_WIDTH)
+------------------------------------------------------------------------
+
+ BIT_FS: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ case (FS_I) is
+ when x"0" => DIV_RATE <= 24;
+ when x"1" => DIV_RATE <= 16;
+ when x"2" => DIV_RATE <= 12;
+ when x"3" => DIV_RATE <= 8;
+ when x"4" => DIV_RATE <= 6;
+ when x"5" => DIV_RATE <= 4;
+ when x"6" => DIV_RATE <= 2;
+ when others => DIV_RATE <= 4;
+ end case;
+ end if;
+ end process;
+
+------------------------------------------------------------------------
+-- Serial clock generator (BCLK_O, BCLK_Fall, BCLK_Rise)
+------------------------------------------------------------------------
+ SER_CLK: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Cnt_Bclk <= 0;
+ BCLK_int <= '0';
+ elsif Cnt_Bclk = ((DIV_RATE/2)-1) then
+ Cnt_Bclk <= 0;
+ BCLK_int <= not BCLK_int;
+ else
+ Cnt_Bclk <= Cnt_Bclk + 1;
+ end if;
+ end if;
+ end process SER_CLK;
+
+ -- Rising and Falling edges when in Slave mode
+ BCLK_Fall_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '1' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
+ BCLK_Rise_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '0' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
+
+
+
+ -- Falling edge selection with respect to Master Mode bit
+ BCLK_Fall <= BCLK_Fall_int;
+
+ -- Risesing edge selection with respect to Master Mode bit
+ BCLK_Rise <= BCLK_Rise_int;
+
+ -- Serial clock output
+ BCLK_O <= BCLK_int when EN_RX_I = '1' or EN_TX_I = '1' else '1';
+
+------------------------------------------------------------------------
+-- Left/Right clock generator (LRCLK_O, LRCLK_Pls)
+------------------------------------------------------------------------
+ LRCLK_GEN: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Cnt_Lrclk <= 0;
+ LRCLK <= '0'; -- Left channel active by default
+ elsif BCLK_Fall = '1' then
+ if Cnt_Lrclk = 31 then -- half of frame (64 bits)
+ Cnt_Lrclk <= 0;
+ LRCLK <= not LRCLK;
+ else
+ Cnt_Lrclk <= Cnt_Lrclk + 1;
+ end if;
+ end if;
+ end if;
+ end process LRCLK_GEN;
+
+ -- L/R clock output
+ LRCLK_O <= LRCLK when EN_TX_I = '1' or EN_RX_I = '1' else '0';
+ LRCLK_int <= LRCLK;
+
+
+------------------------------------------------------------------------
+-- Load in paralled data, shift out serial data (SDATA_O)
+------------------------------------------------------------------------
+ SER_DATA_O: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Data_Out_int(31) <= '0';
+ Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; -- Left channel data by default
+ Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
+ elsif Cnt_Lrclk = 0 and BCLK_Rise = '1' then -- load par. data
+ if LRCLK_int = '1' then
+ Data_Out_int(31) <= '0';
+ Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_R_I;
+ Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
+ else
+ Data_Out_int(31) <= '0';
+ Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I;
+ Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
+ end if;
+ elsif BCLK_Fall = '1' then -- shift out ser. data
+ Data_Out_int <= Data_Out_int(30 downto 0) & '0';
+ end if;
+ end if;
+ end process SER_DATA_O;
+
+ -- Serial data output
+ SDATA_O <= Data_Out_int(31) when EN_TX_I = '1' else '0';
+
+------------------------------------------------------------------------
+-- Shift in serial data, load out parallel data (SDATA_I)
+------------------------------------------------------------------------
+ SER_DATA_I: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Data_In_int <= (others => '0');
+ D_L_O_int <= (others => '0');
+ D_R_O_int <= (others => '0');
+ elsif Cnt_Lrclk = 0 and BCLK_Fall = '1' then -- load par. data
+ if LRCLK_int = '1' then
+ D_L_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
+ Data_In_int <= (others => '0');
+ else
+ D_R_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
+ Data_In_int <= (others => '0');
+ end if;
+ elsif BCLK_Rise = '1' then -- shift in ser. data
+ Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
+ end if;
+ end if;
+ end process SER_DATA_I;
+
+ D_L_O <= D_L_O_int;
+ D_R_O <= D_R_O_int;
+
+--------------------------------------------------------------------------
+---- Output Enable signals (for FIFO)
+--------------------------------------------------------------------------
+-- OE_GEN: process(CLK_I)
+-- begin
+-- if rising_edge(CLK_I) then
+-- if Cnt_Lrclk = 31 and BCLK_Fall = '1' then
+-- if LRCLK_int = '1' then -- Right channel
+-- OE_R_int <= '1';
+-- else -- Left channel
+-- OE_L_int <= '1';
+-- end if;
+-- else
+-- OE_R_int <= '0';
+-- OE_L_int <= '0';
+-- end if;
+-- end if;
+-- end process OE_GEN;
+
+-- OE_R_O <= OE_R_int when EN_TX_I = '1' else '0';
+-- OE_L_O <= OE_L_int when EN_TX_I = '1' else '0';
+
+--------------------------------------------------------------------------
+---- Write Enable signals (for FIFO)
+--------------------------------------------------------------------------
+-- WE_GEN: process(CLK_I)
+-- begin
+-- if rising_edge(CLK_I) then
+-- if Cnt_Lrclk = 1 and BCLK_Rise = '1' then
+-- if LRCLK_int = '1' then -- Right channel
+-- WE_R_int <= '1';
+-- else -- Left channel
+-- WE_L_int <= '1';
+-- end if;
+-- else
+-- WE_R_int <= '0';
+-- WE_L_int <= '0';
+-- end if;
+-- end if;
+-- end process WE_GEN;
+
+-- WE_R_O <= WE_R_int when EN_RX_I = '1' else '0';
+-- WE_L_O <= WE_L_int when EN_RX_I = '1' else '0';
+
+end Behavioral;
+
diff --git a/src/hdl/module_A.vhd b/src/hdl/module_A.vhd
new file mode 100644
index 0000000..767dbcb
--- /dev/null
+++ b/src/hdl/module_A.vhd
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity module_A is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_wave_sel : in std_logic_vector(1 downto 0);
+ I_middle : in std_logic;
+ I_last : in std_logic;
+ O_u_d : out std_logic;
+ O_sign_sel : out std_logic
+ );
+end module_A;
+
+architecture behavioral of module_A is
+
+ type state_type is (st_0_to_PI_2, st_PI_2_to_PI, st_PI_to_3_PI_2, st_3_PI_2_to_2_PI);
+ signal state_reg : state_type := st_0_to_PI_2;
+
+begin
+
+ process (I_clk)
+ begin
+ if rising_edge(I_clk) then
+ if I_rst = '1' then
+ state_reg <= st_0_to_PI_2;
+ O_sign_sel <= '0';
+ else
+ case state_reg is
+ when st_0_to_PI_2 =>
+ if I_middle = '1' then
+ state_reg <= st_PI_2_to_PI;
+ end if;
+ when st_PI_2_to_PI =>
+ if I_last = '1' then
+ state_reg <= st_PI_to_3_PI_2;
+ end if;
+ when st_PI_to_3_PI_2 =>
+ if I_middle = '1' then
+ state_reg <= st_3_PI_2_to_2_PI;
+ end if;
+ when st_3_PI_2_to_2_PI =>
+ if I_last = '1' then
+ state_reg <= st_0_to_PI_2;
+ end if;
+ end case;
+
+ O_sign_sel <= '0' when state_reg = st_0_to_PI_2 or state_reg = st_PI_2_to_PI else '1';
+
+ end if;
+ end if;
+ end process;
+
+ O_u_d <= '1' when (I_wave_sel /= "11" and (state_reg = st_0_to_PI_2 or state_reg = st_PI_to_3_PI_2)) or (I_wave_sel = "11" and (state_reg = st_0_to_PI_2 or state_reg = st_PI_2_to_PI)) else
+ '0';
+
+end behavioral;
diff --git a/src/hdl/module_B.vhd b/src/hdl/module_B.vhd
new file mode 100644
index 0000000..8fca774
--- /dev/null
+++ b/src/hdl/module_B.vhd
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity module_B is
+ generic (
+ G_MAX_VAL : natural := 25
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_u_d : in std_logic;
+ O_val : out std_logic_vector(integer(ceil(log2(real(G_MAX_VAL)))) - 1 downto 0);
+ O_last : out std_logic;
+ O_middle : out std_logic
+ );
+end module_B;
+
+architecture behavioral of module_B is
+
+ signal SR_val_reg : natural range 0 to G_MAX_VAL := 0;
+ constant C_middle_val : natural := G_MAX_VAL/2;
+
+begin
+
+ process(I_clk)
+ begin
+ if rising_edge(I_clk) then
+ if I_rst = '1' then
+ SR_val_reg <= 0;
+ else
+ if I_u_d = '1' then
+ SR_val_reg <= SR_val_reg + 1;
+ else
+ SR_val_reg <= SR_val_reg - 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ O_last <= '1' when (I_u_d = '1' and SR_val_reg = G_MAX_VAL-1) or (I_u_d = '0' and SR_val_reg = 1) else '0';
+ O_middle <= '1' when (I_u_d = '1'and SR_val_reg = C_middle_val-1) or (I_u_d = '0' and SR_val_reg = C_middle_val+1) else '0';
+
+ O_val <= std_logic_vector(to_unsigned(SR_val_reg, integer(ceil(log2(real(G_MAX_VAL))))));
+
+end behavioral;
diff --git a/src/hdl/module_C.vhd b/src/hdl/module_C.vhd
new file mode 100644
index 0000000..c848949
--- /dev/null
+++ b/src/hdl/module_C.vhd
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use work.wave_package.all;
+
+entity module_C is
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_addr : in std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 1 downto 0);
+ O_sine : out std_logic_vector(G_N-1 downto 0)
+ );
+end module_C;
+
+architecture behavioral of module_C is
+
+ constant C_LUT_SIZE : natural := natural(floor(G_fs/(4.0*G_f0)))+1; -- number of samples in the LUT for phases ranging from 0 to PI/2 (inclusive)
+ signal SR_lut : lut_type(0 to C_LUT_SIZE-1)(G_N-1 downto 0) := sine_table(C_LUT_SIZE, G_N, G_f0, G_fs);
+ signal SR_sine_out : signed(G_N-1 downto 0) := (others => '0');
+ signal SC_sat_addr : integer range 0 to C_LUT_SIZE - 1;
+
+begin
+
+ SC_sat_addr <= to_integer(unsigned(I_addr)) when unsigned(I_addr) < C_LUT_SIZE else C_LUT_SIZE - 1;
+
+ process(I_clk)
+ begin
+ if rising_edge(I_clk) then
+ if I_rst = '1' then
+ SR_sine_out <= (others => '0');
+ else
+ SR_sine_out <= SR_lut(SC_sat_addr);
+ end if;
+ end if;
+ end process;
+
+ O_sine <= std_logic_vector(SR_sine_out);
+
+end behavioral;
diff --git a/src/hdl/module_D.vhd b/src/hdl/module_D.vhd
new file mode 100644
index 0000000..fec2d69
--- /dev/null
+++ b/src/hdl/module_D.vhd
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use work.wave_package.all;
+
+entity module_D is
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_addr : in std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 1 downto 0);
+ O_triangle : out std_logic_vector(G_N-1 downto 0)
+ );
+end module_D;
+
+architecture behavioral of module_D is
+
+ constant C_LUT_SIZE : natural := natural(floor(G_fs/(4.0*G_f0))) + 1; -- number of samples in the LUT for phases ranging from 0 to PI/2 (inclusive)
+ signal SR_lut : lut_type(0 to C_LUT_SIZE-1)(G_N-1 downto 0) := triangle_table(C_LUT_SIZE, G_N, G_f0, G_fs);
+ signal SR_triangle_out : signed(G_N-1 downto 0) := (others => '0');
+ signal SC_sat_addr : integer range 0 to C_LUT_SIZE - 1;
+
+begin
+
+ SC_sat_addr <= to_integer(unsigned(I_addr)) when unsigned(I_addr) < C_LUT_SIZE else C_LUT_SIZE - 1;
+
+ process(I_clk)
+ begin
+ if rising_edge(I_clk) then
+ if I_rst = '1' then
+ SR_triangle_out <= (others => '0');
+ else
+ SR_triangle_out <= SR_lut(SC_sat_addr);
+ end if;
+ end if;
+ end process;
+
+ O_triangle <= std_logic_vector(SR_triangle_out);
+
+end behavioral;
diff --git a/src/hdl/module_E.vhd b/src/hdl/module_E.vhd
new file mode 100644
index 0000000..4158ebb
--- /dev/null
+++ b/src/hdl/module_E.vhd
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use work.wave_package.all;
+
+entity module_E is
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_addr : in std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(2.0*G_f0))))))) - 1 downto 0);
+ O_saw_tooth : out std_logic_vector(G_N-1 downto 0)
+ );
+end module_E;
+
+architecture behavioral of module_E is
+
+ constant C_LUT_SIZE : natural := natural(floor(G_fs/(2.0*G_f0))) + 1; -- number of samples in the LUT for phases ranging from 0 to PI (inclusive)
+ signal SR_lut : lut_type(0 to C_LUT_SIZE-1)(G_N-1 downto 0) := saw_tooth_table(C_LUT_SIZE, G_N, G_f0, G_fs);
+ signal SR_saw_tooth_out : signed(G_N-1 downto 0) := (others => '0');
+
+begin
+
+ process(I_clk)
+ begin
+ if rising_edge(I_clk) then
+ if I_rst = '1' then
+ SR_saw_tooth_out <= (others => '0');
+ else
+ SR_saw_tooth_out <= SR_lut(to_integer(unsigned(I_addr)));
+ end if;
+ end if;
+ end process;
+
+ O_saw_tooth <= std_logic_vector(SR_saw_tooth_out);
+
+end behavioral;
diff --git a/src/hdl/module_F.vhd b/src/hdl/module_F.vhd
new file mode 100644
index 0000000..c5eb249
--- /dev/null
+++ b/src/hdl/module_F.vhd
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity module_F is
+ port (
+ I_sel : in std_logic_vector(1 downto 0);
+ I_din0, I_din1, I_din2, I_din3 : in std_logic_vector;
+ O_dout : out std_logic_vector
+ );
+end module_F;
+
+architecture behavioral of module_F is
+
+begin
+
+ process(I_sel, I_din0, I_din1, I_din2, I_din3)
+ begin
+ case I_sel is
+ when "00" =>
+ O_dout <= I_din0;
+ when "01" =>
+ O_dout <= I_din1;
+ when "10" =>
+ O_dout <= I_din2;
+ when others =>
+ O_dout <= I_din3;
+ end case;
+ end process;
+
+end behavioral;
diff --git a/src/hdl/module_G.vhd b/src/hdl/module_G.vhd
new file mode 100644
index 0000000..8b9b5f8
--- /dev/null
+++ b/src/hdl/module_G.vhd
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity module_G is
+ generic (G_N : natural := 24);
+ port (
+ I_din : in std_logic_vector(G_N-1 downto 0);
+ O_dout : out std_logic_vector(G_N-1 downto 0)
+ );
+end module_G;
+
+architecture behavioral of module_G is
+
+ --Min and max values of signed signals
+ constant C_min_val : std_logic_vector := std_logic_vector(to_signed(-2**(G_N-1), G_N));
+ constant C_max_val : std_logic_vector := std_logic_vector(to_signed(2**(G_N-1)-1, G_N));
+
+begin
+
+ O_dout <= C_max_val when I_din = C_min_val else std_logic_vector(-signed(I_din));
+-- be careful: this test suggests that a clipping error of one LSB is accepted.
+end behavioral;
diff --git a/src/hdl/module_H.vhd b/src/hdl/module_H.vhd
new file mode 100644
index 0000000..7f3866e
--- /dev/null
+++ b/src/hdl/module_H.vhd
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity module_H is
+ port (
+ I_sel : in std_logic;
+ I_din0, I_din1 : in std_logic_vector;
+ O_dout : out std_logic_vector
+ );
+end module_H;
+
+architecture behavioral of module_H is
+
+begin
+
+ process(I_sel, I_din0, I_din1)
+ begin
+ if I_sel = '0' then
+ O_dout <= I_din0;
+ else
+ O_dout <= I_din1;
+ end if;
+ end process;
+
+end behavioral;
diff --git a/src/hdl/module_I.vhd b/src/hdl/module_I.vhd
new file mode 100644
index 0000000..db56391
--- /dev/null
+++ b/src/hdl/module_I.vhd
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity module_I is
+ generic (
+ G_N : natural := 8
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_din : in std_logic_vector(G_N-1 downto 0);
+ O_dout : out std_logic_vector(G_N-1 downto 0)
+ );
+end module_I;
+
+architecture behavioral of module_I is
+
+ signal SR_dout : std_logic_vector(G_N-1 downto 0) := (others => '0');
+
+begin
+
+ process(I_clk)
+ begin
+ if rising_edge(I_clk) then
+ if I_rst = '1' then
+ SR_dout <= (others => '0');
+ else
+ SR_dout <= I_din;
+ end if;
+ end if;
+ end process;
+
+ O_dout <= SR_dout;
+
+end behavioral;
diff --git a/src/hdl/synthesizer.vhd b/src/hdl/synthesizer.vhd
new file mode 100644
index 0000000..03c60ec
--- /dev/null
+++ b/src/hdl/synthesizer.vhd
@@ -0,0 +1,80 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity synthesizer is
+ port (clk : in std_logic;
+ rst : in std_logic;
+
+ wave_sel : in std_logic_vector(1 downto 0);
+ config : in std_logic_vector(3 downto 0); -- configuration of the tone generator
+ keycode : in std_logic_vector (15 downto 0);
+ audio_out : out std_logic_vector (23 downto 0));
+end synthesizer;
+
+architecture Behavioral of synthesizer is
+
+ constant N : natural := 11;
+
+ type tone_array_t is array (0 to N-1) of std_logic_vector (23 downto 0);
+ type keycode_array_t is array (0 to N-1) of std_logic_vector (7 downto 0);
+ type freq_array_t is array (0 to N-1) of real;
+
+ signal tone_out : tone_array_t;
+ signal sum : tone_array_t;
+ signal key : std_logic_vector (0 to N-1);
+ constant keycodes : keycode_array_t := (X"15", X"1D", X"24", X"2D", X"2C", X"35", X"3C", X"43", X"44", X"4D", X"54"); -- 35 is for Y
+ constant freqs : freq_array_t := (392.0, 415.0, 440.0, 466.0, 494.0, 523.0, 554.0, 587.0, 622.0, 659.0, 698.0);
+ --Sol Sol# La Si-b Si Do Do# Re Re# Mi Fa
+
+begin
+
+ -- key(0) <= '1' when (keycode(7 downto 0)=X"15" and keycode(15 downto 8)/=X"F0") else '0';
+ -- key(1) <= '1' when (keycode(7 downto 0)=X"1D" and keycode(15 downto 8)/=X"F0") else '0';
+ -- key(2) <= '1' when (keycode(7 downto 0)=X"24" and keycode(15 downto 8)/=X"F0") else '0';
+ -- key(3) <= '1' when (keycode(7 downto 0)=X"2D" and keycode(15 downto 8)/=X"F0") else '0';
+ -- key(4) <= '1' when (keycode(7 downto 0)=X"2C" and keycode(15 downto 8)/=X"F0") else '0';
+
+ -- I want to be able to play two tones at the same time, and with different durations
+ -- so a tone can be held while I play many other tones
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ key <= (others => '0');
+ else
+ testkeys : for i in 0 to N-1 loop
+ if (keycode(7 downto 0) = keycodes(i) and keycode(15 downto 8) /= X"F0") then
+ key(i) <= '1';
+ else
+ if (keycode(7 downto 0) = keycodes(i) and keycode(15 downto 8) = X"F0") then
+ key(i) <= '0';
+ end if;
+ end if;
+ end loop;
+ end if;
+ end if;
+ end process;
+
+ tone_gen : for i in 0 to N-1 generate
+ tone_inst : entity work.tone_generator
+ generic map(
+ N => 24,
+ f0 => freqs(i),
+ harmonics => 4,
+ fs => 48000.0)
+ port map (clk => clk, rst => rst, wave_sel => wave_sel, config => config, key => key(i), tone_out => tone_out(i));
+
+ end generate;
+
+ -- Mix by adding the tones
+ sum(0) <= std_logic_vector(signed(tone_out(0)));
+
+ sum_gen : for i in 1 to N-1 generate
+ sum(i) <= std_logic_vector(signed(sum(i-1))+signed(tone_out(i)));
+ end generate;
+
+ audio_out <= sum(N-1);
+
+end Behavioral;
diff --git a/src/hdl/tb_ADSR_module.vhd b/src/hdl/tb_ADSR_module.vhd
new file mode 100644
index 0000000..19def84
--- /dev/null
+++ b/src/hdl/tb_ADSR_module.vhd
@@ -0,0 +1,94 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_ADSR_module is
+end tb_ADSR_module;
+
+architecture behavior of tb_ADSR_module is
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ component ADSR_module
+ generic (
+ N : natural := 8;
+ N_t : natural := 16;
+ A_t : real := 10.0;
+ D_t : real := 2.0;
+ R_t : real := 50.0;
+ fs : real := 48000.0
+ );
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ key : in std_logic;
+ gain : out std_logic_vector(N-1 downto 0)
+ );
+ end component;
+
+ -- Signals for connecting to the UUT
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal key : std_logic := '0';
+ signal gain : std_logic_vector(7 downto 0);
+
+ -- Clock period definition
+ constant clk_period : time := 20 ns;
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut : ADSR_module
+ port map (
+ clk => clk,
+ rst => rst,
+ key => key,
+ gain => gain
+ );
+
+ -- Clock process definitions
+ clk_process : process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- hold reset state for 100 ns.
+ rst <= '1';
+ wait for 100 ns;
+ rst <= '0';
+
+ -- Test sequence
+ -- Key press (attack phase)
+ key <= '1';
+ wait for 500 ns;
+
+ -- Key release (release phase)
+ key <= '0';
+ wait for 5000 ns;
+
+ -- Key press (attack phase)
+ key <= '1';
+ wait for 50000 ns;
+
+ -- Key release (release phase)
+ key <= '0';
+ wait for 500 ns;
+
+ -- Key press (attack phase)
+ key <= '1';
+ wait for 5000 ns;
+
+ -- Key release (release phase)
+ key <= '0';
+ wait for 500 ns;
+
+ -- End of test
+ wait;
+ end process;
+
+end behavior;
diff --git a/src/hdl/tb_module_B.vhd b/src/hdl/tb_module_B.vhd
new file mode 100644
index 0000000..873e784
--- /dev/null
+++ b/src/hdl/tb_module_B.vhd
@@ -0,0 +1,93 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_module_B is
+-- Testbench has no ports
+end tb_module_B;
+
+architecture behavior of tb_module_B is
+
+ -- Component declaration for the Unit Under Test (UUT)
+ component module_B
+ generic (
+ G_MAX_VAL : natural := 25
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_u_d : in std_logic;
+ O_val : out std_logic_vector(integer(ceil(log2(real(G_MAX_VAL)))) - 1 downto 0);
+ O_last : out std_logic;
+ O_middle : out std_logic
+ );
+ end component;
+
+ -- Clock period constant
+ constant C_clk_period : time := 10 ns;
+
+ constant C_MAX_VAL : natural := 25;
+
+ -- Signals to connect to UUT
+ signal SR_clk : std_logic := '0';
+ signal SR_rst : std_logic := '0';
+ signal SR_u_d : std_logic := '0';
+ signal SC_val : std_logic_vector(integer(ceil(log2(real(C_MAX_VAL)))) - 1 downto 0);
+ signal SC_last : std_logic;
+ signal SC_middle : std_logic;
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut : module_B
+ generic map (
+ G_MAX_VAL => C_MAX_VAL
+ )
+ port map (
+ I_clk => SR_clk,
+ I_rst => SR_rst,
+ I_u_d => SR_u_d,
+ O_val => SC_val,
+ O_last => SC_last,
+ O_middle => SC_middle
+ );
+
+ -- Clock process
+ clk_process : process
+ begin
+ while true loop
+ SR_clk <= '0';
+ wait for C_clk_period / 2;
+ SR_clk <= '1';
+ wait for C_clk_period / 2;
+ end loop;
+ end process;
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- Reset the system
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+
+ -- Test case 1: Count up
+ SR_u_d <= '1';
+ wait for C_clk_period * 30;
+
+ -- Test case 2: Count down
+ SR_u_d <= '0';
+ wait for C_clk_period * 30;
+
+ -- Test case 3: Reset during operation
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+ wait for C_clk_period * 10;
+
+ -- End simulation
+ wait;
+ end process;
+
+end behavior;
diff --git a/src/hdl/tb_module_C.vhd b/src/hdl/tb_module_C.vhd
new file mode 100644
index 0000000..1cdbe8b
--- /dev/null
+++ b/src/hdl/tb_module_C.vhd
@@ -0,0 +1,96 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_module_C is
+-- Testbench has no ports
+end tb_module_C;
+
+architecture behavior of tb_module_C is
+
+ -- Component declaration for the Unit Under Test (UUT)
+ component module_C
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_addr : in std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 1 downto 0);
+ O_sine : out std_logic_vector(G_N-1 downto 0)
+ );
+ end component;
+
+
+ constant C_N : integer := 16;
+ constant C_f0 : real := 1.0;
+ constant C_fs : real := 100.0;
+ constant C_clk_period : time := 10 ns;
+
+ -- Signals to connect to UUT
+ signal SR_clk : std_logic := '0';
+ signal SR_rst : std_logic := '0';
+ signal SR_addr : std_logic_vector(integer(ceil(log2(real(natural(floor(C_fs/(4.0*C_f0))))))) - 1 downto 0);
+ signal SC_sine_out : std_logic_vector(15 downto 0);
+ signal SR_addrNatural : natural := 0;
+
+ -- Clock period constant
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut : module_C
+ generic map (
+ G_N => C_N,
+ G_f0 => C_f0,
+ G_fs => C_fs
+ )
+ port map (
+ I_clk => SR_clk,
+ I_rst => SR_rst,
+ I_addr => SR_addr,
+ O_sine => SC_sine_out
+ );
+
+ -- Clock process
+ clk_process : process
+ begin
+ while true loop
+ SR_clk <= '0';
+ wait for C_clk_period / 2;
+ SR_clk <= '1';
+ wait for C_clk_period / 2;
+ end loop;
+ end process;
+
+ SR_addr <= std_logic_vector(to_unsigned(SR_addrNatural, integer(ceil(log2(real(natural(floor(C_fs/(4.0*C_f0)))))))));
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- Reset the system
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+
+ -- Test case 1: Sweep through all addresses
+ for i in 0 to natural(floor(C_fs/(4.0*C_f0))) loop
+ SR_addrNatural <= i;
+ wait for C_clk_period;
+ end loop;
+
+ -- Test case 2: Reset during operation
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+ SR_addrNatural <= 0;
+ wait for C_clk_period * 10;
+
+ -- End simulation
+ wait;
+ end process;
+
+end behavior;
diff --git a/src/hdl/tb_module_D.vhd b/src/hdl/tb_module_D.vhd
new file mode 100644
index 0000000..d745e70
--- /dev/null
+++ b/src/hdl/tb_module_D.vhd
@@ -0,0 +1,96 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_module_D is
+-- Testbench has no ports
+end tb_module_D;
+
+architecture behavior of tb_module_D is
+
+ -- Component declaration for the Unit Under Test (UUT)
+ component module_D
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_addr : in std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 1 downto 0);
+ O_triangle : out std_logic_vector(G_N-1 downto 0)
+ );
+ end component;
+
+ -- Clock period constant
+ constant C_clk_period : time := 10 ns;
+
+ constant C_N : integer := 16;
+ constant C_f0 : real := 1.0;
+ constant C_fs : real := 100.0;
+
+ -- Signals to connect to UUT
+ signal SR_clk : std_logic := '0';
+ signal SR_rst : std_logic := '0';
+ signal SR_addr : std_logic_vector(integer(ceil(log2(real(natural(floor(C_fs/(4.0*C_f0))))))) - 1 downto 0);
+ signal SC_triangle_out : std_logic_vector(15 downto 0);
+ signal SR_addrNatural : natural := 0;
+
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut : module_D
+ generic map (
+ G_N => C_N,
+ G_f0 => C_f0,
+ G_fs => C_fs
+ )
+ port map (
+ I_clk => SR_clk,
+ I_rst => SR_rst,
+ I_addr => SR_addr,
+ O_triangle => SC_triangle_out
+ );
+
+ -- Clock process
+ clk_process : process
+ begin
+ while true loop
+ SR_clk <= '0';
+ wait for C_clk_period / 2;
+ SR_clk <= '1';
+ wait for C_clk_period / 2;
+ end loop;
+ end process;
+
+ SR_addr <= std_logic_vector(to_unsigned(SR_addrNatural, integer(ceil(log2(real(natural(floor(C_fs/(4.0*C_f0)))))))));
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- Reset the system
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+
+ -- Test case 1: Sweep through all addresses
+ for i in 0 to natural(floor(C_fs/(4.0*C_f0))) loop
+ SR_addrNatural <= i;
+ wait for C_clk_period;
+ end loop;
+
+ -- Test case 2: Reset during operation
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+ SR_addrNatural <= 0;
+ wait for C_clk_period * 10;
+
+ -- End simulation
+ wait;
+ end process;
+
+end behavior;
diff --git a/src/hdl/tb_module_E.vhd b/src/hdl/tb_module_E.vhd
new file mode 100644
index 0000000..24e7735
--- /dev/null
+++ b/src/hdl/tb_module_E.vhd
@@ -0,0 +1,96 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_module_E is
+-- Testbench has no ports
+end tb_module_E;
+
+architecture behavior of tb_module_E is
+
+ -- Component declaration for the Unit Under Test (UUT)
+ component module_E
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_addr : in std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(2.0*G_f0))))))) - 1 downto 0);
+ O_saw_tooth : out std_logic_vector(G_N-1 downto 0)
+ );
+ end component;
+
+ -- Clock period constant
+ constant C_clk_period : time := 10 ns;
+
+ constant C_N : integer := 16;
+ constant C_f0 : real := 1.0;
+ constant C_fs : real := 100.0;
+
+ -- Signals to connect to UUT
+ signal SR_clk : std_logic := '0';
+ signal SR_rst : std_logic := '0';
+ signal SR_addr : std_logic_vector(integer(ceil(log2(real(natural(floor(C_fs/(2.0*C_f0))))))) - 1 downto 0);
+ signal SC_saw_tooth_out : std_logic_vector(15 downto 0);
+ signal SR_addrNatural : natural := 0;
+
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut : module_E
+ generic map (
+ G_N => C_N,
+ G_f0 => C_f0,
+ G_fs => C_fs
+ )
+ port map (
+ I_clk => SR_clk,
+ I_rst => SR_rst,
+ I_addr => SR_addr,
+ O_saw_tooth => SC_saw_tooth_out
+ );
+
+ -- Clock process
+ clk_process : process
+ begin
+ while true loop
+ SR_clk <= '0';
+ wait for C_clk_period / 2;
+ SR_clk <= '1';
+ wait for C_clk_period / 2;
+ end loop;
+ end process;
+
+ SR_addr <= std_logic_vector(to_unsigned(SR_addrNatural, integer(ceil(log2(real(natural(floor(C_fs/(2.0*C_f0)))))))));
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- Reset the system
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+
+ -- Test case 1: Sweep through all addresses
+ for i in 0 to natural(floor(C_fs/(2.0*C_f0))) loop
+ SR_addrNatural <= i;
+ wait for C_clk_period;
+ end loop;
+
+ -- Test case 2: Reset during operation
+ SR_rst <= '1';
+ wait for C_clk_period * 2;
+ SR_rst <= '0';
+ SR_addrNatural <= 0;
+ wait for C_clk_period * 10;
+
+ -- End simulation
+ wait;
+ end process;
+
+end behavior;
diff --git a/src/hdl/tb_module_F.vhd b/src/hdl/tb_module_F.vhd
new file mode 100644
index 0000000..c432165
--- /dev/null
+++ b/src/hdl/tb_module_F.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_module_F is
+end tb_module_F;
+
+architecture behavioral of tb_module_F is
+
+ component module_F is
+ port (
+ I_sel : in std_logic_vector(1 downto 0);
+ I_din0, I_din1, I_din2, I_din3 : in std_logic_vector;
+ O_dout : out std_logic_vector);
+ end component module_F;
+
+ constant C_Size : natural := 16;
+
+ signal SC_sel : std_logic_vector(1 downto 0);
+ signal SC_din0 : std_logic_vector(C_Size -1 downto 0) := std_logic_vector(to_unsigned(3, C_Size));
+ signal SC_din1 : std_logic_vector(C_Size -1 downto 0) := std_logic_vector(to_unsigned(5, C_Size));
+ signal SC_din2 : std_logic_vector(C_Size -1 downto 0) := std_logic_vector(to_unsigned(8, C_Size));
+ signal SC_din3 : std_logic_vector(C_Size -1 downto 0) := std_logic_vector(to_unsigned(12, C_Size));
+ signal SC_dout : std_logic_vector(C_Size -1 downto 0);
+
+begin
+
+ SC_sel <= "00", "01" after 33 ns, "10" after 66 ns, "11" after 99 ns;
+
+ module_F_1 : entity work.module_F
+ port map (
+ I_sel => SC_sel,
+ I_din0 => SC_din0,
+ I_din1 => SC_din1,
+ I_din2 => SC_din2,
+ I_din3 => SC_din3,
+ O_dout => SC_dout
+ );
+
+end behavioral;
diff --git a/src/hdl/tb_module_G.vhd b/src/hdl/tb_module_G.vhd
new file mode 100644
index 0000000..8e00f7a
--- /dev/null
+++ b/src/hdl/tb_module_G.vhd
@@ -0,0 +1,66 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_module_G is
+end tb_module_G;
+
+architecture testbench of tb_module_G is
+ signal SR_din : std_logic_vector(7 downto 0);
+ signal SC_dout : std_logic_vector(7 downto 0);
+
+ -- Instantiate the Unit Under Test (UUT)
+ component module_G
+ generic (
+ G_N : natural := 24
+ );
+ port (
+ I_din : in std_logic_vector(7 downto 0);
+ O_dout : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+begin
+
+ -- Instantiate the UUT
+ uut : module_G
+ generic map (
+ G_N => 8
+ )
+ port map (
+ I_din => SR_din,
+ O_dout => SC_dout
+ );
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- Test case 1
+ SR_din <= "00000001"; -- 1
+ wait for 10 ns;
+ assert SC_dout = "11111111" report "Test case 1 failed" severity error; -- -1
+
+ -- Test case 2
+ SR_din <= "00000010"; -- 2
+ wait for 10 ns;
+ assert SC_dout = "11111110" report "Test case 2 failed" severity error; -- -2
+
+ -- Test case 3
+ SR_din <= "00000100"; -- 4
+ wait for 10 ns;
+ assert SC_dout = "11111100" report "Test case 3 failed" severity error; -- -4
+
+ -- Test case 4
+ SR_din <= "10000000"; -- -128 (two's complement)
+ wait for 10 ns;
+ assert SC_dout = "01111111" report "Test case 4 failed" severity error; -- -128 (two's complement)
+ -- be careful: this test suggests that a clipping error of one LSB is accepted.
+
+ -- Test case 5
+ SR_din <= "11111111"; -- -1 (two's complement)
+ wait for 10 ns;
+ assert SC_dout = "00000001" report "Test case 5 failed" severity error; -- 1
+
+ wait;
+ end process;
+end testbench;
diff --git a/src/hdl/tb_module_H.vhd b/src/hdl/tb_module_H.vhd
new file mode 100644
index 0000000..2f49f25
--- /dev/null
+++ b/src/hdl/tb_module_H.vhd
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_module_H is
+end tb_module_H;
+
+architecture behavioral of tb_module_H is
+
+ component module_H is
+ port (
+ I_sel : in std_logic;
+ I_din0, I_din1 : in std_logic_vector;
+ O_dout : out std_logic_vector
+ );
+ end component module_H;
+
+ constant C_Size : natural := 16;
+
+ signal SC_sel : std_logic;
+ signal SC_din0 : std_logic_vector(C_Size - 1 downto 0) := std_logic_vector(to_unsigned(5, C_Size));
+ signal SC_din1 : std_logic_vector(C_Size - 1 downto 0) := std_logic_vector(to_unsigned(12, C_Size));
+ signal SC_dout : std_logic_vector(C_Size - 1 downto 0);
+
+begin
+
+ SC_sel <= '0', '1' after 33 ns, '0' after 66 ns, '1' after 99 ns;
+
+ module_H_1 : entity work.module_H
+ port map (
+ I_sel => SC_sel,
+ I_din0 => SC_din0,
+ I_din1 => SC_din1,
+ O_dout => SC_dout);
+
+end behavioral;
diff --git a/src/hdl/tb_module_I.vhd b/src/hdl/tb_module_I.vhd
new file mode 100644
index 0000000..c4c380e
--- /dev/null
+++ b/src/hdl/tb_module_I.vhd
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_module_I is
+end tb_module_I;
+
+architecture behavioral of tb_module_I is
+
+ component module_I is
+ generic (
+ G_N : natural := 8
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_din : in std_logic_vector(G_N-1 downto 0);
+ O_dout : out std_logic_vector(G_N-1 downto 0)
+ );
+ end component module_I;
+
+ constant C_Size : natural := 16;
+
+ signal SR_clk : std_logic := '1';
+ signal SR_rst : std_logic := '0';
+ signal SR_din : std_logic_vector(C_Size-1 downto 0);
+ signal SC_dout : std_logic_vector(C_Size-1 downto 0);
+
+begin
+
+ SR_rst <= '0', '1' after 29 ns, '0' after 57 ns;
+
+ SR_clk <= not SR_clk after 7 ns;
+
+ SR_din <= std_logic_vector(to_unsigned(3, C_Size)),
+ std_logic_vector(to_unsigned(7, C_Size)) after 87 ns,
+ std_logic_vector(to_unsigned(13, C_Size)) after 129 ns;
+
+ module_I_1 : entity work.module_I
+ generic map (
+ G_N => C_Size)
+ port map (
+ I_clk => SR_clk,
+ I_rst => SR_rst,
+ I_din => SR_din,
+ O_dout => SC_dout);
+
+
+end behavioral;
diff --git a/src/hdl/tb_wave_generator.vhd b/src/hdl/tb_wave_generator.vhd
new file mode 100644
index 0000000..179cb1f
--- /dev/null
+++ b/src/hdl/tb_wave_generator.vhd
@@ -0,0 +1,73 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_wave_generator is
+end tb_wave_generator;
+
+architecture behavior of tb_wave_generator is
+
+ -- Constants for the testbench
+ constant N : integer := 8;
+ constant f0 : real := 1.0;
+ constant fs : real := 100.0;
+
+ -- Signals for the testbench
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal wave_sel : std_logic_vector(1 downto 0) := "00";
+ signal wav : std_logic_vector(N-1 downto 0);
+
+ -- Clock period definition
+ constant clk_period : time := 10 ns;
+
+begin
+
+ process
+ begin
+ wait for 3 us;
+ wave_sel <= std_logic_vector(unsigned(wave_sel) + 1);
+ end process;
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut : entity work.wave_generator
+ generic map (
+ G_N => N,
+ G_f0 => f0,
+ G_fs => fs
+ )
+ port map (
+ I_clk => clk,
+ I_rst => rst,
+ I_wave_sel => wave_sel,
+ O_wav => wav
+ );
+
+ -- Clock process definitions
+ clk_process : process
+ begin
+ while true loop
+ clk <= '0';
+ wait for clk_period / 2;
+ clk <= '1';
+ wait for clk_period / 2;
+ end loop;
+ end process;
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ -- Reset the system
+ rst <= '1';
+ wait for 20 ns;
+ rst <= '0';
+
+ -- Wait for some time to observe the output
+ wait for 1000 ns;
+
+ -- Finish simulation
+ wait;
+ end process;
+
+end behavior;
diff --git a/src/hdl/tone_generator.vhd b/src/hdl/tone_generator.vhd
new file mode 100644
index 0000000..7aab15c
--- /dev/null
+++ b/src/hdl/tone_generator.vhd
@@ -0,0 +1,85 @@
+-- VHDL module for a tone generator
+-- based on waves
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use IEEE.MATH_REAL.all;
+
+entity tone_generator is
+ generic (
+ N : natural := 24; -- number of bits in the output signal
+ f0 : real := 1000.0; -- frequency of the tone
+ harmonics : natural := 4; -- number of harmonics
+ fs : real := 48000.0 -- sampling frequency
+ );
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ wave_sel : in std_logic_vector(1 downto 0); -- type of waveform (sine, square, triangle, saw-tooth)
+ config : in std_logic_vector(harmonics-1 downto 0); -- configuration of the tone generator
+ key : in std_logic; -- key input
+ tone_out : out std_logic_vector(N-1 downto 0)
+ );
+end tone_generator;
+
+architecture arch of tone_generator is
+ -- when adding sine_waves, we have to deal with the fact that the magnitude of the sum may overflow
+ -- we divide the magnitude of each harmonic by 2^i, where i is the harmonic number
+ -- this way, the sum of the harmonics will not overflow
+
+ type wawe_array_t is array (0 to harmonics-1) of std_logic_vector(N-1-natural(log2(real(harmonics))) downto 0);
+ type wawe_array_sum_t is array (0 to harmonics-1) of signed(N-1 downto 0);
+
+ signal wave_array : wawe_array_t;
+ signal wave_array_sum : wawe_array_sum_t;
+ signal gain : std_logic_vector(7 downto 0); -- triggered by the key
+ signal tone_out_signed : signed(N-1 downto 0);
+ signal tone_out_mult : signed(N+8 downto 0);
+
+begin
+
+ adsr_inst : entity work.ADSR_module
+ generic map (
+ N => 8,
+ N_t => 16, --number of bits to count the time
+ A_t => 10.0, -- length of the attack in ms
+ D_t => 2.0, -- length of the decay in ms
+ R_t => 50.0, -- length of the release in ms
+ fs => fs -- sampling frequency
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ key => key,
+ gain => gain
+ );
+
+ gen_wave : for i in 0 to harmonics-1 generate
+ wave_generator_inst : entity work.wave_generator
+ generic map (
+ G_N => N-natural(log2(real(harmonics))),
+ G_f0 => f0*(natural(i)+1),
+ G_fs => fs
+ )
+ port map (
+ I_clk => clk,
+ I_rst => rst,
+ I_wave_sel => wave_sel,
+ O_wav => wave_array(i)
+ );
+ end generate;
+
+ wave_array_sum(0) <= resize(signed(wave_array(0)), N);
+ sum : for i in 1 to harmonics-1 generate
+ wave_array_sum(i) <= wave_array_sum(i-1) + resize(shift_right(signed(wave_array(i)), i), N) when config(i) = '1' else wave_array_sum(i-1); -- divide by 2^i the magnitude of
+ -- of the i-th harmonic
+ -- of the i-th harmonic
+ end generate;
+
+ tone_out_mult <= wave_array_sum(harmonics-1) * signed('0'&gain);
+
+ tone_out <= std_logic_vector(tone_out_mult(N+8 downto 9));
+ --tone_out <= std_logic_vector(sine_wave_array_sum(harmonics-1));
+
+end architecture arch;
diff --git a/src/hdl/wave_generator.vhd b/src/hdl/wave_generator.vhd
new file mode 100644
index 0000000..310c78f
--- /dev/null
+++ b/src/hdl/wave_generator.vhd
@@ -0,0 +1,161 @@
+-- TOP module of a wave generator
+-- generic parameters:
+-- N: number of bits of the sine value
+-- f0: fundamental frequency
+-- fs: sampling frequency
+-- Inputs:
+-- CLK, RST
+-- WAVE_SEL : selects the type of waveform (sine, square, triangle, saw-tooth)
+-- Outputs:
+-- WAV: the wave output
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity wave_generator is
+ generic (
+ G_N : integer := 8;
+ G_f0 : real := 1.0;
+ G_fs : real := 100.0
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_wave_sel : in std_logic_vector(1 downto 0);
+ O_wav : out std_logic_vector(G_N-1 downto 0)
+ );
+end wave_generator;
+
+architecture arch of wave_generator is
+
+ constant C_addr_half_w : integer := integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0)))))));
+
+ signal S_addr : std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(2.0*G_f0))))))) - 1 downto 0);
+ signal S_sine_out_lut : std_logic_vector(G_N-1 downto 0);
+ signal S_square : std_logic_vector(G_N-1 downto 0);
+ signal S_triangle_out_lut : std_logic_vector(G_N-1 downto 0);
+ signal S_saw_tooth_out_lut : std_logic_vector(G_N-1 downto 0);
+ signal S_opposite_wave_sample : std_logic_vector(G_N-1 downto 0);
+ signal S_wave_value : std_logic_vector(G_N-1 downto 0);
+ signal S_wave_sample : std_logic_vector(G_N-1 downto 0);
+ signal S_last : std_logic;
+ signal S_middle : std_logic;
+ signal S_u_d : std_logic;
+ signal S_sign_sel : std_logic;
+
+begin
+ -- Module A
+ A_inst : entity work.module_A
+ port map (
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_wave_sel => I_wave_sel,
+ I_middle => S_middle,
+ I_last => S_last,
+ O_u_d => S_u_d,
+ O_sign_sel => S_sign_sel
+ );
+
+ -- Module B
+ B_inst : entity work.module_B
+ generic map (
+ G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
+ )
+ port map (
+ I_clk => ,
+ I_rst => ,
+ I_u_d => ,
+ O_val => ,
+ O_last => ,
+ O_middle =>
+ );
+
+ -- Module C
+ C_inst : entity work.module_C
+ generic map (
+ G_N => G_N,
+ G_f0 => G_f0,
+ G_fs => G_fs
+ )
+ port map (
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_addr => S_addr(C_addr_half_w-1 downto 0),
+ O_sine => S_sine_out_lut
+ );
+
+ -- Module D
+ D_inst : entity work.module_D
+ generic map (
+ G_N => G_N,
+ G_f0 => G_f0,
+ G_fs => G_fs
+ )
+ port map (
+ I_clk => ,
+ I_rst => ,
+ I_addr => ,
+ O_triangle =>
+ );
+
+ -- Module E
+ E_inst : entity work.module_E
+ generic map (
+ G_N => G_N,
+ G_f0 => G_f0,
+ G_fs => G_fs
+ )
+ port map (
+ I_clk => ,
+ I_rst => ,
+ I_addr => ,
+ O_saw_tooth =>
+ );
+
+ S_square <= ((G_N-1) => '0', others => '1');
+
+ -- Module F
+ F_inst : entity work.module_F
+ port map (
+ I_sel => ,
+ I_din0 => ,
+ I_din1 => ,
+ I_din2 => ,
+ I_din3 => ,
+ O_dout =>
+ );
+
+ -- Module G
+ G_inst : entity work.module_G
+ generic map(
+ G_N => G_N
+ )
+ port map (
+ I_din => ,
+ O_dout =>
+ );
+
+ -- Module H
+ H_inst : entity work.module_H
+ port map (
+ I_sel => ,
+ I_din0 => ,
+ I_din1 => ,
+ O_dout =>
+ );
+
+ -- Module I
+ I_inst : entity work.module_I
+ generic map (
+ G_N => G_N
+ )
+ port map (
+ I_clk => ,
+ I_rst => ,
+ I_din => ,
+ O_dout =>
+ );
+
+end arch;
diff --git a/src/hdl/wave_package.vhd b/src/hdl/wave_package.vhd
new file mode 100644
index 0000000..5317ba7
--- /dev/null
+++ b/src/hdl/wave_package.vhd
@@ -0,0 +1,71 @@
+library IEEE;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+package wave_package is
+
+ type lut_type is array(natural range <>) of signed;
+
+ function sine_table(constant LUT_SIZE, N : natural; constant f0, fs : real) return lut_type;
+ function triangle_table(constant LUT_SIZE, N : natural; constant f0, fs : real) return lut_type;
+ function saw_tooth_table(constant LUT_SIZE, N : natural; constant f0, fs : real) return lut_type;
+
+end wave_package;
+
+package body wave_package is
+
+ function sine_table(constant LUT_SIZE, N : natural; constant f0, fs : real) return lut_type is
+ variable sine_lut : lut_type(0 to LUT_SIZE-1)(N-1 downto 0);
+ variable sine_int : integer;
+ begin
+ for i in 0 to LUT_SIZE-1 loop
+ sine_int := integer(round(2**(N-1) * sin(MATH_2_PI* f0 * real(i) / fs))); -- 1 bit for sign, 0 bit for integer part and N-2 bits for fractional part
+ -- this means that the LUT will contain values in the range -1 to 1-2^(-N+1)
+ -- and that there will always be an approximation error of 2^(-N+1) in the sine value for +1
+ -- saturate the sine value to the range -1 to 1-2^(-N+1)
+ if sine_int > 2**(N-1)-1 then
+ sine_int := 2**(N-1)-1;
+ end if;
+ sine_lut(i) := to_signed(sine_int, N);
+ end loop;
+ return sine_lut;
+ end function;
+
+
+ function triangle_table(constant LUT_SIZE, N : natural; constant f0, fs : real) return lut_type is
+ variable triangle_lut : lut_type(0 to LUT_SIZE-1)(N-1 downto 0);
+ variable triangle_int : integer;
+ begin
+ for i in 0 to LUT_SIZE-1 loop
+ triangle_int := integer(round(2**(N-1) * real(i) * 4 * f0 / fs)); -- 1 bit for sign, 0 bit for integer part and N-2 bits for fractional part
+ -- this means that the LUT will contain values in the range -1 to 1-2^(-N+1)
+ -- and that there will always be an approximation error of 2^(-N+1) in the value for +1
+ -- saturate the sine value to the range -1 to 1-2^(-N+1)
+ if triangle_int > 2**(N-1)-1 then
+ triangle_int := 2**(N-1)-1;
+ end if;
+ triangle_lut(i) := to_signed(triangle_int, N);
+ end loop;
+ return triangle_lut;
+ end function;
+
+
+ function saw_tooth_table(constant LUT_SIZE, N : natural; constant f0, fs : real) return lut_type is
+ variable triangle_lut : lut_type(0 to LUT_SIZE-1)(N-1 downto 0);
+ variable triangle_int : integer;
+ begin
+ for i in 0 to LUT_SIZE-1 loop
+ triangle_int := integer(round(2**(N-1) * real(i) * 2 * f0 / fs)); -- 1 bit for sign, 0 bit for integer part and N-2 bits for fractional part
+ -- this means that the LUT will contain values in the range -1 to 1-2^(-N+1)
+ -- and that there will always be an approximation error of 2^(-N+1) in the value for +1
+ -- saturate the sine value to the range -1 to 1-2^(-N+1)
+ if triangle_int > 2**(N-1)-1 then
+ triangle_int := 2**(N-1)-1;
+ end if;
+ triangle_lut(i) := to_signed(triangle_int, N);
+ end loop;
+ return triangle_lut;
+ end function;
+
+end wave_package;
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.dcp b/src/ip/clk_wiz_0/clk_wiz_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..1df5ec10a4ff9e7c1b2e8c55ee8f41698941ff5f
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diff --git a/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log b/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log
new file mode 100644
index 0000000..6bd8d52
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log
@@ -0,0 +1,332 @@
+Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+| Date : Thu Jan 21 16:58:14 2016
+| Host : WK86 running 64-bit Service Pack 1 (build 7601)
+| Command : upgrade_ip
+| Device : xc7a200tsbg484-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'clk_wiz_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the update of clk_wiz_0 (xilinx.com:ip:clk_wiz:5.2) to current project options.
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Warnings
+-----------
+
+WARNING: The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. When checking the upgrade script, note that parameter names are case sensitive.
+
+
+3. Interface Information
+------------------------
+
+Detected external interface differences while upgrading IP 'clk_wiz_0'.
+
+
+-upgrade has removed interface 'clock_CLK_OUT2'
+-upgrade has removed interface 'clock_CLK_OUT3'
+-upgrade has removed interface 'clock_CLK_OUT4'
+-upgrade has added interface 'reset'
+
+4. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading IP 'clk_wiz_0'. These changes may impact your design.
+
+
+-upgrade has removed port 'clk_out2'
+-upgrade has removed port 'clk_out3'
+-upgrade has removed port 'clk_out4'
+-upgrade has added port 'reset'
+
+5. Customization warnings
+-------------------------
+
+WARNING: Value 'sys_clock' is out of the range for parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for IP 'clk_wiz_0' . Valid values are - Custom, sys_diff_clock
+
+WARNING: Customization errors found on 'clk_wiz_0'. Restoring to previous valid configuration.
+
+WARNING: An attempt to modify the value of disabled parameter 'CLKOUT2_REQUESTED_OUT_FREQ' from '200.000' to '100.000' has been ignored for IP 'clk_wiz_0'
+
+WARNING: An attempt to modify the value of disabled parameter 'CLKOUT3_REQUESTED_OUT_FREQ' from '12.000' to '100.000' has been ignored for IP 'clk_wiz_0'
+
+WARNING: An attempt to modify the value of disabled parameter 'CLKOUT4_REQUESTED_OUT_FREQ' from '50.000' to '100.000' has been ignored for IP 'clk_wiz_0'
+
+
+6. Debug Commands
+-----------------
+
+ The following debug information can be passed to Vivado as Tcl commands,
+in order to validate or debug the output of the upgrade flow.
+ Please consult the warnings from the previous sections, and alter or remove
+the configuration parameter(s) which caused the warning; then execute the Tcl
+commands, and use the IP Customization GUI to verify the IP configuration.
+
+create_ip -vlnv xilinx.com:ip:clk_wiz:5.2 -user_name clk_wiz_0
+set_property -dict "\
+ CONFIG.CALC_DONE empty \
+ CONFIG.CDDCDONE_PORT cddcdone \
+ CONFIG.CDDCREQ_PORT cddcreq \
+ CONFIG.CLKFB_IN_N_PORT clkfb_in_n \
+ CONFIG.CLKFB_IN_PORT clkfb_in \
+ CONFIG.CLKFB_IN_P_PORT clkfb_in_p \
+ CONFIG.CLKFB_IN_SIGNALING SINGLE \
+ CONFIG.CLKFB_OUT_N_PORT clkfb_out_n \
+ CONFIG.CLKFB_OUT_PORT clkfb_out \
+ CONFIG.CLKFB_OUT_P_PORT clkfb_out_p \
+ CONFIG.CLKFB_STOPPED_PORT clkfb_stopped \
+ CONFIG.CLKIN1_JITTER_PS 100.0 \
+ CONFIG.CLKIN1_UI_JITTER 0.010 \
+ CONFIG.CLKIN2_JITTER_PS 100.0 \
+ CONFIG.CLKIN2_UI_JITTER 0.010 \
+ CONFIG.CLKOUT1_DRIVES BUFG \
+ CONFIG.CLKOUT1_JITTER 151.366 \
+ CONFIG.CLKOUT1_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT1_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT1_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT1_USED true \
+ CONFIG.CLKOUT2_DRIVES BUFG \
+ CONFIG.CLKOUT2_JITTER 132.221 \
+ CONFIG.CLKOUT2_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT2_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 200.000 \
+ CONFIG.CLKOUT2_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT2_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT2_USED true \
+ CONFIG.CLKOUT3_DRIVES BUFG \
+ CONFIG.CLKOUT3_JITTER 231.952 \
+ CONFIG.CLKOUT3_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT3_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ 12.000 \
+ CONFIG.CLKOUT3_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT3_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT3_USED true \
+ CONFIG.CLKOUT4_DRIVES BUFG \
+ CONFIG.CLKOUT4_JITTER 174.353 \
+ CONFIG.CLKOUT4_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT4_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ 50.000 \
+ CONFIG.CLKOUT4_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT4_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT4_USED true \
+ CONFIG.CLKOUT5_DRIVES BUFG \
+ CONFIG.CLKOUT5_JITTER 0.0 \
+ CONFIG.CLKOUT5_PHASE_ERROR 0.0 \
+ CONFIG.CLKOUT5_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT5_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT5_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT5_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT5_USED false \
+ CONFIG.CLKOUT6_DRIVES BUFG \
+ CONFIG.CLKOUT6_JITTER 0.0 \
+ CONFIG.CLKOUT6_PHASE_ERROR 0.0 \
+ CONFIG.CLKOUT6_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT6_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT6_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT6_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT6_USED false \
+ CONFIG.CLKOUT7_DRIVES BUFG \
+ CONFIG.CLKOUT7_JITTER 0.0 \
+ CONFIG.CLKOUT7_PHASE_ERROR 0.0 \
+ CONFIG.CLKOUT7_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT7_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT7_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT7_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT7_USED false \
+ CONFIG.CLKOUTPHY_REQUESTED_FREQ 600.000 \
+ CONFIG.CLK_IN1_BOARD_INTERFACE sys_clock \
+ CONFIG.CLK_IN2_BOARD_INTERFACE Custom \
+ CONFIG.CLK_IN_SEL_PORT clk_in_sel \
+ CONFIG.CLK_OUT1_PORT clk_out1 \
+ CONFIG.CLK_OUT1_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT2_PORT clk_out2 \
+ CONFIG.CLK_OUT2_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT3_PORT clk_out3 \
+ CONFIG.CLK_OUT3_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT4_PORT clk_out4 \
+ CONFIG.CLK_OUT4_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT5_PORT clk_out5 \
+ CONFIG.CLK_OUT5_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT6_PORT clk_out6 \
+ CONFIG.CLK_OUT6_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT7_PORT clk_out7 \
+ CONFIG.CLK_OUT7_USE_FINE_PS_GUI false \
+ CONFIG.CLK_VALID_PORT CLK_VALID \
+ CONFIG.CLOCK_MGR_TYPE auto \
+ CONFIG.Component_Name clk_wiz_0 \
+ CONFIG.DADDR_PORT daddr \
+ CONFIG.DCLK_PORT dclk \
+ CONFIG.DEN_PORT den \
+ CONFIG.DIFF_CLK_IN1_BOARD_INTERFACE Custom \
+ CONFIG.DIFF_CLK_IN2_BOARD_INTERFACE Custom \
+ CONFIG.DIN_PORT din \
+ CONFIG.DOUT_PORT dout \
+ CONFIG.DRDY_PORT drdy \
+ CONFIG.DWE_PORT dwe \
+ CONFIG.ENABLE_CDDC false \
+ CONFIG.ENABLE_CLKOUTPHY false \
+ CONFIG.FEEDBACK_SOURCE FDBK_AUTO \
+ CONFIG.INPUT_CLK_STOPPED_PORT input_clk_stopped \
+ CONFIG.INPUT_MODE frequency \
+ CONFIG.INTERFACE_SELECTION Enable_AXI \
+ CONFIG.IN_FREQ_UNITS Units_MHz \
+ CONFIG.IN_JITTER_UNITS Units_UI \
+ CONFIG.JITTER_OPTIONS UI \
+ CONFIG.JITTER_SEL No_Jitter \
+ CONFIG.LOCKED_PORT locked \
+ CONFIG.MMCM_BANDWIDTH OPTIMIZED \
+ CONFIG.MMCM_CLKFBOUT_MULT_F 6.000 \
+ CONFIG.MMCM_CLKFBOUT_PHASE 0.000 \
+ CONFIG.MMCM_CLKFBOUT_USE_FINE_PS false \
+ CONFIG.MMCM_CLKIN1_PERIOD 10.0 \
+ CONFIG.MMCM_CLKIN2_PERIOD 10.0 \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F 6.000 \
+ CONFIG.MMCM_CLKOUT0_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT0_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT0_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT1_DIVIDE 3 \
+ CONFIG.MMCM_CLKOUT1_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT1_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT1_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT2_DIVIDE 50 \
+ CONFIG.MMCM_CLKOUT2_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT2_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT2_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT3_DIVIDE 12 \
+ CONFIG.MMCM_CLKOUT3_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT3_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT3_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT4_CASCADE false \
+ CONFIG.MMCM_CLKOUT4_DIVIDE 1 \
+ CONFIG.MMCM_CLKOUT4_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT4_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT4_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT5_DIVIDE 1 \
+ CONFIG.MMCM_CLKOUT5_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT5_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT5_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT6_DIVIDE 1 \
+ CONFIG.MMCM_CLKOUT6_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT6_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT6_USE_FINE_PS false \
+ CONFIG.MMCM_CLOCK_HOLD false \
+ CONFIG.MMCM_COMPENSATION ZHOLD \
+ CONFIG.MMCM_DIVCLK_DIVIDE 1 \
+ CONFIG.MMCM_NOTES None \
+ CONFIG.MMCM_REF_JITTER1 0.010 \
+ CONFIG.MMCM_REF_JITTER2 0.010 \
+ CONFIG.MMCM_STARTUP_WAIT false \
+ CONFIG.NUM_OUT_CLKS 4 \
+ CONFIG.OVERRIDE_MMCM false \
+ CONFIG.OVERRIDE_PLL false \
+ CONFIG.PHASE_DUTY_CONFIG false \
+ CONFIG.PLATFORM UNKNOWN \
+ CONFIG.PLL_BANDWIDTH OPTIMIZED \
+ CONFIG.PLL_CLKFBOUT_MULT 4 \
+ CONFIG.PLL_CLKFBOUT_PHASE 0.000 \
+ CONFIG.PLL_CLKIN_PERIOD 10.000 \
+ CONFIG.PLL_CLKOUT0_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT0_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT0_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT1_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT1_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT1_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT2_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT2_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT2_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT3_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT3_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT3_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT4_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT4_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT4_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT5_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT5_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT5_PHASE 0.000 \
+ CONFIG.PLL_CLK_FEEDBACK CLKFBOUT \
+ CONFIG.PLL_COMPENSATION SYSTEM_SYNCHRONOUS \
+ CONFIG.PLL_DIVCLK_DIVIDE 1 \
+ CONFIG.PLL_NOTES None \
+ CONFIG.PLL_REF_JITTER 0.010 \
+ CONFIG.POWER_DOWN_PORT power_down \
+ CONFIG.PRIMARY_PORT clk_in1 \
+ CONFIG.PRIMITIVE MMCM \
+ CONFIG.PRIMTYPE_SEL mmcm_adv \
+ CONFIG.PRIM_IN_FREQ 100.000 \
+ CONFIG.PRIM_IN_JITTER 0.010 \
+ CONFIG.PRIM_IN_TIMEPERIOD 10.000 \
+ CONFIG.PRIM_SOURCE Single_ended_clock_capable_pin \
+ CONFIG.PSCLK_PORT psclk \
+ CONFIG.PSDONE_PORT psdone \
+ CONFIG.PSEN_PORT psen \
+ CONFIG.PSINCDEC_PORT psincdec \
+ CONFIG.RELATIVE_INCLK REL_PRIMARY \
+ CONFIG.RESET_BOARD_INTERFACE Custom \
+ CONFIG.RESET_PORT reset \
+ CONFIG.RESET_TYPE ACTIVE_HIGH \
+ CONFIG.SECONDARY_IN_FREQ 100.000 \
+ CONFIG.SECONDARY_IN_JITTER 0.010 \
+ CONFIG.SECONDARY_IN_TIMEPERIOD 10.000 \
+ CONFIG.SECONDARY_PORT clk_in2 \
+ CONFIG.SECONDARY_SOURCE Single_ended_clock_capable_pin \
+ CONFIG.SS_MODE CENTER_HIGH \
+ CONFIG.SS_MOD_FREQ 250 \
+ CONFIG.SS_MOD_TIME 0.004 \
+ CONFIG.STATUS_PORT STATUS \
+ CONFIG.SUMMARY_STRINGS empty \
+ CONFIG.USE_BOARD_FLOW false \
+ CONFIG.USE_CLKFB_STOPPED false \
+ CONFIG.USE_CLK_VALID false \
+ CONFIG.USE_CLOCK_SEQUENCING false \
+ CONFIG.USE_DYN_PHASE_SHIFT false \
+ CONFIG.USE_DYN_RECONFIG false \
+ CONFIG.USE_FREEZE false \
+ CONFIG.USE_FREQ_SYNTH true \
+ CONFIG.USE_INCLK_STOPPED false \
+ CONFIG.USE_INCLK_SWITCHOVER false \
+ CONFIG.USE_LOCKED true \
+ CONFIG.USE_MAX_I_JITTER false \
+ CONFIG.USE_MIN_O_JITTER false \
+ CONFIG.USE_MIN_POWER false \
+ CONFIG.USE_PHASE_ALIGNMENT true \
+ CONFIG.USE_POWER_DOWN false \
+ CONFIG.USE_RESET false \
+ CONFIG.USE_SAFE_CLOCK_STARTUP false \
+ CONFIG.USE_SPREAD_SPECTRUM false \
+ CONFIG.USE_STATUS false " [get_ips clk_wiz_0]
+
+
+
+
+
+
+
+Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+| Date : Thu Jan 21 15:55:32 2016
+| Host : WK86 running 64-bit Service Pack 1 (build 7601)
+| Command : upgrade_ip
+| Device : xc7a200tsbg484-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'clk_wiz_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of clk_wiz_0 from xilinx.com:ip:clk_wiz:5.1 (Rev. 7) to xilinx.com:ip:clk_wiz:5.2
+
+2. Upgrade messages
+-------------------
+
+Removed parameter PRIM_IN_FREQ
+Added parameter PRIM_IN_FREQ with value 100.000 (source 'default')
+
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.v b/src/ip/clk_wiz_0/clk_wiz_0.v
new file mode 100644
index 0000000..2e3a203
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0.v
@@ -0,0 +1,100 @@
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+// CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+// CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+// CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module clk_wiz_0
+ (
+ // Clock in ports
+ input clk_in1,
+ // Clock out ports
+ output clk_out1,
+ output clk_out2,
+ output clk_out3,
+ output clk_out4,
+ // Status and control signals
+ input reset,
+ output locked
+ );
+
+ clk_wiz_0_clk_wiz inst
+ (
+ // Clock in ports
+ .clk_in1(clk_in1),
+ // Clock out ports
+ .clk_out1(clk_out1),
+ .clk_out2(clk_out2),
+ .clk_out3(clk_out3),
+ .clk_out4(clk_out4),
+ // Status and control signals
+ .reset(reset),
+ .locked(locked)
+ );
+
+endmodule
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.vho b/src/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100644
index 0000000..c6b126b
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,103 @@
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+
+ -- Clock in ports
+ clk_in1 => clk_in1,
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.xci b/src/ip/clk_wiz_0/clk_wiz_0.xci
new file mode 100644
index 0000000..79f1c0a
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0.xci
@@ -0,0 +1,525 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>clk_wiz_0</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">12.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">12.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">6.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">6.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">50</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______151.366____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______132.221____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____12.000______0.000______50.0______231.952____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4____50.000______0.000______50.0______174.353____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">151.366</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">132.221</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">231.952</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">12.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">174.353</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">6.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">6.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">50</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">sbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.xdc b/src/ip/clk_wiz_0/clk_wiz_0.xdc
new file mode 100644
index 0000000..420a6de
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0.xdc
@@ -0,0 +1,59 @@
+# file: clk_wiz_0.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 10.0 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.10000000000000001
+
+
+
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.xml b/src/ip/clk_wiz_0/clk_wiz_0.xml
new file mode 100644
index 0000000..66fd124
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0.xml
@@ -0,0 +1,4933 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
+ <spirit:name>clk_wiz_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>s_axi_lite</spirit:name>
+ <spirit:displayName>S_AXI_LITE</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_lite" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>s_axi_aclk</spirit:name>
+ <spirit:displayName>s_axi_aclk</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi_lite</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_aclk" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>s_axi_resetn</spirit:name>
+ <spirit:displayName>S_AXI_RESETN</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.ASSOCIATED_RESET">aresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_resetn" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>intr</spirit:name>
+ <spirit:displayName>Intr</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>INTERRUPT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ip2intc_irpt</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.intr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clock_CLK_IN1</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>clk_in1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.BOARD.ASSOCIATED_PARAM">CLK_IN1_BOARD_INTERFACE</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:presence>required</xilinx:presence>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_IN1" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Single_ended_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Single_ended_non_clock_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="No_buffer") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Global_buffer"))">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>CLK_IN1_D</spirit:name>
+ <spirit:displayName>CLK_IN1_D</spirit:displayName>
+ <spirit:description>Differential Clock input</spirit:description>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
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+ <spirit:logicalPort>
+ <spirit:name>CLK_N</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>clk_in1_n</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK_P</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>clk_in1_p</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_IN1_D.BOARD.ASSOCIATED_PARAM">CLK_IN1_BOARD_INTERFACE</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:presence>required</xilinx:presence>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_IN1_D" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_non_clock_pin"))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
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+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cddcreq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_HAS_CDDC'))=1)">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT2_USED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_USED" spirit:order="194">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT3_USED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_USED" spirit:order="195">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT4_USED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_USED" spirit:order="196">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT5_USED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_USED" spirit:order="197">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT6_USED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_USED" spirit:order="198">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT7_USED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_USED" spirit:order="199">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKOUT1_BAR</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR" spirit:order="200">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKOUT2_BAR</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR" spirit:order="201">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKOUT3_BAR</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR" spirit:order="202">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKOUT4_BAR</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR" spirit:order="203">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>c_component_name</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLATFORM" spirit:order="204">UNKNOWN</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREQ_SYNTH" spirit:order="205">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT" spirit:order="206">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_JITTER" spirit:order="207">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER" spirit:order="208">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_JITTER_SEL" spirit:order="209">No_Jitter</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MIN_POWER" spirit:order="210">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MIN_O_JITTER" spirit:order="211">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MAX_I_JITTER" spirit:order="212">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT" spirit:order="213">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER" spirit:order="214">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_RECONFIG" spirit:order="215">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM" spirit:order="216">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FAST_SIMULATION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FAST_SIMULATION" spirit:order="217">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMTYPE_SEL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMTYPE_SEL" spirit:order="218">AUTO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLK_VALID" spirit:order="219">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_FREQ" spirit:order="220">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD" spirit:order="220.001">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IN_FREQ_UNITS" spirit:order="221">Units_MHz</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ" spirit:order="222">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD" spirit:order="222.001">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FEEDBACK_SOURCE" spirit:order="223">FDBK_AUTO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_SOURCE" spirit:order="224">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_SOURCE" spirit:order="225">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING" spirit:order="226">SINGLE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_RESET</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_RESET" spirit:order="227">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_RESET_LOW</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_LOW" spirit:order="408">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_LOCKED" spirit:order="228">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_STOPPED" spirit:order="229">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED" spirit:order="230">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_POWER_DOWN" spirit:order="231">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_STATUS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STATUS" spirit:order="232">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREEZE" spirit:order="233">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OUT_CLKS" spirit:order="234">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DRIVES" spirit:order="235">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DRIVES" spirit:order="236">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DRIVES" spirit:order="237">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DRIVES" spirit:order="238">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DRIVES" spirit:order="239">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DRIVES" spirit:order="240">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DRIVES" spirit:order="241">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW0</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW0" spirit:order="242">Input Clock Freq (MHz) Input Jitter (UI)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW1" spirit:order="243">__primary_________100.000____________0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW2" spirit:order="244">no_secondary_input_clock </spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0A</spirit:name>
+ <spirit:displayName>C Outclk Sum Row0a</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A" spirit:order="245"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0B</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B" spirit:order="246"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">CLK_OUT1___100.000______0.000______50.0______151.366____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">CLK_OUT2___200.000______0.000______50.0______132.221____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">CLK_OUT3____12.000______0.000______50.0______231.952____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">CLK_OUT4____50.000______0.000______50.0______174.353____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5" spirit:order="251">no_CLK_OUT5_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6" spirit:order="252">no_CLK_OUT6_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7" spirit:order="253">no_CLK_OUT7_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="254">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">200.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="256">12.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="257">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="258">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="259">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="260">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE" spirit:order="261">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE" spirit:order="262">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE" spirit:order="263">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE" spirit:order="264">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE" spirit:order="265">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE" spirit:order="266">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE" spirit:order="267">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="268">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="269">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="270">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="271">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="272">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="273">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="274">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">200.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">12.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ" spirit:order="279">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ" spirit:order="280">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ" spirit:order="281">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_PHASE" spirit:order="282">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_PHASE" spirit:order="283">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_PHASE" spirit:order="284">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_PHASE" spirit:order="285">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_PHASE" spirit:order="286">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_PHASE" spirit:order="287">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_PHASE" spirit:order="288">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE" spirit:order="289">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE" spirit:order="290">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE" spirit:order="291">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE" spirit:order="292">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE" spirit:order="293">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE" spirit:order="294">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE" spirit:order="295">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP" spirit:order="500">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING" spirit:order="501">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER" spirit:order="502">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER" spirit:order="503">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER" spirit:order="504">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER" spirit:order="505">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER" spirit:order="506">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER" spirit:order="507">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER" spirit:order="508">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_NOTES" spirit:order="296">None</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_BANDWIDTH" spirit:order="297">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F" spirit:order="298">6.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD" spirit:order="299">10.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD" spirit:order="300">10.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE" spirit:order="301">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD" spirit:order="302">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_COMPENSATION" spirit:order="303">ZHOLD</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE" spirit:order="304">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER1" spirit:order="305">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER2" spirit:order="306">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">6.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">50</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">12</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="315">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="316">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="317">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="318">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="319">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="320">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="321">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE" spirit:order="322">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE" spirit:order="323">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE" spirit:order="324">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE" spirit:order="325">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE" spirit:order="326">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE" spirit:order="327">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE" spirit:order="328">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE" spirit:order="329">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="330">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS" spirit:order="331">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS" spirit:order="332">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS" spirit:order="333">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS" spirit:order="334">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS" spirit:order="335">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS" spirit:order="336">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS" spirit:order="337">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_NOTES" spirit:order="338">No notes</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_BANDWIDTH" spirit:order="339">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK" spirit:order="340">CLKFBOUT</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT" spirit:order="341">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD" spirit:order="342">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_COMPENSATION" spirit:order="343">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE" spirit:order="344">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_REF_JITTER" spirit:order="345">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE" spirit:order="346">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE" spirit:order="347">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE" spirit:order="348">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE" spirit:order="349">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE" spirit:order="350">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE" spirit:order="351">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE" spirit:order="352">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE" spirit:order="353">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE" spirit:order="354">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE" spirit:order="355">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE" spirit:order="356">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE" spirit:order="357">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE" spirit:order="358">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE" spirit:order="359">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE" spirit:order="360">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE" spirit:order="361">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE" spirit:order="362">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE" spirit:order="363">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE" spirit:order="364">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLOCK_MGR_TYPE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE" spirit:order="365">NA</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_MMCM" spirit:order="366">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_PLL" spirit:order="367">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">reset</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_HAS_CDDC</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_876bfc32</spirit:name>
+ <spirit:enumeration>UI</spirit:enumeration>
+ <spirit:enumeration>PS</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_a9bdfce0</spirit:name>
+ <spirit:enumeration>LOW</spirit:enumeration>
+ <spirit:enumeration>HIGH</spirit:enumeration>
+ <spirit:enumeration>OPTIMIZED</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_ac75ef1e</spirit:name>
+ <spirit:enumeration>Custom</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_b9d38208</spirit:name>
+ <spirit:enumeration>CLKFBOUT</spirit:enumeration>
+ <spirit:enumeration>CLKOUT0</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_e099fe6c</spirit:name>
+ <spirit:enumeration>MMCM</spirit:enumeration>
+ <spirit:enumeration>PLL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_035ca1c3</spirit:name>
+ <spirit:enumeration spirit:text="SYSTEM SYNCHRONOUS">SYSTEM_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="SOURCE SYNCHRONOUS">SOURCE_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_0920eb1b</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_11d71346</spirit:name>
+ <spirit:enumeration spirit:text="Single ended clock capable pin">Single_ended_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential clock capable pin">Differential_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Global buffer">Global_buffer</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_15c806d5</spirit:name>
+ <spirit:enumeration spirit:text="Automatic Control On-Chip">FDBK_AUTO</spirit:enumeration>
+ <spirit:enumeration spirit:text="Automatic Control Off-Chip">FDBK_AUTO_OFFCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_3c2d3ec7</spirit:name>
+ <spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential">DIFF</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_502d9f23</spirit:name>
+ <spirit:enumeration spirit:text="ZHOLD">ZHOLD</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUF IN">BUF_IN</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_66e4c81f</spirit:name>
+ <spirit:enumeration spirit:text="BUFG">BUFG</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFH">BUFH</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE">BUFGCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFHCE">BUFHCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8b28f1f7</spirit:name>
+ <spirit:enumeration spirit:text="AXI4Lite">Enable_AXI</spirit:enumeration>
+ <spirit:enumeration spirit:text="DRP">Enable_DRP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8eea9b32</spirit:name>
+ <spirit:enumeration spirit:text="Units MHz">Units_MHz</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ns">Units_ns</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a4fbc00c</spirit:name>
+ <spirit:enumeration spirit:text="Active High">ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="Active Low">ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a8642b4c</spirit:name>
+ <spirit:enumeration spirit:text="Balanced">No_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Minimize Output Jitter">Min_O_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Maximize Input Jitter filtering">Max_I_Jitter</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_c5ef7212</spirit:name>
+ <spirit:enumeration spirit:text="Units UI">Units_UI</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ps">Units_ps</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_e1c87518</spirit:name>
+ <spirit:enumeration spirit:text="Primary Clock">REL_PRIMARY</spirit:enumeration>
+ <spirit:enumeration spirit:text="Secondary Clock">REL_SECONDARY</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f4e10086</spirit:name>
+ <spirit:enumeration spirit:text="CENTER HIGH">CENTER_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="CENTER LOW">CENTER_LOW</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN HIGH">DOWN_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN LOW">DOWN_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f669c2f5</spirit:name>
+ <spirit:enumeration spirit:text="Frequency">frequency</spirit:enumeration>
+ <spirit:enumeration spirit:text="Time">Time</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.vho</spirit:name>
+ <spirit:userFileType>vhdlTemplate</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:define>
+ <spirit:name>processing_order</spirit:name>
+ <spirit:value>early</spirit:value>
+ </spirit:define>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_board.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_board</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>doc/clk_wiz_v5_2_changelog.txt</spirit:name>
+ <spirit:userFileType>text</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clk_wiz_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMITIVE</spirit:name>
+ <spirit:displayName>Primitive</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMITIVE" spirit:choiceRef="choice_list_e099fe6c" spirit:order="2">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMTYPE_SEL</spirit:name>
+ <spirit:displayName>Primtype Sel</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMTYPE_SEL" spirit:order="3">mmcm_adv</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLOCK_MGR_TYPE</spirit:name>
+ <spirit:displayName>Clock Mgr Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_MGR_TYPE" spirit:order="410">auto</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREQ_SYNTH" spirit:order="6" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SPREAD_SPECTRUM" spirit:order="7" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PHASE_ALIGNMENT" spirit:order="8" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_POWER" spirit:order="9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_PHASE_SHIFT" spirit:order="10" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_RECONFIG" spirit:order="11" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_SEL" spirit:choiceRef="choice_pairs_a8642b4c" spirit:order="13" spirit:configGroups="0 NoDisplay">No_Jitter</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_FREQ" spirit:order="14.401" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_TIMEPERIOD" spirit:order="14.9" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_JITTER_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RELATIVE_INCLK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RELATIVE_INCLK" spirit:choiceRef="choice_pairs_e1c87518" spirit:order="17" spirit:configGroups="0 NoDisplay">REL_PRIMARY</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_SWITCHOVER" spirit:order="13.9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_FREQ" spirit:order="21.3" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD" spirit:order="21.299" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_PORT" spirit:order="20" spirit:configGroups="0 NoDisplay">clk_in2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="21" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_OPTIONS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_OPTIONS" spirit:choiceRef="choice_list_876bfc32" spirit:order="22" spirit:configGroups="0 NoDisplay">UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_UI_JITTER" spirit:order="23" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_UI_JITTER" spirit:order="24" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_JITTER" spirit:order="25" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_JITTER" spirit:order="26" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_JITTER_PS" spirit:order="27" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_JITTER_PS" spirit:order="28" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_USED" spirit:order="4" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_USED" spirit:order="29" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_USED" spirit:order="30" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_USED" spirit:order="31" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_USED" spirit:order="32" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_USED" spirit:order="33" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_USED" spirit:order="34" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OUT_CLKS" spirit:order="407" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI" spirit:order="36" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI" spirit:order="37" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI" spirit:order="38" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI" spirit:order="39" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI" spirit:order="40" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI" spirit:order="41" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI" spirit:order="42" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMARY_PORT" spirit:order="43" spirit:configGroups="0 NoDisplay">clk_in1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_PORT" spirit:order="44" spirit:configGroups="0 NoDisplay">clk_out1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_PORT" spirit:order="45" spirit:configGroups="0 NoDisplay">clk_out2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_PORT" spirit:order="46" spirit:configGroups="0 NoDisplay">clk_out3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_PORT" spirit:order="47" spirit:configGroups="0 NoDisplay">clk_out4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_PORT" spirit:order="48" spirit:configGroups="0 NoDisplay">clk_out5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_PORT" spirit:order="49" spirit:configGroups="0 NoDisplay">clk_out6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_PORT" spirit:order="50" spirit:configGroups="0 NoDisplay">clk_out7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DADDR_PORT" spirit:order="51" spirit:configGroups="0 NoDisplay">daddr</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DCLK_PORT" spirit:order="52" spirit:configGroups="0 NoDisplay">dclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DRDY_PORT" spirit:order="53" spirit:configGroups="0 NoDisplay">drdy</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DWE_PORT" spirit:order="54" spirit:configGroups="0 NoDisplay">dwe</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_PORT" spirit:order="55" spirit:configGroups="0 NoDisplay">din</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_PORT" spirit:order="56" spirit:configGroups="0 NoDisplay">dout</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DEN_PORT" spirit:order="57" spirit:configGroups="0 NoDisplay">den</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSCLK_PORT" spirit:order="58" spirit:configGroups="0 NoDisplay">psclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSEN_PORT" spirit:order="59" spirit:configGroups="0 NoDisplay">psen</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSINCDEC_PORT" spirit:order="60" spirit:configGroups="0 NoDisplay">psincdec</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSDONE_PORT" spirit:order="61" spirit:configGroups="0 NoDisplay">psdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="62" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" spirit:order="63" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="64" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">200.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE" spirit:order="66" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="67" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="68" spirit:configGroups="0 NoDisplay">12.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE" spirit:order="69" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="70" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="71" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" spirit:order="72" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="73" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="74" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE" spirit:order="75" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="76" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="77" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE" spirit:order="78" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="79" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="80" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE" spirit:order="81" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="82" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MAX_I_JITTER" spirit:order="83" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="86" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="87" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="88" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="89" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="90" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="91" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="92" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FEEDBACK_SOURCE" spirit:choiceRef="choice_pairs_15c806d5" spirit:order="93" spirit:configGroups="0 NoDisplay">FDBK_AUTO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_SIGNALING" spirit:choiceRef="choice_pairs_3c2d3ec7" spirit:order="94" spirit:configGroups="0 NoDisplay">SINGLE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_PORT" spirit:order="95" spirit:configGroups="0 NoDisplay">clkfb_in</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_P_PORT" spirit:order="96" spirit:configGroups="0 NoDisplay">clkfb_in_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_N_PORT" spirit:order="97" spirit:configGroups="0 NoDisplay">clkfb_in_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_PORT" spirit:order="98" spirit:configGroups="0 NoDisplay">clkfb_out</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_P_PORT" spirit:order="99" spirit:configGroups="0 NoDisplay">clkfb_out_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_N_PORT" spirit:order="100" spirit:configGroups="0 NoDisplay">clkfb_out_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLATFORM" spirit:order="101" spirit:configGroups="0 NoDisplay">UNKNOWN</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUMMARY_STRINGS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SUMMARY_STRINGS" spirit:order="102" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_LOCKED" spirit:order="103" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CALC_DONE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CALC_DONE" spirit:order="104" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_RESET</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_RESET" spirit:order="105" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_POWER_DOWN" spirit:order="106" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_STATUS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_STATUS" spirit:order="107" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREEZE" spirit:order="108" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLK_VALID" spirit:order="109" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_STOPPED" spirit:order="110" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLKFB_STOPPED" spirit:order="111" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_PORT" spirit:order="409" spirit:configGroups="0 NoDisplay">reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCKED_PORT" spirit:order="113" spirit:configGroups="0 NoDisplay">locked</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POWER_DOWN_PORT" spirit:order="114" spirit:configGroups="0 NoDisplay">power_down</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_VALID_PORT" spirit:order="115" spirit:configGroups="0 NoDisplay">CLK_VALID</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STATUS_PORT" spirit:order="116" spirit:configGroups="0 NoDisplay">STATUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN_SEL_PORT" spirit:order="117" spirit:configGroups="0 NoDisplay">clk_in_sel</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" spirit:order="118" spirit:configGroups="0 NoDisplay">input_clk_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_STOPPED_PORT" spirit:order="119" spirit:configGroups="0 NoDisplay">clkfb_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MODE" spirit:choiceRef="choice_pairs_f4e10086" spirit:order="120" spirit:configGroups="0 NoDisplay">CENTER_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_FREQ" spirit:order="121" spirit:configGroups="0 NoDisplay">250</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_TIME" spirit:order="121.001" spirit:configGroups="0 NoDisplay">0.004</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_MMCM" spirit:order="122" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_NOTES" spirit:order="123" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="106" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="125" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" spirit:order="126" spirit:configGroups="0 NoDisplay">6.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_PHASE" spirit:order="127" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="128" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN1_PERIOD" spirit:order="129" spirit:configGroups="0 NoDisplay">10.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN2_PERIOD" spirit:order="130" spirit:configGroups="0 NoDisplay">10.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_CASCADE" spirit:order="131" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLOCK_HOLD" spirit:order="132" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_COMPENSATION" spirit:choiceRef="choice_pairs_502d9f23" spirit:order="133" spirit:configGroups="0 NoDisplay">ZHOLD</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER1" spirit:order="134" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER2" spirit:order="135" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_STARTUP_WAIT" spirit:order="136" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" spirit:order="137" spirit:configGroups="0 NoDisplay">6.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="138" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_PHASE" spirit:order="139" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS" spirit:order="140" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="142" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_PHASE" spirit:order="143" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS" spirit:order="144" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="146" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_PHASE" spirit:order="147" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS" spirit:order="148" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">12</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="150" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_PHASE" spirit:order="151" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS" spirit:order="152" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="154" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_PHASE" spirit:order="155" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS" spirit:order="156" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="158" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_PHASE" spirit:order="159" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS" spirit:order="160" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="162" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_PHASE" spirit:order="163" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS" spirit:order="164" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_PLL" spirit:order="165" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_NOTES" spirit:order="166" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="167" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_MULT" spirit:order="168" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_PHASE" spirit:order="169" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLK_FEEDBACK" spirit:choiceRef="choice_list_b9d38208" spirit:order="170" spirit:configGroups="0 NoDisplay">CLKFBOUT</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_DIVCLK_DIVIDE" spirit:order="171" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="52" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKIN_PERIOD" spirit:order="172" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_COMPENSATION" spirit:choiceRef="choice_pairs_035ca1c3" spirit:order="173" spirit:configGroups="0 NoDisplay">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_REF_JITTER" spirit:order="174" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DIVIDE" spirit:order="175" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE" spirit:order="176" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_PHASE" spirit:order="177" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DIVIDE" spirit:order="178" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE" spirit:order="179" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_PHASE" spirit:order="180" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DIVIDE" spirit:order="181" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE" spirit:order="182" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_PHASE" spirit:order="183" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DIVIDE" spirit:order="184" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE" spirit:order="185" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_PHASE" spirit:order="186" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DIVIDE" spirit:order="187" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE" spirit:order="188" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_PHASE" spirit:order="189" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DIVIDE" spirit:order="190" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE" spirit:order="191" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_PHASE" spirit:order="192" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_TYPE</spirit:name>
+ <spirit:displayName>Reset Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_TYPE" spirit:choiceRef="choice_pairs_a4fbc00c" spirit:order="408" spirit:configGroups="0 NoDisplay">ACTIVE_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" spirit:order="85.5" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLOCK_SEQUENCING" spirit:order="501" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER" spirit:order="502" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER" spirit:order="503" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER" spirit:order="504" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER" spirit:order="505" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER" spirit:order="506" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER" spirit:order="507" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER" spirit:order="508" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_BOARD_FLOW</spirit:name>
+ <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.8">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.9">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.1">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CDDC</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CDDC" spirit:order="509">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCDONE_PORT" spirit:order="510" spirit:configGroups="0 NoDisplay">cddcdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCREQ_PORT" spirit:order="511" spirit:configGroups="0 NoDisplay">cddcreq</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLKOUTPHY" spirit:order="123.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUTPHY_REQUESTED_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ" spirit:order="123.2" spirit:configGroups="0 NoDisplay">600.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_JITTER</spirit:name>
+ <spirit:displayName>Clkout1 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_JITTER" spirit:order="1000">151.366</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout1 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_PHASE_ERROR" spirit:order="1001">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_JITTER</spirit:name>
+ <spirit:displayName>Clkout2 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">132.221</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout2 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_PHASE_ERROR" spirit:order="1003">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_JITTER</spirit:name>
+ <spirit:displayName>Clkout3 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_JITTER" spirit:order="1004">231.952</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout3 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_PHASE_ERROR" spirit:order="1005">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_JITTER</spirit:name>
+ <spirit:displayName>Clkout4 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_JITTER" spirit:order="1006">174.353</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout4 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_PHASE_ERROR" spirit:order="1007">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_JITTER</spirit:name>
+ <spirit:displayName>Clkout5 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_JITTER" spirit:order="1008">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout5 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_PHASE_ERROR" spirit:order="1009">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_JITTER</spirit:name>
+ <spirit:displayName>Clkout6 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_JITTER" spirit:order="1010">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout6 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_PHASE_ERROR" spirit:order="1011">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_JITTER</spirit:name>
+ <spirit:displayName>Clkout7 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_JITTER" spirit:order="1012">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout7 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_PHASE_ERROR" spirit:order="1013">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="14.4">frequency</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE_DUTY_CONFIG</spirit:name>
+ <spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PHASE_DUTY_CONFIG">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>Clocking Wizard</xilinx:displayName>
+ <xilinx:coreRevision>0</xilinx:coreRevision>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2015.3</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="69bff2c8"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3a523104"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="a5d35bf6"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="18e8d175"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="09870f83"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_board.xdc b/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
new file mode 100644
index 0000000..3422a8e
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
new file mode 100644
index 0000000..e47643a
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
@@ -0,0 +1,215 @@
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+// CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+// CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+// CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+module clk_wiz_0_clk_wiz
+ (// Clock in ports
+ input clk_in1,
+ // Clock out ports
+ output clk_out1,
+ output clk_out2,
+ output clk_out3,
+ output clk_out4,
+ // Status and control signals
+ input reset,
+ output locked
+ );
+
+ // Input buffering
+ //------------------------------------
+ IBUF clkin1_ibufg
+ (.O (clk_in1_clk_wiz_0),
+ .I (clk_in1));
+
+
+
+ // Clocking PRIMITIVE
+ //------------------------------------
+
+ // Instantiation of the MMCM PRIMITIVE
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire [15:0] do_unused;
+ wire drdy_unused;
+ wire psdone_unused;
+ wire locked_int;
+ wire clkfbout_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfboutb_unused;
+ wire clkout0b_unused;
+ wire clkout1b_unused;
+ wire clkout2b_unused;
+ wire clkout3b_unused;
+ wire clkout4_unused;
+ wire clkout5_unused;
+ wire clkout6_unused;
+ wire clkfbstopped_unused;
+ wire clkinstopped_unused;
+ wire reset_high;
+
+ MMCME2_ADV
+ #(.BANDWIDTH ("OPTIMIZED"),
+ .CLKOUT4_CASCADE ("FALSE"),
+ .COMPENSATION ("ZHOLD"),
+ .STARTUP_WAIT ("FALSE"),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT_F (6.000),
+ .CLKFBOUT_PHASE (0.000),
+ .CLKFBOUT_USE_FINE_PS ("FALSE"),
+ .CLKOUT0_DIVIDE_F (6.000),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT0_USE_FINE_PS ("FALSE"),
+ .CLKOUT1_DIVIDE (3),
+ .CLKOUT1_PHASE (0.000),
+ .CLKOUT1_DUTY_CYCLE (0.500),
+ .CLKOUT1_USE_FINE_PS ("FALSE"),
+ .CLKOUT2_DIVIDE (50),
+ .CLKOUT2_PHASE (0.000),
+ .CLKOUT2_DUTY_CYCLE (0.500),
+ .CLKOUT2_USE_FINE_PS ("FALSE"),
+ .CLKOUT3_DIVIDE (12),
+ .CLKOUT3_PHASE (0.000),
+ .CLKOUT3_DUTY_CYCLE (0.500),
+ .CLKOUT3_USE_FINE_PS ("FALSE"),
+ .CLKIN1_PERIOD (10.0))
+ mmcm_adv_inst
+ // Output clocks
+ (
+ .CLKFBOUT (clkfbout_clk_wiz_0),
+ .CLKFBOUTB (clkfboutb_unused),
+ .CLKOUT0 (clk_out1_clk_wiz_0),
+ .CLKOUT0B (clkout0b_unused),
+ .CLKOUT1 (clk_out2_clk_wiz_0),
+ .CLKOUT1B (clkout1b_unused),
+ .CLKOUT2 (clk_out3_clk_wiz_0),
+ .CLKOUT2B (clkout2b_unused),
+ .CLKOUT3 (clk_out4_clk_wiz_0),
+ .CLKOUT3B (clkout3b_unused),
+ .CLKOUT4 (clkout4_unused),
+ .CLKOUT5 (clkout5_unused),
+ .CLKOUT6 (clkout6_unused),
+ // Input clock control
+ .CLKFBIN (clkfbout_buf_clk_wiz_0),
+ .CLKIN1 (clk_in1_clk_wiz_0),
+ .CLKIN2 (1'b0),
+ // Tied to always select the primary input clock
+ .CLKINSEL (1'b1),
+ // Ports for dynamic reconfiguration
+ .DADDR (7'h0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'h0),
+ .DO (do_unused),
+ .DRDY (drdy_unused),
+ .DWE (1'b0),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (psdone_unused),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .CLKINSTOPPED (clkinstopped_unused),
+ .CLKFBSTOPPED (clkfbstopped_unused),
+ .PWRDWN (1'b0),
+ .RST (reset_high));
+
+ assign reset_high = reset;
+
+ assign locked = locked_int;
+
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkf_buf
+ (.O (clkfbout_buf_clk_wiz_0),
+ .I (clkfbout_clk_wiz_0));
+
+
+
+ BUFG clkout1_buf
+ (.O (clk_out1),
+ .I (clk_out1_clk_wiz_0));
+
+
+ BUFG clkout2_buf
+ (.O (clk_out2),
+ .I (clk_out2_clk_wiz_0));
+
+ BUFG clkout3_buf
+ (.O (clk_out3),
+ .I (clk_out3_clk_wiz_0));
+
+ BUFG clkout4_buf
+ (.O (clk_out4),
+ .I (clk_out4_clk_wiz_0));
+
+
+
+endmodule
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
new file mode 100644
index 0000000..41c79d7
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
@@ -0,0 +1,56 @@
+# file: clk_wiz_0_ooc.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints #
+############################################################
+#create_clock -period 10.0 [get_ports clk_in1]
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
new file mode 100644
index 0000000..e0a8184
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
@@ -0,0 +1,278 @@
+// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+// Date : Thu Jan 21 17:13:26 2016
+// Host : WK86 running 64-bit Service Pack 1 (build 7601)
+// Command : write_verilog -force -mode funcsim C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+// Design : clk_wiz_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+(* NotValidForBitStream *)
+module clk_wiz_0
+ (clk_in1,
+ clk_out1,
+ clk_out2,
+ clk_out3,
+ clk_out4,
+ reset,
+ locked);
+ input clk_in1;
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire clk_out2;
+ wire clk_out3;
+ wire clk_out4;
+ wire locked;
+ wire reset;
+
+ clk_wiz_0_clk_wiz_0_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .clk_out2(clk_out2),
+ .clk_out3(clk_out3),
+ .clk_out4(clk_out4),
+ .locked(locked),
+ .reset(reset));
+endmodule
+
+(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
+module clk_wiz_0_clk_wiz_0_clk_wiz
+ (clk_in1,
+ clk_out1,
+ clk_out2,
+ clk_out3,
+ clk_out4,
+ reset,
+ locked);
+ input clk_in1;
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+
+ wire clk_in1;
+ wire clk_in1_clk_wiz_0;
+ wire clk_out1;
+ wire clk_out1_clk_wiz_0;
+ wire clk_out2;
+ wire clk_out2_clk_wiz_0;
+ wire clk_out3;
+ wire clk_out3_clk_wiz_0;
+ wire clk_out4;
+ wire clk_out4_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfbout_clk_wiz_0;
+ wire locked;
+ wire reset;
+ wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+ wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_clk_wiz_0),
+ .O(clkfbout_buf_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_clk_wiz_0),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout2_buf
+ (.I(clk_out2_clk_wiz_0),
+ .O(clk_out2));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout3_buf
+ (.I(clk_out3_clk_wiz_0),
+ .O(clk_out3));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout4_buf
+ (.I(clk_out4_clk_wiz_0),
+ .O(clk_out4));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ MMCME2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(6.000000),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKFBOUT_USE_FINE_PS("FALSE"),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE_F(6.000000),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT0_USE_FINE_PS("FALSE"),
+ .CLKOUT1_DIVIDE(3),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT1_USE_FINE_PS("FALSE"),
+ .CLKOUT2_DIVIDE(50),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT2_USE_FINE_PS("FALSE"),
+ .CLKOUT3_DIVIDE(12),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT3_USE_FINE_PS("FALSE"),
+ .CLKOUT4_CASCADE("FALSE"),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT4_USE_FINE_PS("FALSE"),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .CLKOUT5_USE_FINE_PS("FALSE"),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.500000),
+ .CLKOUT6_PHASE(0.000000),
+ .CLKOUT6_USE_FINE_PS("FALSE"),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PSEN_INVERTED(1'b0),
+ .IS_PSINCDEC_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .SS_EN("FALSE"),
+ .SS_MODE("CENTER_HIGH"),
+ .SS_MOD_PERIOD(10000),
+ .STARTUP_WAIT("FALSE"))
+ mmcm_adv_inst
+ (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+ .CLKFBOUT(clkfbout_clk_wiz_0),
+ .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+ .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+ .CLKIN1(clk_in1_clk_wiz_0),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+ .CLKOUT0(clk_out1_clk_wiz_0),
+ .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+ .CLKOUT1(clk_out2_clk_wiz_0),
+ .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+ .CLKOUT2(clk_out3_clk_wiz_0),
+ .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+ .CLKOUT3(clk_out4_clk_wiz_0),
+ .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+ .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+ .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(locked),
+ .PSCLK(1'b0),
+ .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .PWRDWN(1'b0),
+ .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
new file mode 100644
index 0000000..84ae83d
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
@@ -0,0 +1,218 @@
+-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+-- Date : Thu Jan 21 17:13:26 2016
+-- Host : WK86 running 64-bit Service Pack 1 (build 7601)
+-- Command : write_vhdl -force -mode funcsim C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+-- Design : clk_wiz_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0_clk_wiz_0_clk_wiz is
+ port (
+ clk_in1 : in STD_LOGIC;
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
+end clk_wiz_0_clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
+ signal clk_in1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out2_clk_wiz_0 : STD_LOGIC;
+ signal clk_out3_clk_wiz_0 : STD_LOGIC;
+ signal clk_out4_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_clk_wiz_0 : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_clk_wiz_0,
+ O => clkfbout_buf_clk_wiz_0
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_clk_wiz_0
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_clk_wiz_0,
+ O => clk_out1
+ );
+clkout2_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out2_clk_wiz_0,
+ O => clk_out2
+ );
+clkout3_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out3_clk_wiz_0,
+ O => clk_out3
+ );
+clkout4_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out4_clk_wiz_0,
+ O => clk_out4
+ );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 6.000000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => false,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 6.000000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => false,
+ CLKOUT1_DIVIDE => 3,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => false,
+ CLKOUT2_DIVIDE => 50,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => false,
+ CLKOUT3_DIVIDE => 12,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => false,
+ CLKOUT4_CASCADE => false,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => false,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => false,
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => false,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => false
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_clk_wiz_0,
+ CLKFBOUT => clkfbout_clk_wiz_0,
+ CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1_clk_wiz_0,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_clk_wiz_0,
+ CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => clk_out2_clk_wiz_0,
+ CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => clk_out3_clk_wiz_0,
+ CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => clk_out4_clk_wiz_0,
+ CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PSCLK => '0',
+ PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => reset
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0 is
+ port (
+ clk_in1 : in STD_LOGIC;
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of clk_wiz_0 : entity is true;
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
+end clk_wiz_0;
+
+architecture STRUCTURE of clk_wiz_0 is
+begin
+inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ locked => locked,
+ reset => reset
+ );
+end STRUCTURE;
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_stub.v b/src/ip/clk_wiz_0/clk_wiz_0_stub.v
new file mode 100644
index 0000000..3e730b7
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -0,0 +1,24 @@
+// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+// Date : Thu Jan 21 17:13:26 2016
+// Host : WK86 running 64-bit Service Pack 1 (build 7601)
+// Command : write_verilog -force -mode synth_stub C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_in1, clk_out1, clk_out2, clk_out3, clk_out4, reset, locked)
+/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,clk_out2,clk_out3,clk_out4,reset,locked" */;
+ input clk_in1;
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+endmodule
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
new file mode 100644
index 0000000..262c691
--- /dev/null
+++ b/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -0,0 +1,33 @@
+-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+-- Date : Thu Jan 21 17:13:26 2016
+-- Host : WK86 running 64-bit Service Pack 1 (build 7601)
+-- Command : write_vhdl -force -mode synth_stub C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+ Port (
+ clk_in1 : in STD_LOGIC;
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC
+ );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,clk_out2,clk_out3,clk_out4,reset,locked";
+begin
+end;
diff --git a/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt b/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
new file mode 100644
index 0000000..c88739c
--- /dev/null
+++ b/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
@@ -0,0 +1,115 @@
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
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