diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 0e66b1c831e7f48694944d4399497af39a1879b1..042a2316afd758e8841ee2aa8aed58246e0d8e1c 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -2,25 +2,39 @@
## Diagramme de la FSM
-
+
## Questions
### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
-Il y a
+Le code utilise deux processus distincts : un processus synchrone, déclenché par le signal d'horloge I_clock et le reset asynchrone I_reset, qui met à jour l’état courant avec l’état suivant (SR_nextState et SR_currentState sur la machine). Ce processus implémente le registre d’état de la machine. L’autre processus est combinatoire et calcule SR_nextState en fonction de l’état actuel et des entrées (I_inputSampleValid et I_processingDone) ; il décrit la logique de transition entre états.
+ On différencie ces processus par leurs sensibilités : le premier réagit à l’horloge (car il stocke un état), tandis que le second ne dépend que des entrées logiques (car il calcule l’évolution sans mémoire explicite).
+
### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
+Oui, la simulation permet de valider la description VHDL de l’unité de contrôle, car on observe la séquence de sortie du filtre, et on peut comparer les valeurs obtenues avec la séquence attendue (317, 476, 925, ...). On remarque que celles-ci sont identiques et cela confirme que l’unité de contrôle génère les bons signaux au bon moment pour piloter correctement le filtre séquentiel. La simulation est donc un outil clé pour vérifier le bon fonctionnement logique du système avant toute implémentation matérielle.
### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
+En testant notre code sur Xilinx Artix 7 FPGA, nous pouvons écouter différents sons fortement bruités puis leur appliquer notre filtre. La différence est flagrante et le son se voit nettement amélioré. Nous validons donc le design de l’unité de contrôle car celle-ci orchestre correctement les opérations internes du filtre.
### Question filtre 4 : Combien de processus sont utilisés et de quelles natures sont-ils ?
+On compte 4 processes dans le code OperativeUnit. On peut aussi expliciter leurs utilités:
+- Processus shift : qui implémente un registre à décalage pour les échantillons d'entrée. Il est séquentiel car il s’active sur front montant ou sur signal de reset. En cas de I_loadShift = '1', décale les valeurs et insère I_inputSample en tête.
-### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
+- processus incr_address : il gère les adresses de lecture pour les registres. Il est séquentiel car sensible à l’horloge et le reset. Il initialise ou charge la somme partielle selon les signaux de contrôle I_initSum et I_loadSum.
+
+- processus sum_acc : il somme les résultats de la multiplication. Il est séquentiel car sensible à l’horloge et le reset.
+
+- processus store_result : Stocke le résultat final de la convolution dans un registre. Il est séquentiel car sensible à l’horloge et le reset.Si I_loadOutput = '1', copie le contenu de SR_sum vers SR_filteredSample.
+
+
+### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
+La simulation valide partiellement la description VHDL du filtre d’un point de vue logique et calculatoire. Toutefois, l’usage de troncatures dans les calculs peut induire des erreurs numériques non négligeables, notamment une perte de précision ou un bruit de quantification accru. Cela peut compromettre la fidélité du filtre. Pour corriger cela, il conviendrait d’augmenter la précision des signaux intermédiaires ou d’utiliser un arrondi contrôlé. Une comparaison avec un modèle en virgule flottante (type MATLAB) peut aider à évaluer l’impact exact de ces troncatures.
### Question filtre 6 : Validez-vous la conception de l’unité opérative ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ?
diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index bd839a9b01be6c20eb7b6840fcbab9fd73e2336d..14f71d41b44c846f1e5766f7552c9137a952e7ac 100644
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+++ b/docs/img/FSM.drawio
@@ -1,52 +1,52 @@
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diff --git a/docs/img/FSM.png b/docs/img/FSM.png
deleted file mode 100644
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..0000000000000000000000000000000000000000
Binary files a/docs/img/FSM.png and /dev/null differ
diff --git a/src/hdl/operativeUnit.v b/src/hdl/operativeUnit.v
deleted file mode 100644
index 167baf65b9d519f5dfc3b2a0e004bb70af020cc2..0000000000000000000000000000000000000000
--- a/src/hdl/operativeUnit.v
+++ /dev/null
@@ -1,4199 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-// Date : Wed Apr 9 16:08:04 2025
-// Host : marzel-XPS-13-7390-2-in-1 running 64-bit Ubuntu 22.04.5 LTS
-// Command : write_verilog
-// /home/marzel/Documents/enseignements/IMTA_ELEC_A1S2_TAF/UE_EE/SAR_TA/Filtre_NexysVideo_PROF/proj/operativeUnit.v
-// Design : operativeUnit
-// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
-// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
-// design files.
-// Device : xc7a200tsbg484-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* STRUCTURAL_NETLIST = "yes" *)
-module operativeUnit
- (I_clock,
- I_reset,
- I_inputSample,
- I_loadShift,
- I_initAddress,
- I_incrAddress,
- I_initSum,
- I_loadSum,
- I_loadOutput,
- O_processingDone,
- O_filteredSample);
- input I_clock;
- input I_reset;
- input [15:0]I_inputSample;
- input I_loadShift;
- input I_initAddress;
- input I_incrAddress;
- input I_initSum;
- input I_loadSum;
- input I_loadOutput;
- output O_processingDone;
- output [15:0]O_filteredSample;
-
- wire \<const0> ;
- wire \<const1> ;
- wire GND_2;
- wire I_clock;
- wire I_clock_IBUF;
- wire I_clock_IBUF_BUFG;
- wire I_incrAddress;
- wire I_incrAddress_IBUF;
- wire I_initAddress;
- wire I_initAddress_IBUF;
- wire I_initSum;
- wire I_initSum_IBUF;
- wire [15:0]I_inputSample;
- wire [15:0]I_inputSample_IBUF;
- wire I_loadOutput;
- wire I_loadOutput_IBUF;
- wire I_loadShift;
- wire I_loadShift_IBUF;
- wire I_loadSum;
- wire I_loadSum_IBUF;
- wire I_reset;
- wire I_reset_IBUF;
- wire [30:15]L;
- wire [15:0]O_filteredSample;
- wire [15:0]O_filteredSample_OBUF;
- wire O_processingDone;
- wire O_processingDone_OBUF;
- wire SC_addResult_i_100_n_0;
- wire SC_addResult_i_101_n_0;
- wire SC_addResult_i_102_n_0;
- wire SC_addResult_i_103_n_0;
- wire SC_addResult_i_104_n_0;
- wire SC_addResult_i_105_n_0;
- wire SC_addResult_i_106_n_0;
- wire SC_addResult_i_107_n_0;
- wire SC_addResult_i_108_n_0;
- wire SC_addResult_i_109_n_0;
- wire SC_addResult_i_110_n_0;
- wire SC_addResult_i_111_n_0;
- wire SC_addResult_i_112_n_0;
- wire SC_addResult_i_113_n_0;
- wire SC_addResult_i_114_n_0;
- wire SC_addResult_i_115_n_0;
- wire SC_addResult_i_116_n_0;
- wire SC_addResult_i_117_n_0;
- wire SC_addResult_i_118_n_0;
- wire SC_addResult_i_119_n_0;
- wire SC_addResult_i_120_n_0;
- wire SC_addResult_i_121_n_0;
- wire SC_addResult_i_122_n_0;
- wire SC_addResult_i_123_n_0;
- wire SC_addResult_i_124_n_0;
- wire SC_addResult_i_29_n_0;
- wire SC_addResult_i_30_n_0;
- wire SC_addResult_i_31_n_0;
- wire SC_addResult_i_32_n_0;
- wire SC_addResult_i_33_n_0;
- wire SC_addResult_i_34_n_0;
- wire SC_addResult_i_35_n_0;
- wire SC_addResult_i_36_n_0;
- wire SC_addResult_i_37_n_0;
- wire SC_addResult_i_38_n_0;
- wire SC_addResult_i_39_n_0;
- wire SC_addResult_i_40_n_0;
- wire SC_addResult_i_41_n_0;
- wire SC_addResult_i_42_n_0;
- wire SC_addResult_i_43_n_0;
- wire SC_addResult_i_44_n_0;
- wire SC_addResult_i_45_n_0;
- wire SC_addResult_i_46_n_0;
- wire SC_addResult_i_47_n_0;
- wire SC_addResult_i_48_n_0;
- wire SC_addResult_i_49_n_0;
- wire SC_addResult_i_50_n_0;
- wire SC_addResult_i_51_n_0;
- wire SC_addResult_i_52_n_0;
- wire SC_addResult_i_53_n_0;
- wire SC_addResult_i_54_n_0;
- wire SC_addResult_i_55_n_0;
- wire SC_addResult_i_56_n_0;
- wire SC_addResult_i_57_n_0;
- wire SC_addResult_i_58_n_0;
- wire SC_addResult_i_59_n_0;
- wire SC_addResult_i_60_n_0;
- wire SC_addResult_i_61_n_0;
- wire SC_addResult_i_62_n_0;
- wire SC_addResult_i_63_n_0;
- wire SC_addResult_i_64_n_0;
- wire SC_addResult_i_65_n_0;
- wire SC_addResult_i_66_n_0;
- wire SC_addResult_i_67_n_0;
- wire SC_addResult_i_68_n_0;
- wire SC_addResult_i_69_n_0;
- wire SC_addResult_i_70_n_0;
- wire SC_addResult_i_71_n_0;
- wire SC_addResult_i_72_n_0;
- wire SC_addResult_i_73_n_0;
- wire SC_addResult_i_74_n_0;
- wire SC_addResult_i_75_n_0;
- wire SC_addResult_i_76_n_0;
- wire SC_addResult_i_77_n_0;
- wire SC_addResult_i_78_n_0;
- wire SC_addResult_i_79_n_0;
- wire SC_addResult_i_80_n_0;
- wire SC_addResult_i_81_n_0;
- wire SC_addResult_i_82_n_0;
- wire SC_addResult_i_83_n_0;
- wire SC_addResult_i_84_n_0;
- wire SC_addResult_i_85_n_0;
- wire SC_addResult_i_86_n_0;
- wire SC_addResult_i_87_n_0;
- wire SC_addResult_i_88_n_0;
- wire SC_addResult_i_89_n_0;
- wire SC_addResult_i_90_n_0;
- wire SC_addResult_i_91_n_0;
- wire SC_addResult_i_92_n_0;
- wire SC_addResult_i_93_n_0;
- wire SC_addResult_i_94_n_0;
- wire SC_addResult_i_95_n_0;
- wire SC_addResult_i_96_n_0;
- wire SC_addResult_i_97_n_0;
- wire SC_addResult_i_98_n_0;
- wire SC_addResult_i_99_n_0;
- wire SC_addResult_n_100;
- wire SC_addResult_n_101;
- wire SC_addResult_n_102;
- wire SC_addResult_n_103;
- wire SC_addResult_n_104;
- wire SC_addResult_n_105;
- wire SC_addResult_n_70;
- wire SC_addResult_n_71;
- wire SC_addResult_n_72;
- wire SC_addResult_n_73;
- wire SC_addResult_n_74;
- wire SC_addResult_n_91;
- wire SC_addResult_n_92;
- wire SC_addResult_n_93;
- wire SC_addResult_n_94;
- wire SC_addResult_n_95;
- wire SC_addResult_n_96;
- wire SC_addResult_n_97;
- wire SC_addResult_n_98;
- wire SC_addResult_n_99;
- wire [11:0]SC_multOperand2;
- wire \SR_filteredSample[3]_i_2_n_0 ;
- wire \SR_filteredSample_reg[11]_i_1_n_0 ;
- wire \SR_filteredSample_reg[11]_i_1_n_1 ;
- wire \SR_filteredSample_reg[11]_i_1_n_2 ;
- wire \SR_filteredSample_reg[11]_i_1_n_3 ;
- wire \SR_filteredSample_reg[15]_i_1_n_1 ;
- wire \SR_filteredSample_reg[15]_i_1_n_2 ;
- wire \SR_filteredSample_reg[15]_i_1_n_3 ;
- wire \SR_filteredSample_reg[3]_i_1_n_0 ;
- wire \SR_filteredSample_reg[3]_i_1_n_1 ;
- wire \SR_filteredSample_reg[3]_i_1_n_2 ;
- wire \SR_filteredSample_reg[3]_i_1_n_3 ;
- wire \SR_filteredSample_reg[7]_i_1_n_0 ;
- wire \SR_filteredSample_reg[7]_i_1_n_1 ;
- wire \SR_filteredSample_reg[7]_i_1_n_2 ;
- wire \SR_filteredSample_reg[7]_i_1_n_3 ;
- wire [3:0]SR_readAddress;
- wire \SR_readAddress[0]_i_1_n_0 ;
- wire \SR_readAddress[1]_i_1_n_0 ;
- wire \SR_readAddress[2]_i_1_n_0 ;
- wire \SR_readAddress[3]_i_1_n_0 ;
- wire \SR_readAddress[3]_i_2_n_0 ;
- wire [15:0]\SR_shiftRegister[0] ;
- wire [15:0]\SR_shiftRegister_reg[0] ;
- wire [15:0]\SR_shiftRegister_reg[10] ;
- wire [15:0]\SR_shiftRegister_reg[11] ;
- wire [15:0]\SR_shiftRegister_reg[12] ;
- wire [15:0]\SR_shiftRegister_reg[13] ;
- wire [15:0]\SR_shiftRegister_reg[14] ;
- wire [15:0]\SR_shiftRegister_reg[15] ;
- wire [15:0]\SR_shiftRegister_reg[1] ;
- wire [15:0]\SR_shiftRegister_reg[2] ;
- wire [15:0]\SR_shiftRegister_reg[3] ;
- wire [15:0]\SR_shiftRegister_reg[4] ;
- wire [15:0]\SR_shiftRegister_reg[5] ;
- wire [15:0]\SR_shiftRegister_reg[6] ;
- wire [15:0]\SR_shiftRegister_reg[7] ;
- wire [15:0]\SR_shiftRegister_reg[8] ;
- wire [15:0]\SR_shiftRegister_reg[9] ;
- wire [35:0]SR_sum;
- wire \SR_sum[35]_i_1_n_0 ;
- wire [15:0]p_0_in;
- wire [35:0]p_1_in;
-
- GND GND
- (.G(\<const0> ));
- GND GND_1
- (.G(GND_2));
- BUFG I_clock_IBUF_BUFG_inst
- (.I(I_clock_IBUF),
- .O(I_clock_IBUF_BUFG));
- IBUF I_clock_IBUF_inst
- (.I(I_clock),
- .O(I_clock_IBUF));
- IBUF I_incrAddress_IBUF_inst
- (.I(I_incrAddress),
- .O(I_incrAddress_IBUF));
- IBUF I_initAddress_IBUF_inst
- (.I(I_initAddress),
- .O(I_initAddress_IBUF));
- IBUF I_initSum_IBUF_inst
- (.I(I_initSum),
- .O(I_initSum_IBUF));
- IBUF \I_inputSample_IBUF[0]_inst
- (.I(I_inputSample[0]),
- .O(I_inputSample_IBUF[0]));
- IBUF \I_inputSample_IBUF[10]_inst
- (.I(I_inputSample[10]),
- .O(I_inputSample_IBUF[10]));
- IBUF \I_inputSample_IBUF[11]_inst
- (.I(I_inputSample[11]),
- .O(I_inputSample_IBUF[11]));
- IBUF \I_inputSample_IBUF[12]_inst
- (.I(I_inputSample[12]),
- .O(I_inputSample_IBUF[12]));
- IBUF \I_inputSample_IBUF[13]_inst
- (.I(I_inputSample[13]),
- .O(I_inputSample_IBUF[13]));
- IBUF \I_inputSample_IBUF[14]_inst
- (.I(I_inputSample[14]),
- .O(I_inputSample_IBUF[14]));
- IBUF \I_inputSample_IBUF[15]_inst
- (.I(I_inputSample[15]),
- .O(I_inputSample_IBUF[15]));
- IBUF \I_inputSample_IBUF[1]_inst
- (.I(I_inputSample[1]),
- .O(I_inputSample_IBUF[1]));
- IBUF \I_inputSample_IBUF[2]_inst
- (.I(I_inputSample[2]),
- .O(I_inputSample_IBUF[2]));
- IBUF \I_inputSample_IBUF[3]_inst
- (.I(I_inputSample[3]),
- .O(I_inputSample_IBUF[3]));
- IBUF \I_inputSample_IBUF[4]_inst
- (.I(I_inputSample[4]),
- .O(I_inputSample_IBUF[4]));
- IBUF \I_inputSample_IBUF[5]_inst
- (.I(I_inputSample[5]),
- .O(I_inputSample_IBUF[5]));
- IBUF \I_inputSample_IBUF[6]_inst
- (.I(I_inputSample[6]),
- .O(I_inputSample_IBUF[6]));
- IBUF \I_inputSample_IBUF[7]_inst
- (.I(I_inputSample[7]),
- .O(I_inputSample_IBUF[7]));
- IBUF \I_inputSample_IBUF[8]_inst
- (.I(I_inputSample[8]),
- .O(I_inputSample_IBUF[8]));
- IBUF \I_inputSample_IBUF[9]_inst
- (.I(I_inputSample[9]),
- .O(I_inputSample_IBUF[9]));
- IBUF I_loadOutput_IBUF_inst
- (.I(I_loadOutput),
- .O(I_loadOutput_IBUF));
- IBUF I_loadShift_IBUF_inst
- (.I(I_loadShift),
- .O(I_loadShift_IBUF));
- IBUF I_loadSum_IBUF_inst
- (.I(I_loadSum),
- .O(I_loadSum_IBUF));
- IBUF I_reset_IBUF_inst
- (.I(I_reset),
- .O(I_reset_IBUF));
- OBUF \O_filteredSample_OBUF[0]_inst
- (.I(O_filteredSample_OBUF[0]),
- .O(O_filteredSample[0]));
- OBUF \O_filteredSample_OBUF[10]_inst
- (.I(O_filteredSample_OBUF[10]),
- .O(O_filteredSample[10]));
- OBUF \O_filteredSample_OBUF[11]_inst
- (.I(O_filteredSample_OBUF[11]),
- .O(O_filteredSample[11]));
- OBUF \O_filteredSample_OBUF[12]_inst
- (.I(O_filteredSample_OBUF[12]),
- .O(O_filteredSample[12]));
- OBUF \O_filteredSample_OBUF[13]_inst
- (.I(O_filteredSample_OBUF[13]),
- .O(O_filteredSample[13]));
- OBUF \O_filteredSample_OBUF[14]_inst
- (.I(O_filteredSample_OBUF[14]),
- .O(O_filteredSample[14]));
- OBUF \O_filteredSample_OBUF[15]_inst
- (.I(O_filteredSample_OBUF[15]),
- .O(O_filteredSample[15]));
- OBUF \O_filteredSample_OBUF[1]_inst
- (.I(O_filteredSample_OBUF[1]),
- .O(O_filteredSample[1]));
- OBUF \O_filteredSample_OBUF[2]_inst
- (.I(O_filteredSample_OBUF[2]),
- .O(O_filteredSample[2]));
- OBUF \O_filteredSample_OBUF[3]_inst
- (.I(O_filteredSample_OBUF[3]),
- .O(O_filteredSample[3]));
- OBUF \O_filteredSample_OBUF[4]_inst
- (.I(O_filteredSample_OBUF[4]),
- .O(O_filteredSample[4]));
- OBUF \O_filteredSample_OBUF[5]_inst
- (.I(O_filteredSample_OBUF[5]),
- .O(O_filteredSample[5]));
- OBUF \O_filteredSample_OBUF[6]_inst
- (.I(O_filteredSample_OBUF[6]),
- .O(O_filteredSample[6]));
- OBUF \O_filteredSample_OBUF[7]_inst
- (.I(O_filteredSample_OBUF[7]),
- .O(O_filteredSample[7]));
- OBUF \O_filteredSample_OBUF[8]_inst
- (.I(O_filteredSample_OBUF[8]),
- .O(O_filteredSample[8]));
- OBUF \O_filteredSample_OBUF[9]_inst
- (.I(O_filteredSample_OBUF[9]),
- .O(O_filteredSample[9]));
- OBUF O_processingDone_OBUF_inst
- (.I(O_processingDone_OBUF),
- .O(O_processingDone));
- LUT3 #(
- .INIT(8'h80))
- O_processingDone_OBUF_inst_i_1
- (.I0(SR_readAddress[1]),
- .I1(SR_readAddress[3]),
- .I2(SR_readAddress[2]),
- .O(O_processingDone_OBUF));
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(0),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(0),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(0),
- .BREG(0),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(0),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("MULTIPLY"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- SC_addResult
- (.A({\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] [15],\SR_shiftRegister[0] }),
- .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,SC_multOperand2}),
- .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .C({SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum[35],SR_sum}),
- .CARRYCASCIN(\<const0> ),
- .CARRYIN(\<const0> ),
- .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
- .CEA1(\<const0> ),
- .CEA2(\<const0> ),
- .CEAD(\<const0> ),
- .CEALUMODE(\<const0> ),
- .CEB1(\<const0> ),
- .CEB2(\<const0> ),
- .CEC(\<const0> ),
- .CECARRYIN(\<const0> ),
- .CECTRL(\<const0> ),
- .CED(\<const0> ),
- .CEINMODE(\<const0> ),
- .CEM(\<const0> ),
- .CEP(\<const0> ),
- .CLK(\<const0> ),
- .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
- .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .MULTSIGNIN(\<const0> ),
- .OPMODE({\<const0> ,\<const1> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
- .P({SC_addResult_n_70,SC_addResult_n_71,SC_addResult_n_72,SC_addResult_n_73,SC_addResult_n_74,L,SC_addResult_n_91,SC_addResult_n_92,SC_addResult_n_93,SC_addResult_n_94,SC_addResult_n_95,SC_addResult_n_96,SC_addResult_n_97,SC_addResult_n_98,SC_addResult_n_99,SC_addResult_n_100,SC_addResult_n_101,SC_addResult_n_102,SC_addResult_n_103,SC_addResult_n_104,SC_addResult_n_105}),
- .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .RSTA(\<const0> ),
- .RSTALLCARRYIN(\<const0> ),
- .RSTALUMODE(\<const0> ),
- .RSTB(\<const0> ),
- .RSTC(\<const0> ),
- .RSTCTRL(\<const0> ),
- .RSTD(\<const0> ),
- .RSTINMODE(\<const0> ),
- .RSTM(\<const0> ),
- .RSTP(\<const0> ));
- LUT2 #(
- .INIT(4'h6))
- SC_addResult_i_1
- (.I0(SR_readAddress[2]),
- .I1(SR_readAddress[3]),
- .O(SC_multOperand2[11]));
- LUT4 #(
- .INIT(16'hBFFD))
- SC_addResult_i_10
- (.I0(SR_readAddress[2]),
- .I1(SR_readAddress[3]),
- .I2(SR_readAddress[1]),
- .I3(SR_readAddress[0]),
- .O(SC_multOperand2[2]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_100
- (.I0(\SR_shiftRegister_reg[15] [6]),
- .I1(\SR_shiftRegister_reg[14] [6]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [6]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [6]),
- .O(SC_addResult_i_100_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_101
- (.I0(\SR_shiftRegister_reg[3] [5]),
- .I1(\SR_shiftRegister_reg[2] [5]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [5]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [5]),
- .O(SC_addResult_i_101_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_102
- (.I0(\SR_shiftRegister_reg[7] [5]),
- .I1(\SR_shiftRegister_reg[6] [5]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [5]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [5]),
- .O(SC_addResult_i_102_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_103
- (.I0(\SR_shiftRegister_reg[11] [5]),
- .I1(\SR_shiftRegister_reg[10] [5]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [5]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [5]),
- .O(SC_addResult_i_103_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_104
- (.I0(\SR_shiftRegister_reg[15] [5]),
- .I1(\SR_shiftRegister_reg[14] [5]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [5]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [5]),
- .O(SC_addResult_i_104_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_105
- (.I0(\SR_shiftRegister_reg[3] [4]),
- .I1(\SR_shiftRegister_reg[2] [4]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [4]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [4]),
- .O(SC_addResult_i_105_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_106
- (.I0(\SR_shiftRegister_reg[7] [4]),
- .I1(\SR_shiftRegister_reg[6] [4]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [4]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [4]),
- .O(SC_addResult_i_106_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_107
- (.I0(\SR_shiftRegister_reg[11] [4]),
- .I1(\SR_shiftRegister_reg[10] [4]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [4]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [4]),
- .O(SC_addResult_i_107_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_108
- (.I0(\SR_shiftRegister_reg[15] [4]),
- .I1(\SR_shiftRegister_reg[14] [4]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [4]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [4]),
- .O(SC_addResult_i_108_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_109
- (.I0(\SR_shiftRegister_reg[3] [3]),
- .I1(\SR_shiftRegister_reg[2] [3]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [3]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [3]),
- .O(SC_addResult_i_109_n_0));
- LUT4 #(
- .INIT(16'h581A))
- SC_addResult_i_11
- (.I0(SR_readAddress[3]),
- .I1(SR_readAddress[1]),
- .I2(SR_readAddress[2]),
- .I3(SR_readAddress[0]),
- .O(SC_multOperand2[1]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_110
- (.I0(\SR_shiftRegister_reg[7] [3]),
- .I1(\SR_shiftRegister_reg[6] [3]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [3]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [3]),
- .O(SC_addResult_i_110_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_111
- (.I0(\SR_shiftRegister_reg[11] [3]),
- .I1(\SR_shiftRegister_reg[10] [3]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [3]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [3]),
- .O(SC_addResult_i_111_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_112
- (.I0(\SR_shiftRegister_reg[15] [3]),
- .I1(\SR_shiftRegister_reg[14] [3]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [3]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [3]),
- .O(SC_addResult_i_112_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_113
- (.I0(\SR_shiftRegister_reg[3] [2]),
- .I1(\SR_shiftRegister_reg[2] [2]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [2]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [2]),
- .O(SC_addResult_i_113_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_114
- (.I0(\SR_shiftRegister_reg[7] [2]),
- .I1(\SR_shiftRegister_reg[6] [2]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [2]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [2]),
- .O(SC_addResult_i_114_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_115
- (.I0(\SR_shiftRegister_reg[11] [2]),
- .I1(\SR_shiftRegister_reg[10] [2]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [2]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [2]),
- .O(SC_addResult_i_115_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_116
- (.I0(\SR_shiftRegister_reg[15] [2]),
- .I1(\SR_shiftRegister_reg[14] [2]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [2]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [2]),
- .O(SC_addResult_i_116_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_117
- (.I0(\SR_shiftRegister_reg[3] [1]),
- .I1(\SR_shiftRegister_reg[2] [1]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [1]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [1]),
- .O(SC_addResult_i_117_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_118
- (.I0(\SR_shiftRegister_reg[7] [1]),
- .I1(\SR_shiftRegister_reg[6] [1]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [1]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [1]),
- .O(SC_addResult_i_118_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_119
- (.I0(\SR_shiftRegister_reg[11] [1]),
- .I1(\SR_shiftRegister_reg[10] [1]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [1]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [1]),
- .O(SC_addResult_i_119_n_0));
- LUT4 #(
- .INIT(16'hF66F))
- SC_addResult_i_12
- (.I0(SR_readAddress[3]),
- .I1(SR_readAddress[1]),
- .I2(SR_readAddress[2]),
- .I3(SR_readAddress[0]),
- .O(SC_multOperand2[0]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_120
- (.I0(\SR_shiftRegister_reg[15] [1]),
- .I1(\SR_shiftRegister_reg[14] [1]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [1]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [1]),
- .O(SC_addResult_i_120_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_121
- (.I0(\SR_shiftRegister_reg[3] [0]),
- .I1(\SR_shiftRegister_reg[2] [0]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [0]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [0]),
- .O(SC_addResult_i_121_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_122
- (.I0(\SR_shiftRegister_reg[7] [0]),
- .I1(\SR_shiftRegister_reg[6] [0]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [0]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [0]),
- .O(SC_addResult_i_122_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_123
- (.I0(\SR_shiftRegister_reg[11] [0]),
- .I1(\SR_shiftRegister_reg[10] [0]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [0]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [0]),
- .O(SC_addResult_i_123_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_124
- (.I0(\SR_shiftRegister_reg[15] [0]),
- .I1(\SR_shiftRegister_reg[14] [0]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [0]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [0]),
- .O(SC_addResult_i_124_n_0));
- MUXF8 SC_addResult_i_13
- (.I0(SC_addResult_i_29_n_0),
- .I1(SC_addResult_i_30_n_0),
- .O(\SR_shiftRegister[0] [15]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_14
- (.I0(SC_addResult_i_31_n_0),
- .I1(SC_addResult_i_32_n_0),
- .O(\SR_shiftRegister[0] [14]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_15
- (.I0(SC_addResult_i_33_n_0),
- .I1(SC_addResult_i_34_n_0),
- .O(\SR_shiftRegister[0] [13]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_16
- (.I0(SC_addResult_i_35_n_0),
- .I1(SC_addResult_i_36_n_0),
- .O(\SR_shiftRegister[0] [12]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_17
- (.I0(SC_addResult_i_37_n_0),
- .I1(SC_addResult_i_38_n_0),
- .O(\SR_shiftRegister[0] [11]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_18
- (.I0(SC_addResult_i_39_n_0),
- .I1(SC_addResult_i_40_n_0),
- .O(\SR_shiftRegister[0] [10]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_19
- (.I0(SC_addResult_i_41_n_0),
- .I1(SC_addResult_i_42_n_0),
- .O(\SR_shiftRegister[0] [9]),
- .S(SR_readAddress[3]));
- LUT4 #(
- .INIT(16'h1E78))
- SC_addResult_i_2
- (.I0(SR_readAddress[2]),
- .I1(SR_readAddress[1]),
- .I2(SR_readAddress[3]),
- .I3(SR_readAddress[0]),
- .O(SC_multOperand2[10]));
- MUXF8 SC_addResult_i_20
- (.I0(SC_addResult_i_43_n_0),
- .I1(SC_addResult_i_44_n_0),
- .O(\SR_shiftRegister[0] [8]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_21
- (.I0(SC_addResult_i_45_n_0),
- .I1(SC_addResult_i_46_n_0),
- .O(\SR_shiftRegister[0] [7]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_22
- (.I0(SC_addResult_i_47_n_0),
- .I1(SC_addResult_i_48_n_0),
- .O(\SR_shiftRegister[0] [6]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_23
- (.I0(SC_addResult_i_49_n_0),
- .I1(SC_addResult_i_50_n_0),
- .O(\SR_shiftRegister[0] [5]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_24
- (.I0(SC_addResult_i_51_n_0),
- .I1(SC_addResult_i_52_n_0),
- .O(\SR_shiftRegister[0] [4]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_25
- (.I0(SC_addResult_i_53_n_0),
- .I1(SC_addResult_i_54_n_0),
- .O(\SR_shiftRegister[0] [3]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_26
- (.I0(SC_addResult_i_55_n_0),
- .I1(SC_addResult_i_56_n_0),
- .O(\SR_shiftRegister[0] [2]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_27
- (.I0(SC_addResult_i_57_n_0),
- .I1(SC_addResult_i_58_n_0),
- .O(\SR_shiftRegister[0] [1]),
- .S(SR_readAddress[3]));
- MUXF8 SC_addResult_i_28
- (.I0(SC_addResult_i_59_n_0),
- .I1(SC_addResult_i_60_n_0),
- .O(\SR_shiftRegister[0] [0]),
- .S(SR_readAddress[3]));
- MUXF7 SC_addResult_i_29
- (.I0(SC_addResult_i_61_n_0),
- .I1(SC_addResult_i_62_n_0),
- .O(SC_addResult_i_29_n_0),
- .S(SR_readAddress[2]));
- LUT2 #(
- .INIT(4'h6))
- SC_addResult_i_3
- (.I0(SR_readAddress[1]),
- .I1(SR_readAddress[3]),
- .O(SC_multOperand2[9]));
- MUXF7 SC_addResult_i_30
- (.I0(SC_addResult_i_63_n_0),
- .I1(SC_addResult_i_64_n_0),
- .O(SC_addResult_i_30_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_31
- (.I0(SC_addResult_i_65_n_0),
- .I1(SC_addResult_i_66_n_0),
- .O(SC_addResult_i_31_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_32
- (.I0(SC_addResult_i_67_n_0),
- .I1(SC_addResult_i_68_n_0),
- .O(SC_addResult_i_32_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_33
- (.I0(SC_addResult_i_69_n_0),
- .I1(SC_addResult_i_70_n_0),
- .O(SC_addResult_i_33_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_34
- (.I0(SC_addResult_i_71_n_0),
- .I1(SC_addResult_i_72_n_0),
- .O(SC_addResult_i_34_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_35
- (.I0(SC_addResult_i_73_n_0),
- .I1(SC_addResult_i_74_n_0),
- .O(SC_addResult_i_35_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_36
- (.I0(SC_addResult_i_75_n_0),
- .I1(SC_addResult_i_76_n_0),
- .O(SC_addResult_i_36_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_37
- (.I0(SC_addResult_i_77_n_0),
- .I1(SC_addResult_i_78_n_0),
- .O(SC_addResult_i_37_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_38
- (.I0(SC_addResult_i_79_n_0),
- .I1(SC_addResult_i_80_n_0),
- .O(SC_addResult_i_38_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_39
- (.I0(SC_addResult_i_81_n_0),
- .I1(SC_addResult_i_82_n_0),
- .O(SC_addResult_i_39_n_0),
- .S(SR_readAddress[2]));
- LUT4 #(
- .INIT(16'hE997))
- SC_addResult_i_4
- (.I0(SR_readAddress[1]),
- .I1(SR_readAddress[3]),
- .I2(SR_readAddress[2]),
- .I3(SR_readAddress[0]),
- .O(SC_multOperand2[8]));
- MUXF7 SC_addResult_i_40
- (.I0(SC_addResult_i_83_n_0),
- .I1(SC_addResult_i_84_n_0),
- .O(SC_addResult_i_40_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_41
- (.I0(SC_addResult_i_85_n_0),
- .I1(SC_addResult_i_86_n_0),
- .O(SC_addResult_i_41_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_42
- (.I0(SC_addResult_i_87_n_0),
- .I1(SC_addResult_i_88_n_0),
- .O(SC_addResult_i_42_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_43
- (.I0(SC_addResult_i_89_n_0),
- .I1(SC_addResult_i_90_n_0),
- .O(SC_addResult_i_43_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_44
- (.I0(SC_addResult_i_91_n_0),
- .I1(SC_addResult_i_92_n_0),
- .O(SC_addResult_i_44_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_45
- (.I0(SC_addResult_i_93_n_0),
- .I1(SC_addResult_i_94_n_0),
- .O(SC_addResult_i_45_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_46
- (.I0(SC_addResult_i_95_n_0),
- .I1(SC_addResult_i_96_n_0),
- .O(SC_addResult_i_46_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_47
- (.I0(SC_addResult_i_97_n_0),
- .I1(SC_addResult_i_98_n_0),
- .O(SC_addResult_i_47_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_48
- (.I0(SC_addResult_i_99_n_0),
- .I1(SC_addResult_i_100_n_0),
- .O(SC_addResult_i_48_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_49
- (.I0(SC_addResult_i_101_n_0),
- .I1(SC_addResult_i_102_n_0),
- .O(SC_addResult_i_49_n_0),
- .S(SR_readAddress[2]));
- LUT4 #(
- .INIT(16'h6186))
- SC_addResult_i_5
- (.I0(SR_readAddress[1]),
- .I1(SR_readAddress[3]),
- .I2(SR_readAddress[2]),
- .I3(SR_readAddress[0]),
- .O(SC_multOperand2[7]));
- MUXF7 SC_addResult_i_50
- (.I0(SC_addResult_i_103_n_0),
- .I1(SC_addResult_i_104_n_0),
- .O(SC_addResult_i_50_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_51
- (.I0(SC_addResult_i_105_n_0),
- .I1(SC_addResult_i_106_n_0),
- .O(SC_addResult_i_51_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_52
- (.I0(SC_addResult_i_107_n_0),
- .I1(SC_addResult_i_108_n_0),
- .O(SC_addResult_i_52_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_53
- (.I0(SC_addResult_i_109_n_0),
- .I1(SC_addResult_i_110_n_0),
- .O(SC_addResult_i_53_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_54
- (.I0(SC_addResult_i_111_n_0),
- .I1(SC_addResult_i_112_n_0),
- .O(SC_addResult_i_54_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_55
- (.I0(SC_addResult_i_113_n_0),
- .I1(SC_addResult_i_114_n_0),
- .O(SC_addResult_i_55_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_56
- (.I0(SC_addResult_i_115_n_0),
- .I1(SC_addResult_i_116_n_0),
- .O(SC_addResult_i_56_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_57
- (.I0(SC_addResult_i_117_n_0),
- .I1(SC_addResult_i_118_n_0),
- .O(SC_addResult_i_57_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_58
- (.I0(SC_addResult_i_119_n_0),
- .I1(SC_addResult_i_120_n_0),
- .O(SC_addResult_i_58_n_0),
- .S(SR_readAddress[2]));
- MUXF7 SC_addResult_i_59
- (.I0(SC_addResult_i_121_n_0),
- .I1(SC_addResult_i_122_n_0),
- .O(SC_addResult_i_59_n_0),
- .S(SR_readAddress[2]));
- LUT3 #(
- .INIT(8'h42))
- SC_addResult_i_6
- (.I0(SR_readAddress[0]),
- .I1(SR_readAddress[1]),
- .I2(SR_readAddress[2]),
- .O(SC_multOperand2[6]));
- MUXF7 SC_addResult_i_60
- (.I0(SC_addResult_i_123_n_0),
- .I1(SC_addResult_i_124_n_0),
- .O(SC_addResult_i_60_n_0),
- .S(SR_readAddress[2]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_61
- (.I0(\SR_shiftRegister_reg[3] [15]),
- .I1(\SR_shiftRegister_reg[2] [15]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [15]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [15]),
- .O(SC_addResult_i_61_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_62
- (.I0(\SR_shiftRegister_reg[7] [15]),
- .I1(\SR_shiftRegister_reg[6] [15]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [15]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [15]),
- .O(SC_addResult_i_62_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_63
- (.I0(\SR_shiftRegister_reg[11] [15]),
- .I1(\SR_shiftRegister_reg[10] [15]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [15]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [15]),
- .O(SC_addResult_i_63_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_64
- (.I0(\SR_shiftRegister_reg[15] [15]),
- .I1(\SR_shiftRegister_reg[14] [15]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [15]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [15]),
- .O(SC_addResult_i_64_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_65
- (.I0(\SR_shiftRegister_reg[3] [14]),
- .I1(\SR_shiftRegister_reg[2] [14]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [14]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [14]),
- .O(SC_addResult_i_65_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_66
- (.I0(\SR_shiftRegister_reg[7] [14]),
- .I1(\SR_shiftRegister_reg[6] [14]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [14]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [14]),
- .O(SC_addResult_i_66_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_67
- (.I0(\SR_shiftRegister_reg[11] [14]),
- .I1(\SR_shiftRegister_reg[10] [14]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [14]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [14]),
- .O(SC_addResult_i_67_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_68
- (.I0(\SR_shiftRegister_reg[15] [14]),
- .I1(\SR_shiftRegister_reg[14] [14]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [14]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [14]),
- .O(SC_addResult_i_68_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_69
- (.I0(\SR_shiftRegister_reg[3] [13]),
- .I1(\SR_shiftRegister_reg[2] [13]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [13]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [13]),
- .O(SC_addResult_i_69_n_0));
- LUT4 #(
- .INIT(16'hA245))
- SC_addResult_i_7
- (.I0(SR_readAddress[0]),
- .I1(SR_readAddress[2]),
- .I2(SR_readAddress[3]),
- .I3(SR_readAddress[1]),
- .O(SC_multOperand2[5]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_70
- (.I0(\SR_shiftRegister_reg[7] [13]),
- .I1(\SR_shiftRegister_reg[6] [13]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [13]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [13]),
- .O(SC_addResult_i_70_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_71
- (.I0(\SR_shiftRegister_reg[11] [13]),
- .I1(\SR_shiftRegister_reg[10] [13]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [13]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [13]),
- .O(SC_addResult_i_71_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_72
- (.I0(\SR_shiftRegister_reg[15] [13]),
- .I1(\SR_shiftRegister_reg[14] [13]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [13]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [13]),
- .O(SC_addResult_i_72_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_73
- (.I0(\SR_shiftRegister_reg[3] [12]),
- .I1(\SR_shiftRegister_reg[2] [12]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [12]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [12]),
- .O(SC_addResult_i_73_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_74
- (.I0(\SR_shiftRegister_reg[7] [12]),
- .I1(\SR_shiftRegister_reg[6] [12]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [12]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [12]),
- .O(SC_addResult_i_74_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_75
- (.I0(\SR_shiftRegister_reg[11] [12]),
- .I1(\SR_shiftRegister_reg[10] [12]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [12]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [12]),
- .O(SC_addResult_i_75_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_76
- (.I0(\SR_shiftRegister_reg[15] [12]),
- .I1(\SR_shiftRegister_reg[14] [12]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [12]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [12]),
- .O(SC_addResult_i_76_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_77
- (.I0(\SR_shiftRegister_reg[3] [11]),
- .I1(\SR_shiftRegister_reg[2] [11]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [11]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [11]),
- .O(SC_addResult_i_77_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_78
- (.I0(\SR_shiftRegister_reg[7] [11]),
- .I1(\SR_shiftRegister_reg[6] [11]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [11]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [11]),
- .O(SC_addResult_i_78_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_79
- (.I0(\SR_shiftRegister_reg[11] [11]),
- .I1(\SR_shiftRegister_reg[10] [11]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [11]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [11]),
- .O(SC_addResult_i_79_n_0));
- LUT4 #(
- .INIT(16'hF18F))
- SC_addResult_i_8
- (.I0(SR_readAddress[0]),
- .I1(SR_readAddress[1]),
- .I2(SR_readAddress[3]),
- .I3(SR_readAddress[2]),
- .O(SC_multOperand2[4]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_80
- (.I0(\SR_shiftRegister_reg[15] [11]),
- .I1(\SR_shiftRegister_reg[14] [11]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [11]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [11]),
- .O(SC_addResult_i_80_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_81
- (.I0(\SR_shiftRegister_reg[3] [10]),
- .I1(\SR_shiftRegister_reg[2] [10]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [10]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [10]),
- .O(SC_addResult_i_81_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_82
- (.I0(\SR_shiftRegister_reg[7] [10]),
- .I1(\SR_shiftRegister_reg[6] [10]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [10]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [10]),
- .O(SC_addResult_i_82_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_83
- (.I0(\SR_shiftRegister_reg[11] [10]),
- .I1(\SR_shiftRegister_reg[10] [10]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [10]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [10]),
- .O(SC_addResult_i_83_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_84
- (.I0(\SR_shiftRegister_reg[15] [10]),
- .I1(\SR_shiftRegister_reg[14] [10]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [10]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [10]),
- .O(SC_addResult_i_84_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_85
- (.I0(\SR_shiftRegister_reg[3] [9]),
- .I1(\SR_shiftRegister_reg[2] [9]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [9]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [9]),
- .O(SC_addResult_i_85_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_86
- (.I0(\SR_shiftRegister_reg[7] [9]),
- .I1(\SR_shiftRegister_reg[6] [9]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [9]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [9]),
- .O(SC_addResult_i_86_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_87
- (.I0(\SR_shiftRegister_reg[11] [9]),
- .I1(\SR_shiftRegister_reg[10] [9]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [9]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [9]),
- .O(SC_addResult_i_87_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_88
- (.I0(\SR_shiftRegister_reg[15] [9]),
- .I1(\SR_shiftRegister_reg[14] [9]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [9]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [9]),
- .O(SC_addResult_i_88_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_89
- (.I0(\SR_shiftRegister_reg[3] [8]),
- .I1(\SR_shiftRegister_reg[2] [8]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [8]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [8]),
- .O(SC_addResult_i_89_n_0));
- LUT4 #(
- .INIT(16'hD5AB))
- SC_addResult_i_9
- (.I0(SR_readAddress[0]),
- .I1(SR_readAddress[2]),
- .I2(SR_readAddress[3]),
- .I3(SR_readAddress[1]),
- .O(SC_multOperand2[3]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_90
- (.I0(\SR_shiftRegister_reg[7] [8]),
- .I1(\SR_shiftRegister_reg[6] [8]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [8]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [8]),
- .O(SC_addResult_i_90_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_91
- (.I0(\SR_shiftRegister_reg[11] [8]),
- .I1(\SR_shiftRegister_reg[10] [8]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [8]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [8]),
- .O(SC_addResult_i_91_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_92
- (.I0(\SR_shiftRegister_reg[15] [8]),
- .I1(\SR_shiftRegister_reg[14] [8]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [8]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [8]),
- .O(SC_addResult_i_92_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_93
- (.I0(\SR_shiftRegister_reg[3] [7]),
- .I1(\SR_shiftRegister_reg[2] [7]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [7]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [7]),
- .O(SC_addResult_i_93_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_94
- (.I0(\SR_shiftRegister_reg[7] [7]),
- .I1(\SR_shiftRegister_reg[6] [7]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [7]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [7]),
- .O(SC_addResult_i_94_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_95
- (.I0(\SR_shiftRegister_reg[11] [7]),
- .I1(\SR_shiftRegister_reg[10] [7]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [7]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [7]),
- .O(SC_addResult_i_95_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_96
- (.I0(\SR_shiftRegister_reg[15] [7]),
- .I1(\SR_shiftRegister_reg[14] [7]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[13] [7]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[12] [7]),
- .O(SC_addResult_i_96_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_97
- (.I0(\SR_shiftRegister_reg[3] [6]),
- .I1(\SR_shiftRegister_reg[2] [6]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[1] [6]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[0] [6]),
- .O(SC_addResult_i_97_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_98
- (.I0(\SR_shiftRegister_reg[7] [6]),
- .I1(\SR_shiftRegister_reg[6] [6]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[5] [6]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[4] [6]),
- .O(SC_addResult_i_98_n_0));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- SC_addResult_i_99
- (.I0(\SR_shiftRegister_reg[11] [6]),
- .I1(\SR_shiftRegister_reg[10] [6]),
- .I2(SR_readAddress[1]),
- .I3(\SR_shiftRegister_reg[9] [6]),
- .I4(SR_readAddress[0]),
- .I5(\SR_shiftRegister_reg[8] [6]),
- .O(SC_addResult_i_99_n_0));
- LUT2 #(
- .INIT(4'h6))
- \SR_filteredSample[3]_i_2
- (.I0(SC_addResult_n_91),
- .I1(L[15]),
- .O(\SR_filteredSample[3]_i_2_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[0]),
- .Q(O_filteredSample_OBUF[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[10]),
- .Q(O_filteredSample_OBUF[10]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[11]),
- .Q(O_filteredSample_OBUF[11]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 \SR_filteredSample_reg[11]_i_1
- (.CI(\SR_filteredSample_reg[7]_i_1_n_0 ),
- .CO({\SR_filteredSample_reg[11]_i_1_n_0 ,\SR_filteredSample_reg[11]_i_1_n_1 ,\SR_filteredSample_reg[11]_i_1_n_2 ,\SR_filteredSample_reg[11]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .O(p_0_in[11:8]),
- .S(L[26:23]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[12]),
- .Q(O_filteredSample_OBUF[12]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[13]),
- .Q(O_filteredSample_OBUF[13]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[14]),
- .Q(O_filteredSample_OBUF[14]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[15]),
- .Q(O_filteredSample_OBUF[15]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 \SR_filteredSample_reg[15]_i_1
- (.CI(\SR_filteredSample_reg[11]_i_1_n_0 ),
- .CO({\SR_filteredSample_reg[15]_i_1_n_1 ,\SR_filteredSample_reg[15]_i_1_n_2 ,\SR_filteredSample_reg[15]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .O(p_0_in[15:12]),
- .S(L[30:27]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[1]),
- .Q(O_filteredSample_OBUF[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[2]),
- .Q(O_filteredSample_OBUF[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[3]),
- .Q(O_filteredSample_OBUF[3]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 \SR_filteredSample_reg[3]_i_1
- (.CI(\<const0> ),
- .CO({\SR_filteredSample_reg[3]_i_1_n_0 ,\SR_filteredSample_reg[3]_i_1_n_1 ,\SR_filteredSample_reg[3]_i_1_n_2 ,\SR_filteredSample_reg[3]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\<const0> ,SC_addResult_n_91}),
- .O(p_0_in[3:0]),
- .S({L[18:16],\SR_filteredSample[3]_i_2_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[4]),
- .Q(O_filteredSample_OBUF[4]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[5]),
- .Q(O_filteredSample_OBUF[5]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[6]),
- .Q(O_filteredSample_OBUF[6]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[7]),
- .Q(O_filteredSample_OBUF[7]));
- (* ADDER_THRESHOLD = "35" *)
- CARRY4 \SR_filteredSample_reg[7]_i_1
- (.CI(\SR_filteredSample_reg[3]_i_1_n_0 ),
- .CO({\SR_filteredSample_reg[7]_i_1_n_0 ,\SR_filteredSample_reg[7]_i_1_n_1 ,\SR_filteredSample_reg[7]_i_1_n_2 ,\SR_filteredSample_reg[7]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
- .O(p_0_in[7:4]),
- .S(L[22:19]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[8]),
- .Q(O_filteredSample_OBUF[8]));
- FDCE #(
- .INIT(1'b0))
- \SR_filteredSample_reg[9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadOutput_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[9]),
- .Q(O_filteredSample_OBUF[9]));
- LUT2 #(
- .INIT(4'h1))
- \SR_readAddress[0]_i_1
- (.I0(SR_readAddress[0]),
- .I1(I_initAddress_IBUF),
- .O(\SR_readAddress[0]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h06))
- \SR_readAddress[1]_i_1
- (.I0(SR_readAddress[1]),
- .I1(SR_readAddress[0]),
- .I2(I_initAddress_IBUF),
- .O(\SR_readAddress[1]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h006A))
- \SR_readAddress[2]_i_1
- (.I0(SR_readAddress[2]),
- .I1(SR_readAddress[1]),
- .I2(SR_readAddress[0]),
- .I3(I_initAddress_IBUF),
- .O(\SR_readAddress[2]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \SR_readAddress[3]_i_1
- (.I0(I_incrAddress_IBUF),
- .I1(I_initAddress_IBUF),
- .O(\SR_readAddress[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h00006AAA))
- \SR_readAddress[3]_i_2
- (.I0(SR_readAddress[3]),
- .I1(SR_readAddress[2]),
- .I2(SR_readAddress[0]),
- .I3(SR_readAddress[1]),
- .I4(I_initAddress_IBUF),
- .O(\SR_readAddress[3]_i_2_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[0]_i_1_n_0 ),
- .Q(SR_readAddress[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[1]_i_1_n_0 ),
- .Q(SR_readAddress[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[2]_i_1_n_0 ),
- .Q(SR_readAddress[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[3]_i_2_n_0 ),
- .Q(SR_readAddress[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[0]),
- .Q(\SR_shiftRegister_reg[0] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[10]),
- .Q(\SR_shiftRegister_reg[0] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[11]),
- .Q(\SR_shiftRegister_reg[0] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[12]),
- .Q(\SR_shiftRegister_reg[0] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[13]),
- .Q(\SR_shiftRegister_reg[0] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[14]),
- .Q(\SR_shiftRegister_reg[0] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[15]),
- .Q(\SR_shiftRegister_reg[0] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[1]),
- .Q(\SR_shiftRegister_reg[0] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[2]),
- .Q(\SR_shiftRegister_reg[0] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[3]),
- .Q(\SR_shiftRegister_reg[0] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[4]),
- .Q(\SR_shiftRegister_reg[0] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[5]),
- .Q(\SR_shiftRegister_reg[0] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[6]),
- .Q(\SR_shiftRegister_reg[0] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[7]),
- .Q(\SR_shiftRegister_reg[0] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[8]),
- .Q(\SR_shiftRegister_reg[0] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[9]),
- .Q(\SR_shiftRegister_reg[0] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [0]),
- .Q(\SR_shiftRegister_reg[10] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [10]),
- .Q(\SR_shiftRegister_reg[10] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [11]),
- .Q(\SR_shiftRegister_reg[10] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [12]),
- .Q(\SR_shiftRegister_reg[10] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [13]),
- .Q(\SR_shiftRegister_reg[10] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [14]),
- .Q(\SR_shiftRegister_reg[10] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [15]),
- .Q(\SR_shiftRegister_reg[10] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [1]),
- .Q(\SR_shiftRegister_reg[10] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [2]),
- .Q(\SR_shiftRegister_reg[10] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [3]),
- .Q(\SR_shiftRegister_reg[10] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [4]),
- .Q(\SR_shiftRegister_reg[10] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [5]),
- .Q(\SR_shiftRegister_reg[10] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [6]),
- .Q(\SR_shiftRegister_reg[10] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [7]),
- .Q(\SR_shiftRegister_reg[10] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [8]),
- .Q(\SR_shiftRegister_reg[10] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9] [9]),
- .Q(\SR_shiftRegister_reg[10] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [0]),
- .Q(\SR_shiftRegister_reg[11] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [10]),
- .Q(\SR_shiftRegister_reg[11] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [11]),
- .Q(\SR_shiftRegister_reg[11] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [12]),
- .Q(\SR_shiftRegister_reg[11] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [13]),
- .Q(\SR_shiftRegister_reg[11] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [14]),
- .Q(\SR_shiftRegister_reg[11] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [15]),
- .Q(\SR_shiftRegister_reg[11] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [1]),
- .Q(\SR_shiftRegister_reg[11] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [2]),
- .Q(\SR_shiftRegister_reg[11] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [3]),
- .Q(\SR_shiftRegister_reg[11] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [4]),
- .Q(\SR_shiftRegister_reg[11] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [5]),
- .Q(\SR_shiftRegister_reg[11] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [6]),
- .Q(\SR_shiftRegister_reg[11] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [7]),
- .Q(\SR_shiftRegister_reg[11] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [8]),
- .Q(\SR_shiftRegister_reg[11] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10] [9]),
- .Q(\SR_shiftRegister_reg[11] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [0]),
- .Q(\SR_shiftRegister_reg[12] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [10]),
- .Q(\SR_shiftRegister_reg[12] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [11]),
- .Q(\SR_shiftRegister_reg[12] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [12]),
- .Q(\SR_shiftRegister_reg[12] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [13]),
- .Q(\SR_shiftRegister_reg[12] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [14]),
- .Q(\SR_shiftRegister_reg[12] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [15]),
- .Q(\SR_shiftRegister_reg[12] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [1]),
- .Q(\SR_shiftRegister_reg[12] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [2]),
- .Q(\SR_shiftRegister_reg[12] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [3]),
- .Q(\SR_shiftRegister_reg[12] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [4]),
- .Q(\SR_shiftRegister_reg[12] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [5]),
- .Q(\SR_shiftRegister_reg[12] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [6]),
- .Q(\SR_shiftRegister_reg[12] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [7]),
- .Q(\SR_shiftRegister_reg[12] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [8]),
- .Q(\SR_shiftRegister_reg[12] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11] [9]),
- .Q(\SR_shiftRegister_reg[12] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [0]),
- .Q(\SR_shiftRegister_reg[13] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [10]),
- .Q(\SR_shiftRegister_reg[13] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [11]),
- .Q(\SR_shiftRegister_reg[13] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [12]),
- .Q(\SR_shiftRegister_reg[13] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [13]),
- .Q(\SR_shiftRegister_reg[13] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [14]),
- .Q(\SR_shiftRegister_reg[13] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [15]),
- .Q(\SR_shiftRegister_reg[13] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [1]),
- .Q(\SR_shiftRegister_reg[13] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [2]),
- .Q(\SR_shiftRegister_reg[13] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [3]),
- .Q(\SR_shiftRegister_reg[13] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [4]),
- .Q(\SR_shiftRegister_reg[13] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [5]),
- .Q(\SR_shiftRegister_reg[13] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [6]),
- .Q(\SR_shiftRegister_reg[13] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [7]),
- .Q(\SR_shiftRegister_reg[13] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [8]),
- .Q(\SR_shiftRegister_reg[13] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12] [9]),
- .Q(\SR_shiftRegister_reg[13] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [0]),
- .Q(\SR_shiftRegister_reg[14] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [10]),
- .Q(\SR_shiftRegister_reg[14] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [11]),
- .Q(\SR_shiftRegister_reg[14] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [12]),
- .Q(\SR_shiftRegister_reg[14] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [13]),
- .Q(\SR_shiftRegister_reg[14] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [14]),
- .Q(\SR_shiftRegister_reg[14] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [15]),
- .Q(\SR_shiftRegister_reg[14] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [1]),
- .Q(\SR_shiftRegister_reg[14] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [2]),
- .Q(\SR_shiftRegister_reg[14] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [3]),
- .Q(\SR_shiftRegister_reg[14] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [4]),
- .Q(\SR_shiftRegister_reg[14] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [5]),
- .Q(\SR_shiftRegister_reg[14] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [6]),
- .Q(\SR_shiftRegister_reg[14] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [7]),
- .Q(\SR_shiftRegister_reg[14] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [8]),
- .Q(\SR_shiftRegister_reg[14] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13] [9]),
- .Q(\SR_shiftRegister_reg[14] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [0]),
- .Q(\SR_shiftRegister_reg[15] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [10]),
- .Q(\SR_shiftRegister_reg[15] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [11]),
- .Q(\SR_shiftRegister_reg[15] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [12]),
- .Q(\SR_shiftRegister_reg[15] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [13]),
- .Q(\SR_shiftRegister_reg[15] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [14]),
- .Q(\SR_shiftRegister_reg[15] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [15]),
- .Q(\SR_shiftRegister_reg[15] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [1]),
- .Q(\SR_shiftRegister_reg[15] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [2]),
- .Q(\SR_shiftRegister_reg[15] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [3]),
- .Q(\SR_shiftRegister_reg[15] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [4]),
- .Q(\SR_shiftRegister_reg[15] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [5]),
- .Q(\SR_shiftRegister_reg[15] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [6]),
- .Q(\SR_shiftRegister_reg[15] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [7]),
- .Q(\SR_shiftRegister_reg[15] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [8]),
- .Q(\SR_shiftRegister_reg[15] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14] [9]),
- .Q(\SR_shiftRegister_reg[15] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [0]),
- .Q(\SR_shiftRegister_reg[1] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [10]),
- .Q(\SR_shiftRegister_reg[1] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [11]),
- .Q(\SR_shiftRegister_reg[1] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [12]),
- .Q(\SR_shiftRegister_reg[1] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [13]),
- .Q(\SR_shiftRegister_reg[1] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [14]),
- .Q(\SR_shiftRegister_reg[1] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [15]),
- .Q(\SR_shiftRegister_reg[1] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [1]),
- .Q(\SR_shiftRegister_reg[1] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [2]),
- .Q(\SR_shiftRegister_reg[1] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [3]),
- .Q(\SR_shiftRegister_reg[1] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [4]),
- .Q(\SR_shiftRegister_reg[1] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [5]),
- .Q(\SR_shiftRegister_reg[1] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [6]),
- .Q(\SR_shiftRegister_reg[1] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [7]),
- .Q(\SR_shiftRegister_reg[1] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [8]),
- .Q(\SR_shiftRegister_reg[1] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0] [9]),
- .Q(\SR_shiftRegister_reg[1] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [0]),
- .Q(\SR_shiftRegister_reg[2] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [10]),
- .Q(\SR_shiftRegister_reg[2] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [11]),
- .Q(\SR_shiftRegister_reg[2] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [12]),
- .Q(\SR_shiftRegister_reg[2] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [13]),
- .Q(\SR_shiftRegister_reg[2] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [14]),
- .Q(\SR_shiftRegister_reg[2] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [15]),
- .Q(\SR_shiftRegister_reg[2] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [1]),
- .Q(\SR_shiftRegister_reg[2] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [2]),
- .Q(\SR_shiftRegister_reg[2] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [3]),
- .Q(\SR_shiftRegister_reg[2] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [4]),
- .Q(\SR_shiftRegister_reg[2] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [5]),
- .Q(\SR_shiftRegister_reg[2] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [6]),
- .Q(\SR_shiftRegister_reg[2] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [7]),
- .Q(\SR_shiftRegister_reg[2] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [8]),
- .Q(\SR_shiftRegister_reg[2] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1] [9]),
- .Q(\SR_shiftRegister_reg[2] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [0]),
- .Q(\SR_shiftRegister_reg[3] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [10]),
- .Q(\SR_shiftRegister_reg[3] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [11]),
- .Q(\SR_shiftRegister_reg[3] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [12]),
- .Q(\SR_shiftRegister_reg[3] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [13]),
- .Q(\SR_shiftRegister_reg[3] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [14]),
- .Q(\SR_shiftRegister_reg[3] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [15]),
- .Q(\SR_shiftRegister_reg[3] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [1]),
- .Q(\SR_shiftRegister_reg[3] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [2]),
- .Q(\SR_shiftRegister_reg[3] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [3]),
- .Q(\SR_shiftRegister_reg[3] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [4]),
- .Q(\SR_shiftRegister_reg[3] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [5]),
- .Q(\SR_shiftRegister_reg[3] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [6]),
- .Q(\SR_shiftRegister_reg[3] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [7]),
- .Q(\SR_shiftRegister_reg[3] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [8]),
- .Q(\SR_shiftRegister_reg[3] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2] [9]),
- .Q(\SR_shiftRegister_reg[3] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [0]),
- .Q(\SR_shiftRegister_reg[4] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [10]),
- .Q(\SR_shiftRegister_reg[4] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [11]),
- .Q(\SR_shiftRegister_reg[4] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [12]),
- .Q(\SR_shiftRegister_reg[4] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [13]),
- .Q(\SR_shiftRegister_reg[4] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [14]),
- .Q(\SR_shiftRegister_reg[4] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [15]),
- .Q(\SR_shiftRegister_reg[4] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [1]),
- .Q(\SR_shiftRegister_reg[4] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [2]),
- .Q(\SR_shiftRegister_reg[4] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [3]),
- .Q(\SR_shiftRegister_reg[4] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [4]),
- .Q(\SR_shiftRegister_reg[4] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [5]),
- .Q(\SR_shiftRegister_reg[4] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [6]),
- .Q(\SR_shiftRegister_reg[4] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [7]),
- .Q(\SR_shiftRegister_reg[4] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [8]),
- .Q(\SR_shiftRegister_reg[4] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3] [9]),
- .Q(\SR_shiftRegister_reg[4] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [0]),
- .Q(\SR_shiftRegister_reg[5] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [10]),
- .Q(\SR_shiftRegister_reg[5] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [11]),
- .Q(\SR_shiftRegister_reg[5] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [12]),
- .Q(\SR_shiftRegister_reg[5] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [13]),
- .Q(\SR_shiftRegister_reg[5] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [14]),
- .Q(\SR_shiftRegister_reg[5] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [15]),
- .Q(\SR_shiftRegister_reg[5] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [1]),
- .Q(\SR_shiftRegister_reg[5] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [2]),
- .Q(\SR_shiftRegister_reg[5] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [3]),
- .Q(\SR_shiftRegister_reg[5] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [4]),
- .Q(\SR_shiftRegister_reg[5] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [5]),
- .Q(\SR_shiftRegister_reg[5] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [6]),
- .Q(\SR_shiftRegister_reg[5] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [7]),
- .Q(\SR_shiftRegister_reg[5] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [8]),
- .Q(\SR_shiftRegister_reg[5] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4] [9]),
- .Q(\SR_shiftRegister_reg[5] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [0]),
- .Q(\SR_shiftRegister_reg[6] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [10]),
- .Q(\SR_shiftRegister_reg[6] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [11]),
- .Q(\SR_shiftRegister_reg[6] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [12]),
- .Q(\SR_shiftRegister_reg[6] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [13]),
- .Q(\SR_shiftRegister_reg[6] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [14]),
- .Q(\SR_shiftRegister_reg[6] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [15]),
- .Q(\SR_shiftRegister_reg[6] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [1]),
- .Q(\SR_shiftRegister_reg[6] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [2]),
- .Q(\SR_shiftRegister_reg[6] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [3]),
- .Q(\SR_shiftRegister_reg[6] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [4]),
- .Q(\SR_shiftRegister_reg[6] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [5]),
- .Q(\SR_shiftRegister_reg[6] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [6]),
- .Q(\SR_shiftRegister_reg[6] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [7]),
- .Q(\SR_shiftRegister_reg[6] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [8]),
- .Q(\SR_shiftRegister_reg[6] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5] [9]),
- .Q(\SR_shiftRegister_reg[6] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [0]),
- .Q(\SR_shiftRegister_reg[7] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [10]),
- .Q(\SR_shiftRegister_reg[7] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [11]),
- .Q(\SR_shiftRegister_reg[7] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [12]),
- .Q(\SR_shiftRegister_reg[7] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [13]),
- .Q(\SR_shiftRegister_reg[7] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [14]),
- .Q(\SR_shiftRegister_reg[7] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [15]),
- .Q(\SR_shiftRegister_reg[7] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [1]),
- .Q(\SR_shiftRegister_reg[7] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [2]),
- .Q(\SR_shiftRegister_reg[7] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [3]),
- .Q(\SR_shiftRegister_reg[7] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [4]),
- .Q(\SR_shiftRegister_reg[7] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [5]),
- .Q(\SR_shiftRegister_reg[7] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [6]),
- .Q(\SR_shiftRegister_reg[7] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [7]),
- .Q(\SR_shiftRegister_reg[7] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [8]),
- .Q(\SR_shiftRegister_reg[7] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6] [9]),
- .Q(\SR_shiftRegister_reg[7] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [0]),
- .Q(\SR_shiftRegister_reg[8] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [10]),
- .Q(\SR_shiftRegister_reg[8] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [11]),
- .Q(\SR_shiftRegister_reg[8] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [12]),
- .Q(\SR_shiftRegister_reg[8] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [13]),
- .Q(\SR_shiftRegister_reg[8] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [14]),
- .Q(\SR_shiftRegister_reg[8] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [15]),
- .Q(\SR_shiftRegister_reg[8] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [1]),
- .Q(\SR_shiftRegister_reg[8] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [2]),
- .Q(\SR_shiftRegister_reg[8] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [3]),
- .Q(\SR_shiftRegister_reg[8] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [4]),
- .Q(\SR_shiftRegister_reg[8] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [5]),
- .Q(\SR_shiftRegister_reg[8] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [6]),
- .Q(\SR_shiftRegister_reg[8] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [7]),
- .Q(\SR_shiftRegister_reg[8] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [8]),
- .Q(\SR_shiftRegister_reg[8] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7] [9]),
- .Q(\SR_shiftRegister_reg[8] [9]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [0]),
- .Q(\SR_shiftRegister_reg[9] [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][10]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [10]),
- .Q(\SR_shiftRegister_reg[9] [10]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][11]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [11]),
- .Q(\SR_shiftRegister_reg[9] [11]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][12]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [12]),
- .Q(\SR_shiftRegister_reg[9] [12]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][13]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [13]),
- .Q(\SR_shiftRegister_reg[9] [13]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][14]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [14]),
- .Q(\SR_shiftRegister_reg[9] [14]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][15]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [15]),
- .Q(\SR_shiftRegister_reg[9] [15]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [1]),
- .Q(\SR_shiftRegister_reg[9] [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [2]),
- .Q(\SR_shiftRegister_reg[9] [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [3]),
- .Q(\SR_shiftRegister_reg[9] [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [4]),
- .Q(\SR_shiftRegister_reg[9] [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [5]),
- .Q(\SR_shiftRegister_reg[9] [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [6]),
- .Q(\SR_shiftRegister_reg[9] [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [7]),
- .Q(\SR_shiftRegister_reg[9] [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][8]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [8]),
- .Q(\SR_shiftRegister_reg[9] [8]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][9]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8] [9]),
- .Q(\SR_shiftRegister_reg[9] [9]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_1
- (.I0(SC_addResult_n_105),
- .I1(I_initSum_IBUF),
- .O(p_1_in[0]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[10]_i_1
- (.I0(SC_addResult_n_95),
- .I1(I_initSum_IBUF),
- .O(p_1_in[10]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[11]_i_1
- (.I0(SC_addResult_n_94),
- .I1(I_initSum_IBUF),
- .O(p_1_in[11]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[12]_i_1
- (.I0(SC_addResult_n_93),
- .I1(I_initSum_IBUF),
- .O(p_1_in[12]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[13]_i_1
- (.I0(SC_addResult_n_92),
- .I1(I_initSum_IBUF),
- .O(p_1_in[13]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[14]_i_1
- (.I0(SC_addResult_n_91),
- .I1(I_initSum_IBUF),
- .O(p_1_in[14]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[15]_i_1
- (.I0(L[15]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[15]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[16]_i_1
- (.I0(L[16]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[16]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[17]_i_1
- (.I0(L[17]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[17]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[18]_i_1
- (.I0(L[18]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[18]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[19]_i_1
- (.I0(L[19]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[19]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[1]_i_1
- (.I0(SC_addResult_n_104),
- .I1(I_initSum_IBUF),
- .O(p_1_in[1]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[20]_i_1
- (.I0(L[20]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[20]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[21]_i_1
- (.I0(L[21]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[21]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[22]_i_1
- (.I0(L[22]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[22]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[23]_i_1
- (.I0(L[23]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[23]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[24]_i_1
- (.I0(L[24]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[24]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[25]_i_1
- (.I0(L[25]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[25]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[26]_i_1
- (.I0(L[26]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[26]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[27]_i_1
- (.I0(L[27]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[27]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[28]_i_1
- (.I0(L[28]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[28]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[29]_i_1
- (.I0(L[29]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[29]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[2]_i_1
- (.I0(SC_addResult_n_103),
- .I1(I_initSum_IBUF),
- .O(p_1_in[2]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[30]_i_1
- (.I0(L[30]),
- .I1(I_initSum_IBUF),
- .O(p_1_in[30]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[31]_i_1
- (.I0(SC_addResult_n_74),
- .I1(I_initSum_IBUF),
- .O(p_1_in[31]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[32]_i_1
- (.I0(SC_addResult_n_73),
- .I1(I_initSum_IBUF),
- .O(p_1_in[32]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[33]_i_1
- (.I0(SC_addResult_n_72),
- .I1(I_initSum_IBUF),
- .O(p_1_in[33]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[34]_i_1
- (.I0(SC_addResult_n_71),
- .I1(I_initSum_IBUF),
- .O(p_1_in[34]));
- LUT2 #(
- .INIT(4'hE))
- \SR_sum[35]_i_1
- (.I0(I_loadSum_IBUF),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[35]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[35]_i_2
- (.I0(SC_addResult_n_70),
- .I1(I_initSum_IBUF),
- .O(p_1_in[35]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[3]_i_1
- (.I0(SC_addResult_n_102),
- .I1(I_initSum_IBUF),
- .O(p_1_in[3]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_1
- (.I0(SC_addResult_n_101),
- .I1(I_initSum_IBUF),
- .O(p_1_in[4]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[5]_i_1
- (.I0(SC_addResult_n_100),
- .I1(I_initSum_IBUF),
- .O(p_1_in[5]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[6]_i_1
- (.I0(SC_addResult_n_99),
- .I1(I_initSum_IBUF),
- .O(p_1_in[6]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[7]_i_1
- (.I0(SC_addResult_n_98),
- .I1(I_initSum_IBUF),
- .O(p_1_in[7]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_1
- (.I0(SC_addResult_n_97),
- .I1(I_initSum_IBUF),
- .O(p_1_in[8]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[9]_i_1
- (.I0(SC_addResult_n_96),
- .I1(I_initSum_IBUF),
- .O(p_1_in[9]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[0]),
- .Q(SR_sum[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[10]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[10]),
- .Q(SR_sum[10]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[11]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[11]),
- .Q(SR_sum[11]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[12]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[12]),
- .Q(SR_sum[12]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[13]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[13]),
- .Q(SR_sum[13]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[14]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[14]),
- .Q(SR_sum[14]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[15]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[15]),
- .Q(SR_sum[15]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[16]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[16]),
- .Q(SR_sum[16]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[17]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[17]),
- .Q(SR_sum[17]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[18]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[18]),
- .Q(SR_sum[18]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[19]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[19]),
- .Q(SR_sum[19]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[1]),
- .Q(SR_sum[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[20]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[20]),
- .Q(SR_sum[20]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[21]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[21]),
- .Q(SR_sum[21]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[22]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[22]),
- .Q(SR_sum[22]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[23]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[23]),
- .Q(SR_sum[23]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[24]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[24]),
- .Q(SR_sum[24]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[25]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[25]),
- .Q(SR_sum[25]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[26]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[26]),
- .Q(SR_sum[26]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[27]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[27]),
- .Q(SR_sum[27]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[28]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[28]),
- .Q(SR_sum[28]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[29]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[29]),
- .Q(SR_sum[29]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[2]),
- .Q(SR_sum[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[30]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[30]),
- .Q(SR_sum[30]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[31]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[31]),
- .Q(SR_sum[31]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[32]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[32]),
- .Q(SR_sum[32]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[33]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[33]),
- .Q(SR_sum[33]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[34]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[34]),
- .Q(SR_sum[34]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[35]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[35]),
- .Q(SR_sum[35]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[3]),
- .Q(SR_sum[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[4]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[4]),
- .Q(SR_sum[4]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[5]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[5]),
- .Q(SR_sum[5]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[6]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[6]),
- .Q(SR_sum[6]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[7]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[7]),
- .Q(SR_sum[7]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[8]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[8]),
- .Q(SR_sum[8]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[9]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[35]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(p_1_in[9]),
- .Q(SR_sum[9]));
- VCC VCC
- (.P(\<const1> ));
-endmodule
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index e30462a8c6a9fbdde05d44b483010d8aedaa68a1..576ce1fa6856fa122a55d7ae5e2f95c5436e37fe 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -45,7 +45,7 @@ entity operativeUnit is
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register;
- I_loadY : in std_logic; -- Control signal to load Y register
+ I_loadOutput : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done
O_filteredSample : out std_logic_vector(15 downto 0) -- filtered sample
);
@@ -86,7 +86,9 @@ begin
-- quantized_signal = round(min(max(signal * 2^(q-1), min_val), max_val)) / 2^(q-1);
-- end
--
- -- q=16
+ -- q=16SETUP MEE_VIVADO_CLASSROOM # sets up the environment (license, PATH)
+
+
--
-- fLPq= quantize(fLP,q);
--
@@ -120,17 +122,18 @@ begin
SR_shiftRegister <= (others => (others => '0'));
elsif rising_edge(I_clock) then
if I_loadShift = '1' then
- for i in 15 downto 1 loop
- SR_shiftRegister(i) <= SR_shiftRegister(i-1);
- end loop;
- SR_shiftRegister(0) <= I_inputSample;
+ --for i in 15 downto 1 loop
+ -- SR_shiftRegister(i) <= SR_shiftRegister(i-1);
+ --end loop;
+ SR_shiftRegister(1 to 15) <= SR_shiftRegister(0 to 14);
+ SR_shiftRegister(0) <= signed(I_inputSample);
end if;
end if;
end process shift;
-- Process to describe the counter providing the selection adresses
-- of the multiplexers
- incr_address : process (I_reset,I_clck) is
+ incr_address : process (I_reset,I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0;
@@ -145,10 +148,10 @@ begin
-- Signal detecting that the next cycle will be the one
-- providing the last product used to compute the convolution
- O_processingDone <= '1' when SR_readAddress = '15' else '0';
+ O_processingDone <= '1' when SR_readAddress = 14 else '0';
-- Signals connected with multiplexers (SIMPLY inferred with table indices)
- SC_multOperand1 <= SR_shiftedRegister(SR_readAddress); -- 16 bits
+ SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 16 bits
SC_multOperand2 <= SR_coefRegister(SR_readAddress); -- 16 bits
-- Multiplication of the operands
@@ -170,17 +173,17 @@ begin
elsif I_loadSum = '1' then
SR_sum <= SC_addResult;
end if;
- end if;cription⚓
+ end if;
end process sum_acc;
-- Register to store the final result if the loadOuput is active
- store_result : process (_BLANK_) is
+ store_result : process (I_reset,I_clock) is
begin
if I_reset = '1' then
SR_filteredSample <= (others => '0');
elsif rising_edge (I_clock) then
- if I_loadY ='1' then
- SR_filteredSample <=
+ if I_loadOutput ='1' then
+ SR_filteredSample <= signed(SC_addResult(30 downto 15));
end if;
end if;