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proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh 0 → 100755
View file @ da45ac30
// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
///////////////////////////////////////////////////////////////////////////////
// These are user functions that should not be modified. Changes to the defines
// or code within the functions may alter the accuracy of the calculations.
// Define debug to provide extra messages durring elaboration
//`define DEBUG 1
// FRAC_PRECISION describes the width of the fractional portion of the fixed
// point numbers. These should not be modified, they are for development
// only
`define FRAC_PRECISION 10
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
// greater than 32
`define FIXED_WIDTH 32
// This function takes a fixed point number and rounds it to the nearest
// fractional precision bit.
function [`FIXED_WIDTH:1] round_frac
(
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
input [`FIXED_WIDTH:1] decimal,
// This describes the precision of the fraction, for example a value
// of 1 would modify the fractional so that instead of being a .16
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
input [`FIXED_WIDTH:1] precision
);
begin
`ifdef DEBUG
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
`endif
// If the fractional precision bit is high then round up
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
end else begin
round_frac = decimal;
end
`ifdef DEBUG
$display("round_frac: %h", round_frac);
`endif
end
endfunction
// This function calculates high_time, low_time, w_edge, and no_count
// of a non-fractional counter based on the divide and duty cycle
//
// NOTE: high_time and low_time are returned as integers between 0 and 63
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
// ignore the overflow)
function [13:0] mmcm_pll_divider
(
input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
);
reg [`FIXED_WIDTH:1] duty_cycle_fix;
// High/Low time is initially calculated with a wider integer to prevent a
// calculation error when it overflows to 64.
reg [6:0] high_time;
reg [6:0] low_time;
reg w_edge;
reg no_count;
reg [`FIXED_WIDTH:1] temp;
begin
// Duty Cycle must be between 0 and 1,000
if(duty_cycle <=0 || duty_cycle >= 100000) begin
`ifndef SYNTHESIS
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
`endif
$finish;
end
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
`ifdef DEBUG
$display("duty_cycle_fix: %h", duty_cycle_fix);
`endif
// If the divide is 1 nothing needs to be set except the no_count bit.
// Other values are dummies
if(divide == 7'h01) begin
high_time = 7'h01;
w_edge = 1'b0;
low_time = 7'h01;
no_count = 1'b1;
end else begin
temp = round_frac(duty_cycle_fix*divide, 1);
// comes from above round_frac
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
// If the duty cycle * divide rounded is .5 or greater then this bit
// is set.
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
// If the high time comes out to 0, it needs to be set to at least 1
// and w_edge set to 0
if(high_time == 7'h00) begin
high_time = 7'h01;
w_edge = 1'b0;
end
if(high_time == divide) begin
high_time = divide - 1;
w_edge = 1'b1;
end
// Calculate low_time based on the divide setting and set no_count to
// 0 as it is only used when divide is 1.
low_time = divide - high_time;
no_count = 1'b0;
end
// Set the return value.
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
end
endfunction
// This function calculates mx, delay_time, and phase_mux
// of a non-fractional counter based on the divide and phase
//
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
// is used.
function [10:0] mmcm_pll_phase
(
// divide must be an integer (use fractional if not)
// assumed that divide already checked to be valid
input [7:0] divide, // Max divide is 128
// Phase is given in degrees (-360,000 to 360,000)
input signed [31:0] phase
);
reg [`FIXED_WIDTH:1] phase_in_cycles;
reg [`FIXED_WIDTH:1] phase_fixed;
reg [1:0] mx;
reg [5:0] delay_time;
reg [2:0] phase_mux;
reg [`FIXED_WIDTH:1] temp;
begin
`ifdef DEBUG
$display("mmcm_pll_phase-divide:%d,phase:%d",
divide, phase);
`endif
if ((phase < -360000) || (phase > 360000)) begin
`ifndef SYNTHESIS
$display("ERROR: phase of $phase is not between -360000 and 360000");
`endif
$finish;
end
// If phase is less than 0, convert it to a positive phase shift
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
if(phase < 0) begin
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
end else begin
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
end
// Put phase in terms of decimal number of vco clock cycles
phase_in_cycles = ( phase_fixed * divide ) / 360;
`ifdef DEBUG
$display("phase_in_cycles: %h", phase_in_cycles);
`endif
temp = round_frac(phase_in_cycles, 3);
// set mx to 2'b00 that the phase mux from the VCO is enabled
mx = 2'b00;
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
`ifdef DEBUG
$display("temp: %h", temp);
`endif
// Setup the return value
mmcm_pll_phase={mx, phase_mux, delay_time};
end
endfunction
// This function takes the divide value and outputs the necessary lock values
function [39:0] mmcm_pll_lock_lookup
(
input [6:0] divide // Max divide is 64
);
reg [2559:0] lookup;
begin
lookup = {
// This table is composed of:
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
40'b00110_00110_1111101000_1111101001_0000000001,
40'b00110_00110_1111101000_1111101001_0000000001,
40'b01000_01000_1111101000_1111101001_0000000001,
40'b01011_01011_1111101000_1111101001_0000000001,
40'b01110_01110_1111101000_1111101001_0000000001,
40'b10001_10001_1111101000_1111101001_0000000001,
40'b10011_10011_1111101000_1111101001_0000000001,
40'b10110_10110_1111101000_1111101001_0000000001,
40'b11001_11001_1111101000_1111101001_0000000001,
40'b11100_11100_1111101000_1111101001_0000000001,
40'b11111_11111_1110000100_1111101001_0000000001,
40'b11111_11111_1100111001_1111101001_0000000001,
40'b11111_11111_1011101110_1111101001_0000000001,
40'b11111_11111_1010111100_1111101001_0000000001,
40'b11111_11111_1010001010_1111101001_0000000001,
40'b11111_11111_1001110001_1111101001_0000000001,
40'b11111_11111_1000111111_1111101001_0000000001,
40'b11111_11111_1000100110_1111101001_0000000001,
40'b11111_11111_1000001101_1111101001_0000000001,
40'b11111_11111_0111110100_1111101001_0000000001,
40'b11111_11111_0111011011_1111101001_0000000001,
40'b11111_11111_0111000010_1111101001_0000000001,
40'b11111_11111_0110101001_1111101001_0000000001,
40'b11111_11111_0110010000_1111101001_0000000001,
40'b11111_11111_0110010000_1111101001_0000000001,
40'b11111_11111_0101110111_1111101001_0000000001,
40'b11111_11111_0101011110_1111101001_0000000001,
40'b11111_11111_0101011110_1111101001_0000000001,
40'b11111_11111_0101000101_1111101001_0000000001,
40'b11111_11111_0101000101_1111101001_0000000001,
40'b11111_11111_0100101100_1111101001_0000000001,
40'b11111_11111_0100101100_1111101001_0000000001,
40'b11111_11111_0100101100_1111101001_0000000001,
40'b11111_11111_0100010011_1111101001_0000000001,
40'b11111_11111_0100010011_1111101001_0000000001,
40'b11111_11111_0100010011_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001,
40'b11111_11111_0011111010_1111101001_0000000001
};
// Set lookup_entry with the explicit bits from lookup with a part select
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
`ifdef DEBUG
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
`endif
end
endfunction
// This function takes the divide value and the bandwidth setting of the PLL
// and outputs the digital filter settings necessary.
function [9:0] mmcm_pll_filter_lookup
(
input [6:0] divide, // Max divide is 64
input [8*9:0] BANDWIDTH
);
reg [639:0] lookup_low;
reg [639:0] lookup_high;
reg [9:0] lookup_entry;
begin
lookup_low = {
// CP_RES_LFHF
10'b0010_1111_00,
10'b0010_1111_00,
10'b0010_0111_00,
10'b0010_1101_00,
10'b0010_0101_00,
10'b0010_0101_00,
10'b0010_1001_00,
10'b0010_1110_00,
10'b0010_1110_00,
10'b0010_0001_00,
10'b0010_0001_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_0110_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1010_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_1100_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0010_0010_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0011_1100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00
};
lookup_high = {
// CP_RES_LFHF
10'b0011_0111_00,
10'b0011_0111_00,
10'b0101_1111_00,
10'b0111_1111_00,
10'b0111_1011_00,
10'b1101_0111_00,
10'b1110_1011_00,
10'b1110_1101_00,
10'b1111_1101_00,
10'b1111_0111_00,
10'b1111_1011_00,
10'b1111_1101_00,
10'b1111_0011_00,
10'b1110_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b1111_0101_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0111_0110_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b0101_1100_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b1100_0001_00,
10'b0100_0010_00,
10'b0100_0010_00,
10'b0100_0010_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0011_0100_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0010_1000_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0100_1100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00,
10'b0010_0100_00
};
// Set lookup_entry with the explicit bits from lookup with a part select
if(BANDWIDTH == "LOW") begin
// Low Bandwidth
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
end else begin
// High or optimized bandwidth
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
end
`ifdef DEBUG
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
`endif
end
endfunction
// This function takes in the divide, phase, and duty cycle
// setting to calculate the upper and lower counter registers.
function [37:0] mmcm_pll_count_calc
(
input [7:0] divide, // Max divide is 128
input signed [31:0] phase,
input [31:0] duty_cycle // Multiplied by 100,000
);
reg [13:0] div_calc;
reg [16:0] phase_calc;
begin
`ifdef DEBUG
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
divide, phase, duty_cycle);
`endif
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
div_calc = mmcm_pll_divider(divide, duty_cycle);
// mx[10:9], pm[8:6], dt[5:0]
phase_calc = mmcm_pll_phase(divide, phase);
// Return value is the upper and lower address of counter
// Upper address is:
// RESERVED [31:26]
// MX [25:24]
// EDGE [23]
// NOCOUNT [22]
// DELAY_TIME [21:16]
// Lower Address is:
// PHASE_MUX [15:13]
// RESERVED [12]
// HIGH_TIME [11:6]
// LOW_TIME [5:0]
`ifdef DEBUG
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
div_calc[13], div_calc[12],
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
`endif
mmcm_pll_count_calc =
{
// Upper Address
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
// Lower Address
phase_calc[8:6], 1'b0, div_calc[11:0]
};
end
endfunction
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt 0 → 100644
View file @ da45ac30
################################################################################
# Vivado (TM) v2024.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./clk_wiz_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './clk_wiz_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh 0 → 100755
View file @ da45ac30
#!/usr/bin/env bash
#**********************************************************************************************************
# Vivado (TM) v2024.1 (64-bit)
#
# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Filename : clk_wiz_0.sh
# Simulator : Aldec Active-HDL Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : clk_wiz_0.sh
# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# clk_wiz_0.sh [-reset_run]
# clk_wiz_0.sh [-reset_log]
# clk_wiz_0.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'clk_wiz_0.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# script info
echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# map simulator index file
map_setup_file
fi
}
# map library.cfg file
map_setup_file()
{
file="library.cfg"
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: clk_wiz_0.sh [-help]\n\
Usage: clk_wiz_0.sh [-step]\n\
Usage: clk_wiz_0.sh [-lib_map_path]\n\
Usage: clk_wiz_0.sh [-reset_run]\n\
Usage: clk_wiz_0.sh [-reset_log]\n\
Usage: clk_wiz_0.sh [-keep_index]\n\
Usage: clk_wiz_0.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do 0 → 100644
View file @ da45ac30
transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
vlib work
vlib activehdl/xpm
vlib activehdl/xil_defaultlib
vmap xpm activehdl/xpm
vmap xil_defaultlib activehdl/xil_defaultlib
vlog -work xpm -sv2k12 "+incdir+../../../ipstatic" -l xpm -l xil_defaultlib \
"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
vcom -work xpm - \
"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" -l xpm -l xil_defaultlib \
"../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
"../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
vlog -work xil_defaultlib \
"glbl.v"
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt 0 → 100644
View file @ da45ac30
xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v 0 → 100755
View file @ da45ac30
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do 0 → 100644
View file @ da45ac30
transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O2 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
do {clk_wiz_0.udo}
run
endsim
quit -force
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt 0 → 100644
View file @ da45ac30
################################################################################
# Vivado (TM) v2024.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./clk_wiz_0.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './clk_wiz_0.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt 0 → 100644
View file @ da45ac30
xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do 0 → 100644
View file @ da45ac30
add wave *
add wave /glbl/GSR