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control_unit.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity controlUnit is
+
+  port (
+    I_clock               : in  std_logic;  -- global clock
+    I_reset               : in  std_logic;  -- asynchronous global reset
+    I_inputSampleValid    : in  std_logic;  -- Control signal to load the input sample in the sample shift register and shift the register
+    I_processingDone      : in  std_logic;
+    O_loadShift           : out std_logic;  -- filtered sample
+    O_initAddress         : out std_logic;  -- Control signal to initialize register read address
+    O_incrAddress         : out std_logic;  -- Control signal to increment register read address
+    O_initSum             : out std_logic;  -- Control signal to initialize the MAC register
+    O_loadSum             : out std_logic;  -- Control signal to load the MAC register to Sum;
+    O_loadSubstraction    : out std_logic;  -- Control signal to load the MAC register to substraction;
+    O_loadR               : out std_logic;  -- Control signal to load R register
+    O_FilteredSampleValid : out std_logic ; -- Data valid signal for filtered sample
+    O_Selector            : out std_logic_vector(1 downto 0);
+    );
+
+end entity controlUnit;
+architecture archi_operativeUnit of controlUnit is
+
+
+  type T_state is (WAIT_SAMPLE, STORE_X, STORE_Y, STORE_Z, STORE_inter, PROCESSING_LOOP_Y, PROCESSING_LOOP_Z,PROCESSING_LOOP_Backward_Z, PROCESSING_LOOP_R, OUTPUT, WAIT_END_SAMPLE);  -- state list
+  signal SR_presentState : T_state;
+  signal SR_futurState   : T_state;
+
+begin
+
+  process (I_reset, I_clock) is
+  begin
+    if I_reset = '1' then               -- asynchronous reset (active high)
+      SR_presentState <= WAIT_SAMPLE;
+    elsif rising_edge(I_clock) then     -- rising clock edge
+      SR_presentState <= SR_futurState;
+    end if;
+  end process;
+
+  process (SR_presentState, I_inputSampleValid, I_processingDone) is
+  begin
+    case SR_presentState is
+
+      when WAIT_SAMPLE =>
+          if (I_inputSampleValid = '1') then
+            SR_futurState <= STORE_X;
+          end if;
+       
+      when STORE_X =>
+         SR_futurState <= PROCESSING_LOOP_Y;
+     
+      when PROCESSING_LOOP_Y =>
+          if (I_processingDone = '1') then
+            SR_futurState <= STORE_Y;
+          end if;
+   
+      when STORE_Y =>
+          SR_futurState <= PROCESSING_LOOP_Z;
+          
+         
+      when PROCESSING_LOOP_Z =>
+        if (I_processingDone = '1') then
+            SR_futurState <= STORE_inter;
+          end if;
+          
+          
+      when STORE_inter =>
+          SR_futurState <= PROCESSING_LOOP_Backward_Z;
+          
+      when PROCESSING_LOOP_Backward_Z =>
+          if (I_processingDone = '1') then
+            SR_futurState <= STORE_Z;
+          end if;  
+          
+     when STORE_Z =>
+          SR_futurState <= PROCESSING_LOOP_R;
+          
+      when PROCESSING_LOOP_R =>
+          if (I_processingDone = '1') then
+            SR_futurState <= OUTPUT;
+          end if;
+     
+      when OUTPUT =>
+          SR_futurState <= WAIT_END_SAMPLE;
+     
+      when WAIT_END_SAMPLE =>
+          if (I_inputSampleValid = '1') then
+            SR_futurState <= WAIT_SAMPLE;
+          else
+            SR_futurState <= WAIT_END_SAMPLE;
+          end if;
+
+      when others => null;
+    end case;
+  end process;
+
+  O_loadShift           <= '1' when SR_presentState=STORE_X else '0';
+  O_initAddress         <= '1' when (SR_presentState=STORE_X OR SR_presentState=STORE_Y OR SR_presentState=STORE_Z) else '0';
+  O_incrAddress         <= '1' when (SR_presentState=PROCESSING_LOOP_Y OR SR_presentState=PROCESSING_LOOP_Z OR SR_presentState=PROCESSING_LOOP_R) else '0';
+  O_initSum             <= '1' when SR_presentState=STORE_Z OR SR_presentState=STORE_X else '0';
+  O_loadSum             <= '1' when (SR_presentState=PROCESSING_LOOP_Y OR SR_presentState=PROCESSING_LOOP_Z OR SR_presentState=PROCESSING_LOOP_R)else '0';
+  O_loadSubstraction    <= '1' when SR_presentState=PROCESSING_LOOP_Backward_Z else '0';
+  O_loadR               <= '1' when SR_presentState=OUTPUT else '0';
+  O_FilteredSampleValid <= '1' when SR_presentState=WAIT_END_SAMPLE else '0';
+  Selector              <= '01' when (SR_presentState=STORE_Y OR SR_presentState=PROCESSING_LOOP_Z) else '10' when (SR_presentState=PROCESSING_LOOP_Backward_Z OR SR_presentState=STORE_inter) else '11' when (SR_presentState=STORE_Z OR SR_presentState=PROCESSING_LOOP_R  OR SR_presentState=OUTPUT OR SR_presentState=WAIT_END_SAMPLE ) else '00';
+
+
+
+
+end architecture archi_operativeUnit;