Update files

src/hdl/controlUnit.vhd

@@ -49,33 +49,92 @@ architecture archi_operativeUnit of controlUnit is
 
 begin
 
-  process (_BLANK_) is
+  process (I_reset, I_clock) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
-      SR_presentState <= _BLANK_
+      SR_presentState <= WAIT_SAMPLE;
     elsif rising_edge(I_clock) then     -- rising clock edge
-      _BLANK_
+      SR_presentState <= SR_futurState;
     end if;
   end process;
 
-  process (_BLANK_) is
+  process (SR_presentState, I_inputSampleValid, I_processingDone) is
   begin
     case SR_presentState is
 
       when WAIT_SAMPLE =>
-        _BLANK_
+        O_loadShift <= '0';
+        O_initAddress <= '0';
+        O_incrAddress <= '0';
+        O_initSum <= '0';
+        O_loadSum <= '0';
+        O_loadY <= '0';
+      
+        if(I_inputSampleValid = '1')then
+            SR_futurState <= STORE;
+        else
+            SR_futurState <= WAIT_SAMPLE;
+        end if;
+            
+      when STORE =>
+        O_loadShift <= '1';
+        O_initAddress <= '1';
+        O_incrAddress <= '0';
+        O_initSum <= '1';
+        O_loadSum <= '0';
+        O_loadY <= '0';
+        
+        SR_futurState <= PROCESSING_LOOP;
+            
+      when PROCESSING_LOOP =>
+        O_loadShift <= '0';
+        O_initAddress <= '0';
+        O_incrAddress <= '1';
+        O_initSum <= '0';
+        O_loadSum <= '1';
+        O_loadY <= '0';
+        
+        if(I_processingDone = '1')then
+            SR_futurState <= OUTPUT;
+        else
+            SR_futurState <= PROCESSING_LOOP;
+        end if;
+            
+      when OUTPUT =>
+        O_loadShift <= '0';
+        O_initAddress <= '0';
+        O_incrAddress <= '0';
+        O_initSum <= '0';
+        O_loadSum <= '0';
+        O_loadY <= '1';
+        
+        SR_futurState <= WAIT_END_SAMPLE;
+            
+      when WAIT_END_SAMPLE =>
+        O_loadShift <= '0';
+        O_initAddress <= '0';
+        O_incrAddress <= '0';
+        O_initSum <= '0';
+        O_loadSum <= '0';
+        O_loadY <= '0';
+        
+        if(I_inputSampleValid = '0')then
+            SR_futurState <= WAIT_SAMPLE;
+        else
+            SR_futurState <= WAIT_END_SAMPLE;
+        end if;
 
       when others => null;
     end case;
   end process;
 
-  O_loadShift           <= '1' when _BLANK_ ;
-  O_initAddress         <= '1' when _BLANK_ ;
-  O_incrAddress         <= '1' when _BLANK_ ;
-  O_initSum             <= '1' when _BLANK_ ;
-  O_loadSum             <= '1' when _BLANK_ ;
-  O_loadY               <= '1' when _BLANK_ ;
-  O_FilteredSampleValid <= '1' when _BLANK_ ;
+--  O_loadShift           <= '1' when SR_presentState = STORE else '0';
+--  O_initAddress         <= '1' when _BLANK_ ;
+--  O_incrAddress         <= '1' when _BLANK_ ;
+--  O_initSum             <= '1' when _BLANK_ ;
+--  O_loadSum             <= '1' when _BLANK_ ;
+--  O_loadY               <= '1' when _BLANK_ ;
+--  O_FilteredSampleValid <= '1' when _BLANK_ ;
 
 
 

src/hdl/operativeUnit.vhd

@@ -85,12 +85,17 @@ begin
                       to_signed(2, 8)
                       );
 
-  shift : process (_BLANK_) is
+  shift : process (I_reset, I_clock) is
   begin  -- process shift
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_shiftRegister <= (others => (others => '0'));
-    elsif _BLANK_
-
+    elsif rising_edge(I_clock) then
+        if(I_loadShift = '1')then
+            SR_shiftRegister <= I_inputSample;
+        else
+            SR_shiftRegister(6 downto 0) <= SR_shiftRegister(7 downto 1);
+            SR_shiftRegister(7) <= I_inputSample;
+        end if;
     end if;
   end process shift;