test

src/controlUnit.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/26/2025 04:14:55 PM
+-- Design Name: 
+-- Module Name: controlUnit - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity controlUnit is
+--  Port ( );
+
+port (
+    I_clock                   : in  std_logic;  -- global clock
+    I_reset                   : in  std_logic;  -- asynchronous global reset
+    I_inputSampleValid        : in  std_logic;  -- Control signal to load the input sample in the sample shift register and shift the register
+    I_processingDone_FIR1     : in  std_logic;
+    I_processingDone_X_IIR    : in  std_logic;
+    I_processingDone_Y_IIR    : in  std_logic;
+    I_processingDone_FIR2     : in  std_logic;
+    O_loadShift_FIR1          : out std_logic;  -- filtered sample
+    O_loadShift_IIR           : out std_logic;  -- filtered sample
+    O_loadShift_FIR2          : out std_logic;  -- filtered sample
+    O_initAddress             : out std_logic;  -- Control signal to initialize register read address
+    O_incrAddress             : out std_logic;  -- Control signal to increment register read address
+    O_initSum                 : out std_logic;  -- Control signal to initialize the MAC register
+    O_loadSum                 : out std_logic;  -- Control signal to load the MAC register;
+    O_loadOutput              : out std_logic;  -- Control signal to load Y register
+    O_sel                     : out std_logic_vector(1 downto 0);
+    O_FilteredSampleValid     : out std_logic  -- Data valid signal for filtered sample
+    );
+end controlUnit;
+
+architecture Behavioral of controlUnit is
+
+
+type T_state is (WAIT_SAMPLE, STORE_FIR1, PROCESSING_LOOP_FIR1, STORE_IIR, PROCESSING_LOOP_X_IIR, INIT_Y, 
+  PROCESSING_LOOP_Y_IIR, STORE_FIR2, PROCESSING_LOOP_FIR2, OUTPUT, WAIT_END_SAMPLE);  -- state list
+  signal SR_presentState : T_state; 
+  signal SR_futurState   : T_state;
+
+begin
+
+  process (I_clock,I_reset) is
+  begin
+    if I_reset = '1' then               -- asynchronous reset (active high)
+      SR_presentState <= WAIT_SAMPLE;
+    elsif rising_edge(I_clock) then     -- rising clock edge
+      SR_presentState <= SR_futurState; 
+    end if;
+  end process;
+
+  process (SR_presentState,I_inputSampleValid,I_processingDone_FIR1,I_processingDone_X_IIR,I_processingDone_Y_IIR,I_processingDone_FIR2) is
+  begin
+    case SR_presentState is
+
+      when WAIT_SAMPLE =>
+      if I_inputSampleValid = '1' then
+         SR_futurState <= STORE_FIR1;
+      else
+        SR_futurState <= WAIT_SAMPLE;
+      end if;  
+      
+      when STORE_FIR1 =>
+        O_sel <= "00";
+        SR_futurState <= PROCESSING_LOOP_FIR1;
+        
+      when PROCESSING_LOOP_FIR1 => 
+        if I_processingDone_FIR1  = '1' then
+            SR_futurState <= STORE_IIR;
+        else
+            SR_futurState <= PROCESSING_LOOP_FIR1;
+        end if;  
+        
+      when STORE_IIR => 
+         O_sel <= "01";
+         SR_futurState <= PROCESSING_LOOP_X_IIR;
+            
+      when PROCESSING_LOOP_X_IIR => 
+        if I_processingDone_X_IIR  = '1' then
+            SR_futurState <= INIT_Y;
+        else
+            SR_futurState <= PROCESSING_LOOP_X_IIR;
+        end if; 
+      
+      when INIT_Y =>
+        O_sel <= "10";
+        SR_futurState <= PROCESSING_LOOP_Y_IIR;
+        
+      when PROCESSING_LOOP_Y_IIR => 
+        if I_processingDone_Y_IIR  = '1' then
+            SR_futurState <= STORE_FIR2;
+        else
+            SR_futurState <= PROCESSING_LOOP_Y_IIR;
+        end if; 
+        
+      when STORE_FIR2 =>
+        O_sel <= "11";
+        SR_futurState <= PROCESSING_LOOP_FIR2;
+      
+      when PROCESSING_LOOP_FIR2 => 
+        if I_processingDone_FIR2  = '1' then
+            SR_futurState <= OUTPUT;
+        else
+            SR_futurState <= PROCESSING_LOOP_FIR2;
+        end if; 
+      
+      when OUTPUT =>
+        SR_futurState <= WAIT_END_SAMPLE;
+      
+      when WAIT_END_SAMPLE =>
+        if I_inputSampleValid = '0' then
+            SR_futurState <= WAIT_SAMPLE;
+        else
+            SR_futurState <= WAIT_END_SAMPLE;
+        end if;
+        
+      when others => 
+        SR_futurState <= WAIT_SAMPLE;
+    end case;
+  end process;
+
+
+
+  O_loadShift_FIR1      <= '1' when SR_presentState = STORE_FIR1 else '0' ;
+  O_loadShift_IIR       <= '1' when SR_presentState = STORE_IIR else '0' ;
+  O_loadShift_FIR2      <= '1' when SR_presentState = STORE_FIR2 else '0' ;
+  O_initAddress         <= '1' when SR_presentState = STORE_FIR1 OR SR_presentState = STORE_IIR OR SR_presentState = STORE_FIR2 else '0' ;
+  O_incrAddress         <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR SR_presentState = PROCESSING_LOOP_X_IIR OR SR_presentState = PROCESSING_LOOP_Y_IIR OR SR_presentState = PROCESSING_LOOP_FIR2 else '0' ;
+  O_initSum             <= '1' when SR_presentState = STORE_FIR1 OR SR_presentState = STORE_IIR OR SR_presentState = STORE_FIR2 else '0' ;
+  O_loadSum             <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR SR_presentState = PROCESSING_LOOP_X_IIR OR SR_presentState = PROCESSING_LOOP_Y_IIR OR SR_presentState = PROCESSING_LOOP_FIR2 else '0' ;
+  O_loadOutput          <= '1' when SR_presentState = OUTPUT else '0' ;  
+ -- O_FilteredSampleValid <= '1' when _BLANK_ ; ????
+
+end architecture Behavioral;
+
+

src/operativeUnit.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/26/2025 04:22:28 PM
+-- Design Name: 
+-- Module Name: operativeUnit - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity operativeUnit is
+--  Port ( );
+end operativeUnit;
+
+architecture Behavioral of operativeUnit is
+    type registerFile is array(0 to 94) of signed(10 downto 0);
+    signal SR_coefRegister_FIR1 : registerFile;
+
+begin
+
+SR_coefRegister_FIR1 <= (to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-2, 11),
+    to_signed(-2, 11),
+    to_signed(-2, 11),
+    to_signed(-3, 11),
+    to_signed(-3, 11),
+    to_signed(-3, 11),
+    to_signed(-4, 11),
+    to_signed(-4, 11),
+    to_signed(-5, 11),
+    to_signed(-5, 11),
+    to_signed(-6, 11),
+    to_signed(-6, 11),
+    to_signed(-7, 11),
+    to_signed(-7, 11),
+    to_signed(-8, 11),
+    to_signed(-8, 11),
+    to_signed(-9, 11),
+    to_signed(-10, 11),
+    to_signed(-10, 11),
+    to_signed(-11, 11),
+    to_signed(-11, 11),
+    to_signed(-12, 11),
+    to_signed(-13, 11),
+    to_signed(-13, 11),
+    to_signed(-14, 11),
+    to_signed(-14, 11),
+    to_signed(-15, 11),
+    to_signed(-15, 11),
+    to_signed(-16, 11),
+    to_signed(-16, 11),
+    to_signed(-17, 11),
+    to_signed(-17, 11),
+    to_signed(-18, 11),
+    to_signed(-18, 11),
+    to_signed(-18, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(1004, 121,
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-19, 11),
+    to_signed(-18, 11),
+    to_signed(-18, 11),
+    to_signed(-18, 11),
+    to_signed(-17, 11),
+    to_signed(-17, 11),
+    to_signed(-16, 11),
+    to_signed(-16, 11),
+    to_signed(-15, 11),
+    to_signed(-15, 11),
+    to_signed(-14, 11),
+    to_signed(-14, 11),
+    to_signed(-13, 11),
+    to_signed(-13, 11),
+    to_signed(-12, 11),
+    to_signed(-11, 11),
+    to_signed(-11, 11),
+    to_signed(-10, 11),
+    to_signed(-10, 11),
+    to_signed(-9, 11),
+    to_signed(-8, 11),
+    to_signed(-8, 11),
+    to_signed(-7, 11),
+    to_signed(-7, 11),
+    to_signed(-6, 11),
+    to_signed(-6, 11),
+    to_signed(-5, 11),
+    to_signed(-5, 11),
+    to_signed(-4, 11),
+    to_signed(-4, 11),
+    to_signed(-3, 11),
+    to_signed(-3, 11),
+    to_signed(-3, 11),
+    to_signed(-2, 11),
+    to_signed(-2, 11),
+    to_signed(-2, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11),
+    to_signed(-1, 11)
+    );
+
+
+
+
+end Behavioral;