Skip to content
Snippets Groups Projects
Commit e7521bf2 authored by Jean-Noël Bazin's avatar Jean-Noël Bazin
Browse files

suppression reset asynchrone

parent fe579534
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
src/hdl/controlUnit.vhd
+ 46
− 50
View file @ e7521bf2
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> -- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company : -- Company :
-- Created : 2018-04-11 -- Created : 2018-04-11
-- Last update: 2019-02-13 -- Last update: 2024-03-26
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -24,61 +24,57 @@ use ieee.std_logic_1164.all; ...@@ -24,61 +24,57 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
entity controlUnit is entity controlUnit is
port (
port ( I_clock : in std_logic; -- global clock
I_clock : in std_logic; -- global clock I_GlobalInit : in std_logic; -- asynchronous global reset
I_reset : in std_logic; -- asynchronous global reset I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register I_processingDone : in std_logic;
I_processingDone : in std_logic; O_loadShift : out std_logic; -- filtered sample
O_loadShift : out std_logic; -- filtered sample O_initAddress : out std_logic; -- Control signal to initialize register read address
O_initAddress : out std_logic; -- Control signal to initialize register read address O_incrAddress : out std_logic; -- Control signal to increment register read address
O_incrAddress : out std_logic; -- Control signal to increment register read address O_initSum : out std_logic; -- Control signal to initialize the MAC register
O_initSum : out std_logic; -- Control signal to initialize the MAC register O_loadSum : out std_logic; -- Control signal to load the MAC register;
O_loadSum : out std_logic; -- Control signal to load the MAC register; O_loadY : out std_logic; -- Control signal to load Y register
O_loadY : out std_logic; -- Control signal to load Y register O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample );
);
end entity controlUnit; end entity controlUnit;
architecture archi_operativeUnit of controlUnit is architecture archi_operativeUnit of controlUnit is
type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE); -- state list
type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE); -- state list signal SR_presentState : T_state;
signal SR_presentState : T_state; signal SR_futurState : T_state;
signal SR_futurState : T_state;
begin begin
process (_BLANK_) is -- Register for Present state
begin process (_BLANK_) is
if I_reset = '1' then -- asynchronous reset (active high) begin
SR_presentState <= _BLANK_ if rising_edge(I_clock) then
elsif rising_edge(I_clock) then -- rising clock edge _BLANK_
_BLANK_ end if;
end if; end process;
end process;
-- Compute futur state
process (_BLANK_) is process (_BLANK_) is
begin begin
case SR_presentState is case SR_presentState is
when WAIT_SAMPLE => when WAIT_SAMPLE =>
_BLANK_ _BLANK_
when others => null; when others => null;
end case; end case;
end process; end process;
O_loadShift <= '1' when _BLANK_ ; -- Compute the outputs
O_initAddress <= '1' when _BLANK_ ; O_loadShift <= '1' when _BLANK_;
O_incrAddress <= '1' when _BLANK_ ; O_initAddress <= '1' when _BLANK_;
O_initSum <= '1' when _BLANK_ ; O_incrAddress <= '1' when _BLANK_;
O_loadSum <= '1' when _BLANK_ ; O_initSum <= '1' when _BLANK_;
O_loadY <= '1' when _BLANK_ ; O_loadSum <= '1' when _BLANK_;
O_FilteredSampleValid <= '1' when _BLANK_ ; O_loadY <= '1' when _BLANK_;
O_FilteredSampleValid <= '1' when _BLANK_;
end architecture archi_operativeUnit; end architecture archi_operativeUnit;
src/hdl/fir.vhd
+ 68
− 60
View file @ e7521bf2
...@@ -4,87 +4,95 @@ use ieee.numeric_std.all; ...@@ -4,87 +4,95 @@ use ieee.numeric_std.all;
entity fir is entity fir is
generic ( generic (
dwidth : natural := 18; dwidth : natural := 18;
ntaps : natural := 15); ntaps : natural := 15);
port ( port (
din : in std_logic_vector(dwidth-1 downto 0); din : in std_logic_vector(dwidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0); dout : out std_logic_vector(dwidth-1 downto 0);
config_sw : in std_logic_vector(4 downto 0); --inutilise dans le TP majeure config_sw : in std_logic_vector(4 downto 0); --inutilise dans le TP majeure
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
ce : in std_logic; -- signal de validation de din a la frequence des echantillons audio ce : in std_logic; -- signal de validation de din a la frequence des echantillons audio
dbg_output_0 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure dbg_output_0 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
dbg_output_1 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure dbg_output_1 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
dbg_output_2 : out std_logic; --inutilise dans le TP majeure dbg_output_2 : out std_logic; --inutilise dans le TP majeure
dbg_output_3 : out std_logic; --inutilise dans le TP majeure dbg_output_3 : out std_logic; --inutilise dans le TP majeure
dbg_output_4 : out std_logic --inutilise dans le TP majeure dbg_output_4 : out std_logic --inutilise dans le TP majeure
-- dout_valid : out std_logic -- dout_valid : out std_logic
); );
end fir; end fir;
architecture myarch of fir is architecture myarch of fir is
component firUnit is component firUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_GlobalInit : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0); I_inputSample : in std_logic_vector(7 downto 0);
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); O_filteredSample : out std_logic_vector(7 downto 0);
O_filteredSampleValid : out std_logic); O_filteredSampleValid : out std_logic
end component firUnit; );
end component firUnit;
signal D_in, D_out : std_logic_vector(7 downto 0); signal D_in, D_out : std_logic_vector(7 downto 0);
begin -- myarch begin -- myarch
-- Quantization on 8 bits or less -- Quantization on 8 bits or less
-- When config_sw(3)='1', rounding is made by finding the nearest value else rounding is made by truncating. -- When config_sw(3)='1', rounding is made by finding the nearest value else rounding is made by truncating.
prc : process (config_sw(3 downto 0), din) is prc : process (config_sw(3 downto 0), din) is
begin -- process prc begin -- process prc
case to_integer(unsigned(config_sw(3 downto 0))) is case to_integer(unsigned(config_sw(3 downto 0))) is
when 0 => D_in <= din(dwidth-1 downto dwidth -8); when 0 => D_in <= din(dwidth-1 downto dwidth -8);
when 1 => D_in <= din(dwidth-1 downto dwidth -7)&'0'; when 1 => D_in <= din(dwidth-1 downto dwidth -7)&'0';
when 2 => D_in <= din(dwidth-1 downto dwidth -6)&"00"; when 2 => D_in <= din(dwidth-1 downto dwidth -6)&"00";
when 3 => D_in <= din(dwidth-1 downto dwidth -5)&"000"; when 3 => D_in <= din(dwidth-1 downto dwidth -5)&"000";
when 4 => D_in <= din(dwidth-1 downto dwidth -4)&"0000"; when 4 => D_in <= din(dwidth-1 downto dwidth -4)&"0000";
when 5 => D_in <= din(dwidth-1 downto dwidth -3)&"00000"; when 5 => D_in <= din(dwidth-1 downto dwidth -3)&"00000";
when 6 => D_in <= din(dwidth-1 downto dwidth -2)&"000000"; when 6 => D_in <= din(dwidth-1 downto dwidth -2)&"000000";
when 7 => D_in <= din(dwidth-1)&"0000000"; when 7 => D_in <= din(dwidth-1)&"0000000";
when 8 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -8);else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -8))+1); end if; when 8 =>
when 9 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -7)&'0'; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -7))+1)&'0'; end if; if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -8); else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -8))+1); end if;
when 10 => if din(dwidth-7) = '0' then D_in <= din(dwidth-1 downto dwidth -6)&"00"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -6))+1)&"00"; end if; when 9 =>
when 11 => if din(dwidth-6) = '0' then D_in <= din(dwidth-1 downto dwidth -5)&"000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -5))+1)&"000"; end if; if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -7)&'0'; else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -7))+1)&'0'; end if;
when 12 => if din(dwidth-5) = '0' then D_in <= din(dwidth-1 downto dwidth -4)&"0000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -4))+1)&"0000"; end if; when 10 =>
when 13 => if din(dwidth-4) = '0' then D_in <= din(dwidth-1 downto dwidth -3)&"00000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -3))+1)&"00000"; end if; if din(dwidth-7) = '0' then D_in <= din(dwidth-1 downto dwidth -6)&"00"; else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -6))+1)&"00"; end if;
when 14 => if din(dwidth-3) = '0' then D_in <= din(dwidth-1 downto dwidth -2)&"000000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -2))+1)&"000000"; end if; when 11 =>
when 15 => D_in <= din(dwidth-1)&"0000000"; if din(dwidth-6) = '0' then D_in <= din(dwidth-1 downto dwidth -5)&"000"; else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -5))+1)&"000"; end if;
when others => D_in <= (others => '0'); when 12 =>
end case; if din(dwidth-5) = '0' then D_in <= din(dwidth-1 downto dwidth -4)&"0000"; else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -4))+1)&"0000"; end if;
end process prc; when 13 =>
if din(dwidth-4) = '0' then D_in <= din(dwidth-1 downto dwidth -3)&"00000"; else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -3))+1)&"00000"; end if;
when 14 =>
if din(dwidth-3) = '0' then D_in <= din(dwidth-1 downto dwidth -2)&"000000"; else D_in <= std_logic_vector(signed(din(dwidth-1 downto dwidth -2))+1)&"000000"; end if;
when 15 => D_in <= din(dwidth-1)&"0000000";
when others => D_in <= (others => '0');
end case;
end process prc;
--FIR over 8 bits --FIR over 8 bits
firUnit_1 : entity work.firUnit firUnit_1 : entity work.firUnit
port map ( port map (
I_clock => clk, I_clock => clk,
I_reset => rst, I_GlobalInit => rst,
I_inputSample => D_in, I_inputSample => D_in,
I_inputSampleValid => ce, I_inputSampleValid => ce,
O_filteredSample => D_out, O_filteredSample => D_out,
O_filteredSampleValid => open); O_filteredSampleValid => open);
-- End of FIR -- End of FIR
dout(dwidth-1 downto dwidth -8) <= D_out when config_sw(4) = '1' else D_in; dout(dwidth-1 downto dwidth -8) <= D_out when config_sw(4) = '1' else D_in;
dout(dwidth-9 downto 0) <= (others => '0'); dout(dwidth-9 downto 0) <= (others => '0');
......
src/hdl/firUnit.vhd
+ 72
− 74
View file @ e7521bf2
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Title : firUnit -- Title : firUnit
-- Project : -- Project :
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : operativeUnit.vhd -- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> -- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company : -- Company :
-- Created : 2018-04-11 -- Created : 2018-04-11
-- Last update: 2018-04-11 -- Last update: 2024-03-26
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: 8 bit FIR -- Description: 8 bit FIR
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2018 -- Copyright (c) 2018
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
...@@ -25,85 +25,83 @@ use ieee.numeric_std.all; ...@@ -25,85 +25,83 @@ use ieee.numeric_std.all;
entity firUnit is entity firUnit is
port ( port (
I_clock : in std_logic; -- global clock I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset I_GlobalInit : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic O_filteredSampleValid : out std_logic
); );
end entity firUnit; end entity firUnit;
architecture archi_firUnit of firUnit is architecture archi_firUnit of firUnit is
component controlUnit is component controlUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_GlobalInit : in std_logic;
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
I_processingDone : in std_logic; I_processingDone : in std_logic;
O_loadShift : out std_logic; O_loadShift : out std_logic;
O_initAddress : out std_logic; O_initAddress : out std_logic;
O_incrAddress : out std_logic; O_incrAddress : out std_logic;
O_initSum : out std_logic; O_initSum : out std_logic;
O_loadSum : out std_logic; O_loadSum : out std_logic;
O_loadY : out std_logic; O_loadY : out std_logic;
O_FilteredSampleValid : out std_logic); O_FilteredSampleValid : out std_logic);
end component controlUnit; end component controlUnit;
component operativeUnit is component operativeUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_inputSample : in std_logic_vector(7 downto 0);
I_inputSample : in std_logic_vector(7 downto 0); I_loadShift : in std_logic;
I_loadShift : in std_logic; I_initAddress : in std_logic;
I_initAddress : in std_logic; I_incrAddress : in std_logic;
I_incrAddress : in std_logic; I_initSum : in std_logic;
I_initSum : in std_logic; I_loadSum : in std_logic;
I_loadSum : in std_logic; I_loadY : in std_logic;
I_loadY : in std_logic; O_processingDone : out std_logic;
O_processingDone : out std_logic; O_Y : out std_logic_vector(7 downto 0));
O_Y : out std_logic_vector(7 downto 0)); end component operativeUnit;
end component operativeUnit;
signal SC_processingDone : std_logic; signal SC_processingDone : std_logic;
signal SC_loadShift : std_logic; signal SC_loadShift : std_logic;
signal SC_initAddress : std_logic; signal SC_initAddress : std_logic;
signal SC_incrAddress : std_logic; signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic; signal SC_initSum : std_logic;
signal SC_loadSum : std_logic; signal SC_loadSum : std_logic;
signal SC_loadY : std_logic; signal SC_loadY : std_logic;
begin begin
controlUnit_1 : entity work.controlUnit controlUnit_1 : entity work.controlUnit
port map ( port map (
I_clock => I_clock, I_clock => I_clock,
I_reset => I_reset, I_GlobalInit => I_GlobalInit,
I_inputSampleValid => I_inputSampleValid, I_inputSampleValid => I_inputSampleValid,
I_processingDone => SC_processingDone, I_processingDone => SC_processingDone,
O_loadShift => SC_loadShift, O_loadShift => SC_loadShift,
O_initAddress => SC_initAddress, O_initAddress => SC_initAddress,
O_incrAddress => SC_incrAddress, O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum, O_initSum => SC_initSum,
O_loadSum => SC_loadSum, O_loadSum => SC_loadSum,
O_loadY => SC_loadY, O_loadY => SC_loadY,
O_FilteredSampleValid => O_FilteredSampleValid); O_FilteredSampleValid => O_FilteredSampleValid);
operativeUnit_1 : entity work.operativeUnit operativeUnit_1 : entity work.operativeUnit
port map ( port map (
I_clock => I_clock, I_clock => I_clock,
I_reset => I_reset, I_inputSample => I_inputSample,
I_inputSample => I_inputSample, I_loadShift => SC_loadShift,
I_loadShift => SC_loadShift, I_initAddress => SC_initAddress,
I_initAddress => SC_initAddress, I_incrAddress => SC_incrAddress,
I_incrAddress => SC_incrAddress, I_initSum => SC_initSum,
I_initSum => SC_initSum, I_loadSum => SC_loadSum,
I_loadSum => SC_loadSum, I_loadY => SC_loadY,
I_loadY => SC_loadY, O_processingDone => SC_processingDone,
O_processingDone => SC_processingDone, O_Y => O_filteredSample);
O_Y => O_filteredSample);
end architecture archi_firUnit; end architecture archi_firUnit;
src/hdl/operativeUnit.vhd
+ 6
− 15
View file @ e7521bf2
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> -- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company : -- Company :
-- Created : 2018-04-11 -- Created : 2018-04-11
-- Last update: 2019-02-13 -- Last update: 2024-03-26
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -33,7 +33,6 @@ entity operativeUnit is ...@@ -33,7 +33,6 @@ entity operativeUnit is
port ( port (
I_clock : in std_logic; -- global clock I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_initAddress : in std_logic; -- Control signal to initialize register read address I_initAddress : in std_logic; -- Control signal to initialize register read address
...@@ -49,8 +48,8 @@ end entity operativeUnit; ...@@ -49,8 +48,8 @@ end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is architecture arch_operativeUnit of operativeUnit is
type registerFile is array(0 to 15) of signed(7 downto 0); type registerFile is array(0 to 15) of signed(7 downto 0);
signal SR_coefRegister : registerFile;
signal SR_coefRegister : registerFile;
signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples
signal SC_multOperand1 : signed(7 downto 0); signal SC_multOperand1 : signed(7 downto 0);
...@@ -61,8 +60,6 @@ architecture arch_operativeUnit of operativeUnit is ...@@ -61,8 +60,6 @@ architecture arch_operativeUnit of operativeUnit is
signal SR_Y : signed(7 downto 0); -- filtered sample storage register signal SR_Y : signed(7 downto 0); -- filtered sample storage register
signal SR_readAddress : integer range 0 to 15; -- register files read address signal SR_readAddress : integer range 0 to 15; -- register files read address
begin begin
-- Low-pass filter provided with octave (or Matlab ;)) command -- Low-pass filter provided with octave (or Matlab ;)) command
...@@ -86,19 +83,15 @@ begin ...@@ -86,19 +83,15 @@ begin
); );
shift : process (_BLANK_) is shift : process (_BLANK_) is
begin -- process shift begin
if I_reset = '1' then -- asynchronous reset (active high) if rising_edge(I_clock) then
SR_shiftRegister <= (others => (others => '0'));
elsif _BLANK_
end if; end if;
end process shift; end process shift;
incr_address : process (_BLANK_) is incr_address : process (_BLANK_) is
begin begin
if I_reset = '1' then -- asynchronous reset (active high) if _BLANK_
SR_readAddress <= 0;
elsif _BLANK_
end if; end if;
end process incr_address; end process incr_address;
...@@ -112,9 +105,7 @@ begin ...@@ -112,9 +105,7 @@ begin
sum_acc : process (_BLANK_) is sum_acc : process (_BLANK_) is
begin begin
if I_reset = '1' then -- asynchronous reset (active high) if _BLANK_
SR_sum <= (others => '0');
elsif _BLANK_
end if; end if;
end process sum_acc; end process sum_acc;
......
src/hdl/tb_firUnit.vhd
+ 48
− 48
View file @ e7521bf2
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Title : FirUnit -- Title : FirUnit
-- Project : -- Project :
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : operativeUnit.vhd -- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> -- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company : -- Company :
-- Created : 2018-04-11 -- Created : 2018-04-11
-- Last update: 2019-02-26 -- Last update: 2024-03-26
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: 8 bit FIR -- Description: 8 bit FIR
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2018 -- Copyright (c) 2018
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
-- 2018-04-11 1.0 jnbazin Created -- 2018-04-11 1.0 jnbazin Created
-- 2018-04-18 1.1 marzel Modified to add more test inputs -- 2018-04-18 1.1 marzel Modified to add more test inputs
-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering -- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -29,59 +29,59 @@ entity tb_firUnit is ...@@ -29,59 +29,59 @@ entity tb_firUnit is
end entity tb_firUnit; end entity tb_firUnit;
architecture archi_tb_firUnit of tb_firUnit is architecture archi_tb_firUnit of tb_firUnit is
component firUnit is component firUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_GlobalInit : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0); I_inputSample : in std_logic_vector(7 downto 0);
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); O_filteredSample : out std_logic_vector(7 downto 0);
O_filteredSampleValid : out std_logic); O_filteredSampleValid : out std_logic);
end component firUnit; end component firUnit;
signal SC_clock : std_logic := '0'; signal SC_clock : std_logic := '0';
signal SC_reset : std_logic; signal SC_reset : std_logic;
signal SC_inputSample : std_logic_vector(7 downto 0); signal SC_inputSample : std_logic_vector(7 downto 0);
signal SC_inputSampleValid : std_logic:='0'; signal SC_inputSampleValid : std_logic := '0';
signal SC_filteredSample : std_logic_vector(7 downto 0); signal SC_filteredSample : std_logic_vector(7 downto 0);
signal SC_filteredSampleValid : std_logic; signal SC_filteredSampleValid : std_logic;
begin begin
SC_clock <= not SC_clock after 5 ns; SC_clock <= not SC_clock after 5 ns;
SC_reset <= '0', '1' after 19 ns, '0' after 57 ns; SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
-- Sample period = 20 clk period -- Sample period = 20 clk period
SC_inputSampleValid <= not SC_inputSampleValid after 100 ns; SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
-- Null signal followed by a Dirac and then an arbitrary sequence -- Null signal followed by a Dirac and then an arbitrary sequence
SC_inputSample <= "00000000", SC_inputSample <= "00000000",
"01111111" after 401 ns, "01111111" after 401 ns,
"00000000" after 601 ns, "00000000" after 601 ns,
"00100100" after 4201 ns, "00100100" after 4201 ns,
"01100100" after 4401 ns, "01100100" after 4401 ns,
"10100010" after 4601 ns, "10100010" after 4601 ns,
"11011011" after 4801 ns, "11011011" after 4801 ns,
"00001011" after 5001 ns, "00001011" after 5001 ns,
"10000000" after 5201 ns, "10000000" after 5201 ns,
"01111111" after 5401 ns, "01111111" after 5401 ns,
"10111010" after 5601 ns; "10111010" after 5601 ns;
-- the filter output on 8 bits is a sequence of signed numbers (with the assumption -- the filter output on 8 bits is a sequence of signed numbers (with the assumption
-- of rounding the output, so the accuracy can be slightly different depending -- of rounding the output, so the accuracy can be slightly different depending
-- on your final stage): -- on your final stage):
-- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8 -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
-- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116 -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
firUnit_1 : entity work.firUnit
port map ( firUnit_1 : entity work.firUnit
I_clock => SC_clock, port map (
I_reset => SC_reset, I_clock => SC_clock,
I_inputSample => SC_inputSample, I_GlobalInit => SC_reset,
I_inputSampleValid => SC_inputSampleValid, I_inputSample => SC_inputSample,
O_filteredSample => SC_filteredSample, I_inputSampleValid => SC_inputSampleValid,
O_filteredSampleValid => SC_filteredSampleValid); O_filteredSample => SC_filteredSample,
O_filteredSampleValid => SC_filteredSampleValid);
end architecture archi_tb_firUnit; end architecture archi_tb_firUnit;
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment