loto.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity loto is
    generic (
        n_fast : natural := 15;
        n_slow : natural := 25);
    port (
        I_bouton   : in  std_logic;
        I_bloque   : in  std_logic;
        I_clk_100m : in  std_logic;
        I_rst      : in  std_logic;
        O_aff      : out std_logic_vector(6 downto 0);
        O_rouge    : out std_logic;
        O_vert     : out std_logic;
        O_an       : out std_logic_vector(7 downto 0)
        );
end entity loto;

architecture arch of loto is

    component tirage is
        port (
            I_clk         : in  std_logic;
            I_rst         : in  std_logic;
            I_clk_display : in  std_logic;
            I_bouton      : in  std_logic;
            O_reg0        : out std_logic_vector(5 downto 0);
            O_reg1        : out std_logic_vector(5 downto 0);
            O_reg2        : out std_logic_vector(5 downto 0);
            O_reg3        : out std_logic_vector(5 downto 0);
            O_reg4        : out std_logic_vector(5 downto 0);
            O_reg5        : out std_logic_vector(5 downto 0);
            O_l_rouge     : out std_logic;
            O_l_verte     : out std_logic);
    end component tirage;

    component compteur_modulo6 is
        port (
            I_clk         : in  std_logic;
            I_rst         : in  std_logic;
            I_bloque      : in  std_logic;
            O_CounterMod6 : out std_logic_vector(2 downto 0));
    end component compteur_modulo6;

    component diviseur_freq is
        generic (
            n_fast : natural;
            n_slow : natural);
        port (
            I_clk  : in  std_logic;
            I_rst  : in  std_logic;
            O_FAST : out std_logic;
            O_SLOW : out std_logic
            );
    end component diviseur_freq;

    component transcodeur7s_d_u is
        port (
            I_nombre : in  std_logic_vector(5 downto 0);
            O_uni    : out std_logic_vector (6 downto 0);
            O_diz    : out std_logic_vector (6 downto 0)
            );
    end component transcodeur7s_d_u;

    component mux6_1 is
        port (
            I_0    : in  std_logic_vector(5 downto 0);
            I_1    : in  std_logic_vector(5 downto 0);
            I_2    : in  std_logic_vector(5 downto 0);
            I_3    : in  std_logic_vector(5 downto 0);
            I_4    : in  std_logic_vector(5 downto 0);
            I_5    : in  std_logic_vector(5 downto 0);
            I_sel  : in  std_logic_vector(2 downto 0);
            O_mux6 : out std_logic_vector(5 downto 0)
            );
    end component mux6_1;

    component decodeur_uni is
        port (
            I_E   : in  std_logic_vector(2 downto 0);
            O_uni : out std_logic_vector(6 downto 0)
            );
    end component decodeur_uni;

    component modulo4 is
        port (
            I_clk   : in  std_logic;
            I_rst   : in  std_logic;
            O_Mod4  : out std_logic_vector(1 downto 0);
            O_decod : out std_logic_vector(3 downto 0));
    end component modulo4;

    signal SC_clkDisplay   : std_logic;
    signal SC_clk          : std_logic;
    signal SC_reg0         : std_logic_vector(5 downto 0);
    signal SC_reg1         : std_logic_vector(5 downto 0);
    signal SC_reg2         : std_logic_vector(5 downto 0);
    signal SC_reg3         : std_logic_vector(5 downto 0);
    signal SC_reg4         : std_logic_vector(5 downto 0);
    signal SC_reg5         : std_logic_vector(5 downto 0);
    signal SC_num          : std_logic_vector(2 downto 0);
    signal SC_nombre       : std_logic_vector(5 downto 0);
    signal SC_uni          : std_logic_vector(6 downto 0);
    signal SC_diz          : std_logic_vector(6 downto 0);
    signal SC_minus        : std_logic_vector(6 downto 0);
    signal SC_numTranscode : std_logic_vector(6 downto 0);
    signal SC_affSelect    : std_logic_vector(1 downto 0);

begin

    tirage_1 : entity work.tirage
        port map (
            I_clk         => SC_clk,
            I_rst         => I_rst,
            I_clk_display => SC_clkDisplay,
            I_bouton      => I_bouton,
            O_reg0        => SC_reg0,
            O_reg1        => SC_reg1,
            O_reg2        => SC_reg2,
            O_reg3        => SC_reg3,
            O_reg4        => SC_reg4,
            O_reg5        => SC_reg5,
            O_l_rouge     => O_rouge,
            O_l_verte     => O_vert
            );

    modulo6_1 : entity work.compteur_modulo6
        port map (
            I_clk         => SC_clkDisplay,
            I_rst         => I_rst,
            I_bloque      => I_bloque,
            O_CounterMod6 => SC_num
            );

    diviseur_freq_1 : entity work.diviseur_freq
        generic map (
            n_fast => n_fast,
            n_slow => n_slow)
        port map (
            I_clk  => I_clk_100m,
            I_rst  => I_rst,
            O_FAST => SC_clk,
            O_SLOW => SC_clkDisplay
            );

    mux6_1_1 : entity work.mux6_1
        port map (
            I_0    => SC_reg0,
            I_1    => SC_reg1,
            I_2    => SC_reg2,
            I_3    => SC_reg3,
            I_4    => SC_reg4,
            I_5    => SC_reg5,
            I_sel  => SC_num,
            O_mux6 => SC_nombre
            );

    transcod_1 : entity work.transcodeur7s_d_u(transcod_int)  --(transcod_ARCH)
        port map (
            I_nombre => SC_nombre,
            O_uni    => SC_uni,
            O_diz    => SC_diz
            );

    decodeur_uni_1 : entity work.transcodeur7s_u
        port map (
            E    => SC_num,
            Suni => SC_numTranscode
            );

    modulo4_2 : entity work.modulo4
        port map (
            I_clk   => SC_clk,
            I_rst   => I_rst,
            O_Mod4  => SC_affSelect,
            O_decod => O_an(3 downto 0)
            );

    O_an(4) <= '1';
    O_an(5) <= '1';
    O_an(6) <= '1';
    O_an(7) <= '1';

    SC_minus <= "0111111";

    with SC_affSelect select O_aff <=
        SC_uni          when "00",
        SC_diz          when "01",
        SC_minus        when "10",
        SC_numTranscode when others;

end architecture arch;