project_loto/project_loto.cache/sim/ssm.db

+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Feb 12 10:34:45 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################

project_loto/project_loto.cache/wt/project.wpc

+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
+eof:

project_loto/project_loto.cache/wt/xsim.wdf

+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:2427094519

project_loto/project_loto.hw/project_loto.lpr

+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

project_loto/project_loto.ip_user_files/README.txt

+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

project_loto/project_loto.sim/sim_1/behav/xsim/compile.sh

+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Feb 12 12:17:00 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj"
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."

project_loto/project_loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl

+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

project_loto/project_loto.sim/sim_1/behav/xsim/elaborate.log

+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log 
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_automate of entity xil_defaultlib.automate [automate_default]
+Compiling architecture a_registres of entity xil_defaultlib.registres [registres_default]
+Compiling architecture a_compteur_valid of entity xil_defaultlib.compteur_valid [compteur_valid_default]
+Compiling architecture compteur_a of entity xil_defaultlib.compteur1_49 [compteur1_49_default]
+Compiling architecture arch of entity xil_defaultlib.led_pwm [led_pwm_default]
+Compiling architecture a_tirage of entity xil_defaultlib.tirage [tirage_default]
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture behavioral of entity xil_defaultlib.diviseur_freq [\diviseur_freq(n_fast=0,n_slow=3...]
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture transcod_int of entity xil_defaultlib.transcodeur7s_d_u [transcodeur7s_d_u_default]
+Compiling architecture modulo4_a of entity xil_defaultlib.modulo4 [modulo4_default]
+Compiling architecture arch of entity xil_defaultlib.loto [\loto(n_fast=0,n_slow=3)\]
+Compiling architecture ar of entity xil_defaultlib.loto_tb [loto_tb]
+Built simulation snapshot loto_tb_ar_cfg_behav

project_loto/project_loto.sim/sim_1/behav/xsim/elaborate.sh

+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename    : elaborate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Feb 12 12:17:02 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+

project_loto/project_loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl

+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

project_loto/project_loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj

+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../../src/automate.vhd" \
+"../../../../../src/compteur1_49.vhd" \
+"../../../../../src/compteur_modulo6.vhd" \
+"../../../../../src/compteur_valid.vhd" \
+"../../../../../src/diviseur_freq.vhd" \
+"../../../../../src/led_pwm.vhd" \
+"../../../../../src/registres.vhd" \
+"../../../../../src/tirage.vhd" \
+"../../../../../src/mux6_1.vhd" \
+"../../../../../src/transcodeur7s_d_u.vhd" \
+"../../../../../src/modulo4.vhd" \
+"../../../../../src/loto.vhd" \
+"../../../../../src/loto_tb.vhd" \
+
+# Do not sort compile order
+nosort

project_loto/project_loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl

+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns