modification FSM finale + ajout du fichier vhdl

controlUnit.vhd

+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity controlUnit is
+
+  port (
+    I_clock               : in  std_logic;  -- global clock
+    I_reset               : in  std_logic;  -- asynchronous global reset
+    I_inputSampleValid    : in  std_logic;  -- Control signal to load the input sample in the sample shift register and shift the register
+    I_processingDone_X    : in  std_logic;
+    I_processingDone_Y    : in  std_logic;
+    I_processingDone_Z_A    : in  std_logic;
+    I_processingDone_Z_B    : in  std_logic;
+    O_loadShift_X         : out std_logic;  -- filtered sample
+    O_loadShift_Y         : out std_logic;  -- filtered sample
+    O_loadShift_Z         : out std_logic;  -- filtered sample
+    O_initAddress         : out std_logic;  -- Control signal to initialize register read address
+    O_incrAddress         : out std_logic;  -- Control signal to increment register read address
+    O_initSum             : out std_logic;  -- Control signal to initialize the MAC register
+    O_loadSum             : out std_logic;  -- Control signal to load the MAC register;
+    O_loadY               : out std_logic;  -- Control signal to load Y register
+    O_FilteredSampleValid : out std_logic  -- Data valid signal for filtered sample
+    );
+
+end entity controlUnit;
+architecture archi_operativeUnit of controlUnit is
+
+
+  type T_state is (WAIT_SAMPLE, STORE_X, STORE_Y, STORE_Z, PROCESSING_LOOP_X, PROCESSING_LOOP_Y, PROCESSING_LOOP_Z_A, PROCESSING_LOOP_Z_B, OUTPUT, WAIT_END_SAMPLE);  -- state list
+  signal SR_presentState : T_state;
+  signal SR_futurState   : T_state;
+
+begin
+
+  process ( I_clock, I_reset ) is
+  begin
+    if I_reset = '1' then               -- asynchronous reset (active high)
+      SR_presentState <= WAIT_SAMPLE;
+    elsif rising_edge(I_clock) then     -- rising clock edge
+      SR_presentState <= SR_futurState;
+    end if;
+  end process;
+
+  process (SR_presentState, I_inputSampleValid, I_processingDone_X, I_processingDone_Y, I_processingDone_Z_A, I_processingDone_Z_B) is
+  begin
+    case SR_presentState is
+
+      when WAIT_SAMPLE =>
+        if I_inputSampleValid = '1' then
+            SR_futurState <= STORE_X;
+        else
+            SR_futurState <= WAIT_SAMPLE;
+        end if;
+      
+      when STORE_X =>
+        O_initAddress <= '1';
+        O_initSum     <= '1';
+        O_incrAddress <= '0';
+        O_loadSum     <= '0';
+        SR_futurState <= PROCESSING_LOOP_X;
+        
+      when PROCESSING_LOOP_X =>
+        O_initAddress <= '0';
+        O_initSum     <= '0';
+        O_incrAddress <= '1';
+        O_loadSum     <= '1';
+        if I_processingDone_X = '1' then
+            SR_futurState <= STORE_Y;
+        else
+            SR_futurState <= PROCESSING_LOOP_X;
+        end if;
+      
+      when STORE_Y =>
+        O_initAddress <= '1';
+        O_initSum     <= '1';
+        O_incrAddress <= '0';
+        O_loadSum     <= '0';
+        SR_futurState <= PROCESSING_LOOP_Y;
+        
+      when PROCESSING_LOOP_Y =>
+        O_initAddress <= '0';
+        O_initSum     <= '0';
+        O_incrAddress <= '1';
+        O_loadSum     <= '1';
+        if I_processingDone_Y = '1' then
+            SR_futurState <= PROCESSING_LOOP_Z_A;
+        else
+            SR_futurState <= PROCESSING_LOOP_Y;
+        end if;
+        
+      when PROCESSING_LOOP_Z_A =>
+        O_initAddress <= '0';
+        O_initSum     <= '0';
+        O_incrAddress <= '1';
+        O_loadSum     <= '1';
+        if I_processingDone_Z_A = '1' then
+            SR_futurState <= STORE_Z;
+        else
+            SR_futurState <= PROCESSING_LOOP_Z_A;
+        end if;
+        
+      when STORE_Z =>
+        O_initAddress <= '1';
+        O_initSum     <= '1';
+        O_incrAddress <= '0';
+        O_loadSum     <= '0';
+        SR_futurState <= PROCESSING_LOOP_Z_B;
+      
+      when PROCESSING_LOOP_Z_B =>
+        O_initAddress <= '0';
+        O_initSum     <= '0';
+        O_incrAddress <= '1';
+        O_loadSum     <= '1';
+        if I_processingDone_Z_B = '1' then
+            SR_futurState <= OUTPUT;
+        else
+            SR_futurState <= PROCESSING_LOOP_Z_B;
+        end if;
+  
+      when OUTPUT =>
+        SR_futurState <= WAIT_END_SAMPLE;
+      
+      when WAIT_END_SAMPLE =>
+        if I_inputSampleValid = '0' then
+            SR_futurState <= WAIT_SAMPLE;
+        else
+            SR_futurState <= WAIT_END_SAMPLE;
+        end if;
+        
+      when others => null;
+    end case;
+  end process;
+
+O_loadShift_X         <= '1' when SR_presentState = STORE_X else '0';
+O_loadShift_Y         <= '1' when SR_presentState = STORE_Y else '0';
+O_loadShift_Z         <= '1' when SR_presentState = STORE_Z else '0';
+O_loadY               <= '1' when SR_presentState = OUTPUT else '0';
+O_FilteredSampleValid <= '1' when SR_presentState = WAIT_END_SAMPLE else '0';
+
+
+
+
+
+end architecture archi_operativeUnit;
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