wave generator teste

src/hdl/wave_generator.vhd

@@ -65,7 +65,7 @@ begin
             )
         port map (
             I_clk    => I_clk,
-            I_rst    => I_rst ,
+            I_rst    => I_rst,
             I_u_d    => S_u_d,
             O_val    => S_addr,
             O_last   => S_last,
@@ -108,10 +108,10 @@ begin
             G_fs => G_fs
             )
         port map (
-            I_clk       => I_clk ,
+            I_clk       => I_clk,
             I_rst       => I_rst,
             I_addr      => S_addr,
-            O_saw_tooth => S_saw_tooth_out_lut
+            O_saw_tooth => S_saw_tooth_out_lut 
             );
 
     S_square <= ((G_N-1) => '0', others => '1');
@@ -122,8 +122,8 @@ begin
             I_sel  => I_wave_sel,
             I_din0 => S_sine_out_lut,
             I_din1 => S_square,
-            I_din2 => S_saw_tooth_out_lut,
-            I_din3 => S_triangle_out_lut,
+            I_din2 => S_saw_tooth_out_lut ,
+            I_din3 => S_triangle_out_lut ,
             O_dout => S_wave_sample
             );
 
@@ -143,7 +143,7 @@ begin
             I_sel  => S_sign_sel,
             I_din0 => S_wave_sample,
             I_din1 => S_opposite_wave_sample,
-            O_dout => S_wave_sample
+            O_dout => S_wave_value
             );
 
     -- Module I
@@ -152,10 +152,10 @@ begin
             G_N => G_N
             )
         port map (
-            I_clk  => I_clk  ,
-            I_rst  => I_rst,
-            I_din  => S_wave_sample,
-            O_dout => S_wave_value   
+            I_clk  => I_clk,
+            I_rst  => I_rst ,
+            I_din  => S_wave_value,
+            O_dout => O_wav
             );
 
 end arch;