emilien

src/hdl/operativeUnit.vhd

@@ -114,29 +114,28 @@ begin
                         );
     
     -- Process to describe the shift register storing the input samples
-    shift : process (I_clock,I_reset) is
+    shift : process (I_clock, I_reset) is
     begin  -- process shift
         if I_reset = '1' then           -- asynchronous reset (active high)
             SR_shiftRegister <= (others => (others => '0'));
-        elsif rising_edge(I_clock) then
-            if I_loadShift = '1' then
-                for i in 15 downto 1 loop
-                    SR_shiftRegister(i) <= SR_shiftRegister(i-1);
-                end loop;
+        elsif rising_edge (I_clock) then 
+            if I_loadshift='1' then
+                SR_shiftRegister(0 downto 14) <= SR_shiftRegister(1 downto 15); 
                 SR_shiftRegister(0) <= signed(I_inputSample);
             end if;
         end if;
     end process shift;
 
-    -- Process for incrementing and initializing the read address
+    -- Process to describe the counter providing the selection adresses
+    -- of the multiplexers
     incr_address : process (I_clock, I_reset) is
     begin
-        if I_reset = '1' then
+        if I_reset = '1' then               -- asynchronous reset (active high)
             SR_readAddress <= 0;
-        elsif rising_edge(I_clock) then
-            if I_initAddress = '1' then
+        elsif rising_edge (I_clock) then 
+            if I_initAddress ='1' then 
                 SR_readAddress <= 0;
-            elsif I_incrAddress = '1' then
+            elsif I_incrAddress = '1' then  
                 SR_readAddress <= SR_readAddress + 1;
             end if;
         end if;
@@ -146,31 +145,46 @@ begin
     -- providing the last product used to compute the convolution
     O_processingDone <= '1' when SR_readAddress = 15 else '0';
 
-   -- Multiplication operands
-    SC_multOperand1 <= SR_shiftRegister(SR_readAddress);
-    SC_multOperand2 <= SR_coefRegister(SR_readAddress);
+    -- Signals connected with multiplexers (SIMPLY inferred with table indices)
+    SC_multOperand1 <= SR_shiftRegister(SR_readAddress);             -- 16 bits
+    SC_multOperand2 <= SR_coefRegister(SR_readAddress);             -- 16 bits
+
+    -- Multiplication of the operands
+    SC_MultResult   <= SC_multOperand1*SC_multOperand2;             -- 32 bits
 
-    -- Multiplication
-    SC_MultResult   <= resize(SC_multOperand1, 32) * resize(SC_multOperand2, 32);
     -- Sum of the multiplication result and the accumulated value
     SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
 
     -- Register to store the accumulated value if the loadSum is active
     -- It also reduces the width of the sum to fit to the input and output
     -- signal widths (be careful with truncating/rounding)
-    sum_acc : process (_BLANK_) is
+    sum_acc : process (I_clock, I_reset) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_sum <= (others => '0');
-        elsif _BLANK_
+        elsif rising_edge (I_clock) then 
+            if I_initSum = '1' then 
+                SR_sum <= (others => '0');
+            elsif I_loadSum = '1' then 
+                Sr_sum <= SC_addResult;    
+            end if;
         end if;
     end process sum_acc;
 
     -- Register to store the final result if the loadOuput is active
-    store_result : process (_BLANK_) is
+    store_result : process (I_clock, I_reset) is
     begin
-        _BLANK_
-
+        if I_reset='1' then 
+            SR_filteredSample <= (others => '0');
+        elsif rising_edge (I_clock) then
+            if I_loadY = '1' then
+                if SC_addResult(14) = '1' then
+                    SR_filteredSample <= SC_addResult(30 downto 15) + 1;
+                else    
+                    SR_filteredSample <= SC_addResult(30 downto 15);
+                end if;
+            end if;
+         end if;
     end process store_result;
 
     O_filteredSample <= std_logic_vector(SR_filteredSample);