2_completes

src/hdl/controlUnit.vhd

@@ -90,6 +90,13 @@ begin
             SR_nextState <= WAIT_END_SAMPLE;
         end if;
         
+      when PROCESSING_LOOP =>
+        if I_processingDone = '1' then
+            SR_nextState <= OUTPUT;
+        else
+            SR_nextState <= PROCESSING_LOOP;
+        end if;
+        
       when others =>
         SR_nextState <= WAIT_SAMPLE;