operative_unit_final version

docs/compte-rendu.md

@@ -9,9 +9,15 @@
 
 ### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
 
+Dans controlUnit.vhd, on définit 2 processus différents:
+- Un processus séquentiel qui décrit le registre d'état. Il sert à actualiser l'état actuel à chaque front montant de l'horloge: soit on reset, soit on prend le prochain état qui a été calculé par l'autre processu             s
+- Un processus combinatoire, qui calcule le prochain état, en respectant la description du système.
 
 ### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
 
+Durant la simulation, on voit qu'on passe par les différents états, et que les changements d'états respectent bien le comportement attendu du système. Les conditions de changements d'états sont elles aussi respectées.
+
+Ainsi, la simulation nous permet de valider notre description VHDL de l'unité de controle.
 
 ### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
 

src/hdl/operativeUnit.vhd

@@ -68,7 +68,7 @@ architecture arch_operativeUnit of operativeUnit is
 
 
 
-begin
+begin 
 
     -- Low-pass filter provided with octave (or Matlab ;)) script :
     -- pkg load signal
@@ -114,41 +114,45 @@ begin
                         );
     
     -- Process to describe the shift register storing the input samples
-    shift : process (I_reset, I_loadShift) is
-    begin  -- process shift
+    shift : process (I_reset, I_clock) is
+    begin 
         if I_reset = '1' then           -- asynchronous reset (active high)
             SR_shiftRegister <= (others => (others => '0'));
-        elsif I_loadShift = '1' then  -- load the input sample in the shift register
-            SR_shiftRegister(0) <= signed(I_inputSample);  -- load the input sample in the first register
-            for i in 1 to 15 loop
-                SR_shiftRegister(i) <= SR_shiftRegister(i-1);  -- shift the register
-            end loop;
-
-
+        elsif rising_edge(I_clock)then
+            if I_loadShift = '1' then  -- load the input sample in the shift register
+                SR_shiftRegister(1 to 15) <= SR_shiftRegister(0 to 14); -- shift the register to leave space for the inputSampl
+                SR_shiftRegister(0) <= signed(I_inputSample);  -- load the input sample in the first register
+--            for i in 1 to 15 loop
+--                SR_shiftRegister(i) <= SR_shiftRegister(i-1);  -- shift the register
+--            end loop;
+                
+            end if;
         end if;
     end process shift;
 
     -- Process to describe the counter providing the selection adresses
     -- of the multiplexers
-    incr_address : process (I_reset, I_incrAddress, I_initAddress) is
+    incr_address : process (I_reset, I_clock) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_readAddress <= 0;
-        elsif I_initAddress = '1' then  -- initialize the address to 0
-            SR_readAddress <= 0;
-        elsif I_incrAddress = '1' then  -- increment the address
-            if SR_readAddress < 15 then
-                SR_readAddress <= SR_readAddress + 1;  -- increment the address
-            else
-                SR_readAddress <= 0;  -- reset the address to 0
-            end if;
+        elsif rising_edge(I_clock)then
+            if I_initAddress = '1' then  -- initialize the address to 0
+                SR_readAddress <= 0;
+            elsif I_incrAddress = '1' then  -- increment the address
+                if SR_readAddress < 15 then
+                    SR_readAddress <= SR_readAddress + 1;  -- increment the address
+                else
+                    SR_readAddress <= 0;  -- reset the address to 0
+                end if;
 
+            end if;
         end if;
     end process incr_address;
 
     -- Signal detecting that the next cycle will be the one
     -- providing the last product used to compute the convolution
-    O_processingDone <= '1' when SR_readAddress = 15;
+    O_processingDone <= '1' when SR_readAddress = 14 else '0';
 
     -- Signals connected with multiplexers (SIMPLY inferred with table indices)
     SC_multOperand1 <= SR_shiftRegister(SR_readAddress);             -- 16 bits
@@ -157,30 +161,39 @@ begin
     -- Multiplication of the operands
     SC_MultResult   <= SC_multOperand1 * SC_multOperand2;             -- 32 bits
 
-    -- Sum of the multiplication result and the accumulated value
-    SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+    -- Sum of the multiplication result and the accumulated value    
+    SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum; 
 
     -- Register to store the accumulated value if the loadSum is active
     -- It also reduces the width of the sum to fit to the input and output
-    -- signal widths (be careful with truncating/rounding)
-    sum_acc : process (I_reset, I_initSum, I_loadSum) is
+    -- signal widths (be careful with truncating/rounding) 
+    sum_acc : process (I_reset, I_clock) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_sum <= (others => '0');
-        elsif I_initSum = '1' then  -- initialize the sum to 0
-            SR_sum <= (others => '0');
-        elsif I_loadSum = '1' then  -- load the sum with the multiplication result
-            SR_sum <= SC_addResult;  -- load the sum with the multiplication result
+        elsif rising_edge(I_clock) then
+            if I_initSum = '1' then  -- initialize the sum to 0
+                SR_sum <= (others => '0');
+            elsif I_loadSum = '1' then  -- load the sum with the multiplication result
+                SR_sum <= SC_addResult;
+            end if;
         end if;
     end process sum_acc;
 
     -- Register to store the final result if the loadOuput is active
-    store_result : process (I_reset, I_loadY) is
+    store_result : process (I_reset, I_clock) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_filteredSample <= (others => '0');
-        elsif I_loadY = '1' then  -- load the output register with the sum value
-            SR_filteredSample <= resize(SR_sum, SR_filteredSample'length);  -- load the output register with the sum value
+        elsif rising_edge(I_clock) then
+            if I_loadY = '1' then  -- load the output register with the sum value
+                if SR_sum(14) = '1' then
+                    SR_filteredSample <= SR_sum(30 downto 15) + 1;
+                else
+                    SR_filteredSample <= SR_sum(30 downto 15);
+                end if;
+                -- SR_filteredSample <= resize(SR_sum, SR_filteredSample'length);  -- load the output register with the sum value
+            end if;
         end if;
 
     end process store_result;