tpfiltre_encours

docs/compte-rendu.md

@@ -8,10 +8,16 @@
 ## Questions
 
 ### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
+On utilise deux processus explicites:  process (I_clock,I_reset) et  process (SR_currentState, I_inputSampleValid, I_processingDone). Le premier processus est séquentiel synchrone car il utilise l'horloge CLK et sert à mémoriser l'état courant SR_currentState et change d'état à chaque rising edge de l'horloge. De plus il peut aussi retourner à l'état initial si reste vaut 1.
+ Le second est sans horloge et est donc combinatoire, il sert à calculer la valeur du prochain état en fonction de l'état courant et des entrées. 
+Ensuite, on utilise 7 autres processus implicites qui sont combinatoires. Ces processus sont:
 
+  O_loadShift,  O_initAddress,  O_incrAddress, O_initSum,  O_loadSum, O_loadOutput et O_FilteredSampleValid.
+    
 
+  
 ### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
-
+ca valide
 
 ### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
 

src/hdl/controlUnit.vhd

@@ -54,23 +54,53 @@ begin
   -- Process to describe the state register
   -- Current state is provide at the output of the register
   -- and is updated with the next state at each rising edge of clock
-  process (_BLANK_) is
+  process (I_clock,I_reset) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
-      SR_currentState <= _BLANK_
-    elsif rising_edge(I_clock) then     -- rising clock edge
-      _BLANK_
+     SR_currentState <=WAIT_SAMPLE;
+    elsif rising_edge (I_clock) then
+      SR_currentState <= SR_nextState;
     end if;
   end process;
 
   -- Combinatorial process computing the next state which depends on
-  -- the current state and on the inputs
-  process (_BLANK_) is
-  begin
+  -- the current state and on the inputs 
+  
+   process (SR_currentState, I_inputSampleValid, I_processingDone) is
+   begin
     case SR_currentState is
 
       when WAIT_SAMPLE =>
-        _BLANK_
+        if I_inputSampleValid= '1' then
+            SR_nextState<= STORE;
+        else
+            SR_nextState<= WAIT_SAMPLE;
+        end if;
+        
+      when STORE =>
+        SR_nextState <= PROCESSING_LOOP;
+      
+      when PROCESSING_LOOP =>
+        if I_processingDone = '1' then
+            SR_nextState <= OUTPUT;
+        else
+            SR_nextState <=  PROCESSING_LOOP;
+        end if;
+        
+       when OUTPUT =>
+        SR_nextState <= WAIT_END_SAMPLE;
+            
+        when WAIT_END_SAMPLE =>
+          if I_inputSampleValid = '0' then
+            SR_nextState <= WAIT_SAMPLE;
+               
+            
+         else
+           SR_nextState <= WAIT_END_SAMPLE;
+         end if;
+              
+        
+          
 
       when others => null;
     end case;
@@ -78,13 +108,13 @@ begin
 
   -- Rules to compute the outputs depending on the current state
   -- (and on the inputs, if you want a Mealy machine).
-  O_loadShift           <= '1' when _BLANK_ else '0';
-  O_initAddress         <= '1' when _BLANK_ else '0';
-  O_incrAddress         <= '1' when _BLANK_ else '0';
-  O_initSum             <= '1' when _BLANK_ else '0';
-  O_loadSum             <= '1' when _BLANK_ else '0';
-  O_loadOutput          <= '1' when _BLANK_ else '0';
-  O_FilteredSampleValid <= '1' when _BLANK_ else '0';
+  O_loadShift           <= '1' when SR_currentState = STORE else '0';
+  O_initAddress         <= '1' when SR_currentState = STORE else '0';
+  O_incrAddress         <= '1' when SR_currentState = PROCESSING_LOOP else '0';
+  O_initSum             <= '1' when SR_currentState = STORE else '0';
+  O_loadSum             <= '1' when SR_currentState = PROCESSING_LOOP else '0';
+  O_loadOutput          <= '1' when SR_currentState = OUTPUT else '0';
+  O_FilteredSampleValid <= '1' when SR_currentState = OUTPUT or SR_currentState=WAIT_END_SAMPLE else '0';