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Commit 84218874 authored by Sadok LAJMI's avatar Sadok LAJMI
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Update TP filtre séance 2

parent 9166d51e
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......@@ -45,7 +45,7 @@ entity operativeUnit is
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register
I_loadOutput : in std_logic; -- Control signal to load output register
O_processingDone : out std_logic; -- Indicate that processing is done
O_filteredSample : out std_logic_vector(15 downto 0) -- filtered sample
);
......@@ -114,36 +114,48 @@ begin
);
-- Process to describe the shift register storing the input samples
shift : process (_BLANK_) is
shift : process (I_clock,I_reset) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));
elsif _BLANK_
elsif rising_edge(I_clock) then
if I_loadShift = '1' then
for i in SR_shiftRegister'length-1 downto 1 loop
SR_shiftRegister(i) <= SR_shiftRegister(i-1);
end loop;
SR_shiftRegister(0) <= signed(I_inputSample);
end if;
end if;
end process shift;
-- Process to describe the counter providing the selection adresses
-- of the multiplexers
incr_address : process (_BLANK_) is
incr_address : process (I_reset,I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0;
elsif _BLANK_
elsif rising_edge(I_clock) then --at each Rising edge, we look if the condition I_incrAddress = '1' is met
if I_initAddress = '1' then
SR_readAddress <= 0 ;
elsif I_incrAddress = '1' and SR_readAddress < 15 then
SR_readAddress <= SR_readAddress + 1;
end if;
end if;
end process incr_address;
-- Signal detecting that the next cycle will be the one
-- providing the last product used to compute the convolution
O_processingDone <= '1' when _BLANK_;
O_processingDone <= '1' when SR_readAddress = 14 else '0'; --pour ne pas dépasser le compteur
-- Signals connected with multiplexers (SIMPLY inferred with table indices)
SC_multOperand1 <= _BLANK_; -- 16 bits
SC_multOperand2 <= _BLANK_; -- 16 bits
SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 16 bits
SC_multOperand2 <= SR_coefRegister(SR_readAddress); -- 16 bits
-- Multiplication of the operands
SC_MultResult <= _BLANK_; -- 32 bits
SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 32 bits
-- Sum of the multiplication result and the accumulated value
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
......@@ -151,18 +163,35 @@ begin
-- Register to store the accumulated value if the loadSum is active
-- It also reduces the width of the sum to fit to the input and output
-- signal widths (be careful with truncating/rounding)
sum_acc : process (_BLANK_) is
sum_acc : process (I_reset,I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_sum <= (others => '0');
elsif _BLANK_
SR_sum <= (others => '0'); --Si le reset est actif, alors on initialise tout à 0
elsif rising_edge (I_clock) then -- Si on est à un front montant, on vérifie les conditions I_initSum et I_loadSum
if I_initSum='1' then
SR_sum <= (others => '0');
elsif I_loadSum='1' then --On fait la somme si I_loadSum vaut 1
SR_sum <= SC_addResult; --on ne prend pas les 4 premiers bits car ils ne servent à rien, et on ne prend pas les 16 derniers bits car il s'agit de la partie décimale et on veut des entiers
end if;
end if;
end process sum_acc;
-- Register to store the final result if the loadOuput is active
store_result : process (_BLANK_) is
store_result : process (I_clock,I_reset) is
begin
_BLANK_
if I_reset = '1' then
SR_filteredSample <= (others => '0');
elsif rising_edge (I_clock) then
if I_loadOutput='1' then
if SR_sum(14)='1' then
SR_filteredSample <= SR_sum(30 downto 15)+1;
else
SR_filteredSample <= SR_sum(30 downto 15);
end if;
end if;
end if;
end process store_result;
......
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