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Commit d9e7b9a5 authored by Lianne SOO's avatar Lianne SOO
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synthe

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proj/tb_module_B_behav.wcfg 0 → 100644
+ 56
− 0
View file @ d9e7b9a5
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_module_B_behav.wdb" id="1">
<top_modules>
<top_module name="tb_module_B" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="412.420 ns"></ZoomStartTime>
<ZoomEndTime time="490.221 ns"></ZoomEndTime>
<Cursor1Time time="258.970 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="120"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="8" />
<wvobject type="logic" fp_name="/tb_module_B/SR_clk">
<obj_property name="ElementShortName">SR_clk</obj_property>
<obj_property name="ObjectShortName">SR_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_module_B/SR_rst">
<obj_property name="ElementShortName">SR_rst</obj_property>
<obj_property name="ObjectShortName">SR_rst</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_module_B/SR_u_d">
<obj_property name="ElementShortName">SR_u_d</obj_property>
<obj_property name="ObjectShortName">SR_u_d</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_module_B/SC_val">
<obj_property name="ElementShortName">SC_val[4:0]</obj_property>
<obj_property name="ObjectShortName">SC_val[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_module_B/SC_last">
<obj_property name="ElementShortName">SC_last</obj_property>
<obj_property name="ObjectShortName">SC_last</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_module_B/SC_middle">
<obj_property name="ElementShortName">SC_middle</obj_property>
<obj_property name="ObjectShortName">SC_middle</obj_property>
</wvobject>
<wvobject type="other" fp_name="/tb_module_B/C_clk_period">
<obj_property name="ElementShortName">C_clk_period</obj_property>
<obj_property name="ObjectShortName">C_clk_period</obj_property>
</wvobject>
<wvobject type="other" fp_name="/tb_module_B/C_MAX_VAL">
<obj_property name="ElementShortName">C_MAX_VAL</obj_property>
<obj_property name="ObjectShortName">C_MAX_VAL</obj_property>
</wvobject>
</wave_config>
proj/tb_module_G_behav.wcfg 0 → 100644
+ 30
− 0
View file @ d9e7b9a5
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_module_G_behav.wdb" id="1">
<top_modules>
<top_module name="tb_module_G" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000 ns"></ZoomStartTime>
<ZoomEndTime time="82.101 ns"></ZoomEndTime>
<Cursor1Time time="10.000 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="120"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="2" />
<wvobject type="array" fp_name="/tb_module_G/SR_din">
<obj_property name="ElementShortName">SR_din[7:0]</obj_property>
<obj_property name="ObjectShortName">SR_din[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_module_G/SC_dout">
<obj_property name="ElementShortName">SC_dout[7:0]</obj_property>
<obj_property name="ObjectShortName">SC_dout[7:0]</obj_property>
</wvobject>
</wave_config>
src/hdl/wave_generator.vhd
+ 30
− 30
View file @ d9e7b9a5
...@@ -64,12 +64,12 @@ begin ...@@ -64,12 +64,12 @@ begin
G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0))) G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_u_d => , I_u_d => S_u_d,
O_val => , O_val => S_addr,
O_last => , O_last => S_last,
O_middle => O_middle => S_middle
); );
-- Module C -- Module C
...@@ -94,10 +94,10 @@ begin ...@@ -94,10 +94,10 @@ begin
G_fs => G_fs G_fs => G_fs
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_addr => , I_addr => S_addr(C_addr_half_w-1 downto 0),
O_triangle => O_triangle => S_triangle_out_lut
); );
-- Module E -- Module E
...@@ -108,10 +108,10 @@ begin ...@@ -108,10 +108,10 @@ begin
G_fs => G_fs G_fs => G_fs
) )
port map ( port map (
I_clk => , I_clk => I_clk ,
I_rst => , I_rst => I_rst ,
I_addr => , I_addr => S_addr,
O_saw_tooth => O_saw_tooth =>S_saw_tooth_out_lut
); );
S_square <= ((G_N-1) => '0', others => '1'); S_square <= ((G_N-1) => '0', others => '1');
...@@ -119,12 +119,12 @@ begin ...@@ -119,12 +119,12 @@ begin
-- Module F -- Module F
F_inst : entity work.module_F F_inst : entity work.module_F
port map ( port map (
I_sel => , I_sel => I_wave_sel,
I_din0 => , I_din0 => S_sine_out_lut,
I_din1 => , I_din1 => S_square ,
I_din2 => , I_din2 => S_saw_tooth_out_lut ,
I_din3 => , I_din3 => S_triangle_out_lut,
O_dout => O_dout => S_wave_sample
); );
-- Module G -- Module G
...@@ -133,17 +133,17 @@ begin ...@@ -133,17 +133,17 @@ begin
G_N => G_N G_N => G_N
) )
port map ( port map (
I_din => , I_din => S_wave_sample,
O_dout => O_dout => S_opposite_wave_sample
); );
-- Module H -- Module H
H_inst : entity work.module_H H_inst : entity work.module_H
port map ( port map (
I_sel => , I_sel => S_sign_sel,
I_din0 => , I_din0 => S_wave_sample,
I_din1 => , I_din1 => S_opposite_wave_sample,
O_dout => O_dout => S_wave_value
); );
-- Module I -- Module I
...@@ -152,10 +152,10 @@ begin ...@@ -152,10 +152,10 @@ begin
G_N => G_N G_N => G_N
) )
port map ( port map (
I_clk => , I_clk => I_clk ,
I_rst => , I_rst => I_rst,
I_din => , I_din => S_wave_value,
O_dout => O_dout => O_wav
); );
end arch; end arch;
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