wave g V2

src/hdl/wave_generator.vhd

@@ -44,7 +44,6 @@ architecture arch of wave_generator is
     signal S_middle               : std_logic;
     signal S_u_d                  : std_logic;
     signal S_sign_sel             : std_logic;
-  
 
 begin
     -- Module A
@@ -70,7 +69,7 @@ begin
             I_u_d    => S_u_d,
             O_val    => S_addr,
             O_last   => S_last,
-            O_middle =>S_middle
+            O_middle => S_middle
             );
 
     -- Module C
@@ -98,7 +97,7 @@ begin
             I_clk      => I_clk,
             I_rst      => I_rst,
             I_addr     => S_addr(C_addr_half_w-1 downto 0),
-            O_triangle =>S_triangle_out_lut
+            O_triangle => S_triangle_out_lut 
             );
 
     -- Module E
@@ -112,7 +111,7 @@ begin
             I_clk       => I_clk,
             I_rst       => I_rst,
             I_addr      => S_addr,
-            O_saw_tooth =>S_saw_tooth_out_lut
+            O_saw_tooth => S_saw_tooth_out_lut 
             );
 
     S_square <= ((G_N-1) => '0', others => '1');
@@ -123,9 +122,9 @@ begin
             I_sel  => I_wave_sel,
             I_din0 => S_sine_out_lut,
             I_din1 => S_square,
-            I_din2 => S_saw_tooth_out_lut,
-            I_din3 => S_triangle_out_lut,
-            O_dout =>S_wave_sample
+            I_din2 => S_saw_tooth_out_lut ,
+            I_din3 => S_triangle_out_lut ,
+            O_dout => S_wave_sample
             );
 
     -- Module G
@@ -154,7 +153,7 @@ begin
             )
         port map (
             I_clk  => I_clk,
-            I_rst  => I_rst,
+            I_rst  => I_rst ,
             I_din  => S_wave_value,
             O_dout => O_wav
             );