Séance 3

docs/compte-rendu.md

@@ -22,12 +22,21 @@ Ce process SR_nextState en fonction des entrées
 En vérifiant les valeurs prises par SC_filteredSample avec les valeurs spécifiées dans le site ,on valide notre description VHDL
 On vérifie également la bonne succession des différents états et leurs bons emplacement.
 ### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
+Ona testé notre filtre avec à l'aide de la carte FPGA et un wave generator , on remarque qu'il y a une atténuation pour les fréquences supérieures à 300 Hz.
 
+On vérifie bien qu'il s'agit d'un filtre passe bas de fréquence de coupure 300Hz.
 
 ### Question filtre 4 : Combien de processus sont utilisés et de quelles natures sont-ils ?
-
-
+Il y'aseul type de processus dans l'unité opérative qui est séquentiel :
+- Le processus qui ...
+-Le processus qui ...
 ### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
+Oui, marche bien. on retrrouve les bonnes valeurs.
+- 1er problème : 
+    -Register to store the accumulated value if the loadSum is active t also reduces the width of the sum to fit to the input and output
+    -- signal widths (be careful with truncating/rounding)
+    sum_acc : process (I_clock,I_reset) is
+
 
 
 ### Question filtre 6 : Validez-vous la conception de l’unité opérative ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ?

proj/AudioProc.cache/sim/ssm.db

@@ -2,7 +2,7 @@
 #                            DONOT REMOVE THIS FILE
 # Unified simulation database file for selected simulation model for IP
 #
-# File: ssm.db (Fri May  9 16:36:02 2025)
+# File: ssm.db (Mon May 12 16:11:31 2025)
 #
 # This file is generated by the unified simulation automation and contains the
 # selected simulation model information for the IP/BD instances.

proj/AudioProc.sim/sim_1/behav/xsim/compile.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Fri May 09 16:43:10 CEST 2025
+# Generated by Vivado on Mon May 12 17:13:05 CEST 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -16,13 +16,9 @@
 #
 # ****************************************************************************
 set -Eeuo pipefail
-# compile Verilog/System Verilog design sources
-echo "xvlog --incr --relax -prj tb_firUnit_vlog.prj"
-xvlog --incr --relax -prj tb_firUnit_vlog.prj 2>&1 | tee compile.log
-
 # compile VHDL design sources
 echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
-xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee -a compile.log
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee compile.log
 
 echo "Waiting for jobs to finish..."
 echo "No pending jobs, compilation finished."

proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log

 Vivado Simulator v2024.1
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log 
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log 
 Using 8 slave threads.
 Starting static elaboration
-Pass Through NonSizing Optimizer
-WARNING: [VRFC 10-3091] actual bit length 36 differs from formal bit length 48 for port 'P' [/homes/m24rharr/TP_filtre/tp-filtre-etudiant-m24rharr/src/hdl/operativeUnit.v:422]
-WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'CO' [/homes/m24rharr/TP_filtre/tp-filtre-etudiant-m24rharr/src/hdl/operativeUnit.v:1478]
 Completed static elaboration
 Starting simulation data flow analysis
 Completed simulation data flow analysis
@@ -15,27 +12,8 @@ Compiling package std.standard
 Compiling package std.textio
 Compiling package ieee.std_logic_1164
 Compiling package ieee.numeric_std
-Compiling package vl.vl_types
-Compiling module xil_defaultlib.glbl
 Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
-Compiling module unisims_ver.GND
-Compiling module unisims_ver.BUFG
-Compiling module unisims_ver.IBUF
-Compiling module unisims_ver.OBUF
-Compiling module unisims_ver.x_lut3_mux8
-Compiling module unisims_ver.LUT3
-Compiling module unisims_ver.DSP48E1(ACASCREG=0,ALUMODEREG=0,...
-Compiling module unisims_ver.x_lut2_mux4
-Compiling module unisims_ver.LUT2
-Compiling module unisims_ver.LUT4
-Compiling module unisims_ver.LUT6
-Compiling module unisims_ver.MUXF8
-Compiling module unisims_ver.MUXF7
-Compiling module unisims_ver.FDCE_default
-Compiling module unisims_ver.CARRY4
-Compiling module unisims_ver.LUT5(INIT=32'b0110101010101010)
-Compiling module unisims_ver.VCC
-Compiling module xil_defaultlib.operativeUnit
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
 Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
 Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
 Built simulation snapshot tb_firUnit_behav

proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Fri May 09 16:43:14 CEST 2025
+# Generated by Vivado on Mon May 12 17:13:08 CEST 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -17,6 +17,6 @@
 # ****************************************************************************
 set -Eeuo pipefail
 # elaborate design
-echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log"
-xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
 

proj/AudioProc.sim/sim_1/behav/xsim/glbl.v

-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

proj/AudioProc.sim/sim_1/behav/xsim/simulate.log

+Time resolution is 1 ps

proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for simulating the design by launching the simulator
 #
-# Generated by Vivado on Fri May 09 16:36:31 CEST 2025
+# Generated by Vivado on Mon May 12 16:59:12 CEST 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj

 # compile vhdl design source files
 vhdl xil_defaultlib  \
 "../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
 "../../../../../src/hdl/firUnit.vhd" \
 "../../../../../src/hdl/tb_firUnit.vhd" \
 

proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj

-# compile verilog/system verilog design source files
-verilog xil_defaultlib  \
-"../../../../../src/hdl/operativeUnit.v" \
-
-# compile glbl module
-verilog xil_defaultlib "glbl.v"
-
-# Do not sort compile order
-nosort

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt

---incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" "xil_defaultlib.glbl" -log "elaborate.log" 
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log" 

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx

 
 { 
-    crc :  17166115203713447618  , 
+    crc :  2000809351303675742  , 
     ccp_crc :  0  , 
-    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl" , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" , 
     buildDate : "May 22 2024" , 
     buildTime : "18:54:44" , 
     linkCmd : "/usr/bin/gcc -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/tb_firUnit_behav/xsimk\"   \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel    -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,