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Commit a4f9528a authored by ARZEL Matthieu's avatar ARZEL Matthieu
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mise à jour des noms de port et des signaux+coeff sur 16 bits+nouveau fichier... 

mise à jour des noms de port et des signaux+coeff sur 16 bits+nouveau fichier verilog pour l'unité operative
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src/hdl/controlUnit.vhd
+ 21
− 12
View file @ a4f9528a
...@@ -17,6 +17,8 @@ ...@@ -17,6 +17,8 @@
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
-- 2018-04-11 1.0 jnbazin Created -- 2018-04-11 1.0 jnbazin Created
-- 2025-04-09 1.1 marzel Renamed some signals and port names to match
-- the description of lab activity
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
library ieee; library ieee;
...@@ -35,7 +37,7 @@ entity controlUnit is ...@@ -35,7 +37,7 @@ entity controlUnit is
O_incrAddress : out std_logic; -- Control signal to increment register read address O_incrAddress : out std_logic; -- Control signal to increment register read address
O_initSum : out std_logic; -- Control signal to initialize the MAC register O_initSum : out std_logic; -- Control signal to initialize the MAC register
O_loadSum : out std_logic; -- Control signal to load the MAC register; O_loadSum : out std_logic; -- Control signal to load the MAC register;
O_loadY : out std_logic; -- Control signal to load Y register O_loadOutput : out std_logic; -- Control signal to load Y register
O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
); );
...@@ -44,23 +46,28 @@ architecture archi_operativeUnit of controlUnit is ...@@ -44,23 +46,28 @@ architecture archi_operativeUnit of controlUnit is
type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE); -- state list type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE); -- state list
signal SR_presentState : T_state; signal SR_currentState : T_state;
signal SR_futurState : T_state; signal SR_nextState : T_state;
begin begin
-- Process to describe the state register
-- Current state is provide at the output of the register
-- and is updated with the next state at each rising edge of clock
process (_BLANK_) is process (_BLANK_) is
begin begin
if I_reset = '1' then -- asynchronous reset (active high) if I_reset = '1' then -- asynchronous reset (active high)
SR_presentState <= _BLANK_ SR_currentState <= _BLANK_
elsif rising_edge(I_clock) then -- rising clock edge elsif rising_edge(I_clock) then -- rising clock edge
_BLANK_ _BLANK_
end if; end if;
end process; end process;
-- Combinatorial process computing the next state which depends on
-- the current state and on the inputs
process (_BLANK_) is process (_BLANK_) is
begin begin
case SR_presentState is case SR_currentState is
when WAIT_SAMPLE => when WAIT_SAMPLE =>
_BLANK_ _BLANK_
...@@ -69,13 +76,15 @@ begin ...@@ -69,13 +76,15 @@ begin
end case; end case;
end process; end process;
O_loadShift <= '1' when _BLANK_ ; -- Rules to compute the outputs depending on the current state
O_initAddress <= '1' when _BLANK_ ; -- (and on the inputs, if you want a Mealy machine).
O_incrAddress <= '1' when _BLANK_ ; O_loadShift <= '1' when _BLANK_ else '0';
O_initSum <= '1' when _BLANK_ ; O_initAddress <= '1' when _BLANK_ else '0';
O_loadSum <= '1' when _BLANK_ ; O_incrAddress <= '1' when _BLANK_ else '0';
O_loadY <= '1' when _BLANK_ ; O_initSum <= '1' when _BLANK_ else '0';
O_FilteredSampleValid <= '1' when _BLANK_ ; O_loadSum <= '1' when _BLANK_ else '0';
O_loadOutput <= '1' when _BLANK_ else '0';
O_FilteredSampleValid <= '1' when _BLANK_ else '0';
......
src/hdl/firUnit.vhd
+ 13
− 10
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...@@ -16,6 +16,9 @@ ...@@ -16,6 +16,9 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
-- 2025-04-09 1.1 marzel Renamed some signals and port names to match
-- the description of lab activity
-- Modified the sample width to 16 bits
-- 2018-04-11 1.0 jnbazin Created -- 2018-04-11 1.0 jnbazin Created
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -28,9 +31,9 @@ entity firUnit is ...@@ -28,9 +31,9 @@ entity firUnit is
port ( port (
I_clock : in std_logic; -- global clock I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample I_inputSample : in std_logic_vector(15 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample O_filteredSample : out std_logic_vector(15 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic O_filteredSampleValid : out std_logic
); );
...@@ -49,7 +52,7 @@ architecture archi_firUnit of firUnit is ...@@ -49,7 +52,7 @@ architecture archi_firUnit of firUnit is
O_incrAddress : out std_logic; O_incrAddress : out std_logic;
O_initSum : out std_logic; O_initSum : out std_logic;
O_loadSum : out std_logic; O_loadSum : out std_logic;
O_loadY : out std_logic; O_loadOutput : out std_logic;
O_FilteredSampleValid : out std_logic); O_FilteredSampleValid : out std_logic);
end component controlUnit; end component controlUnit;
...@@ -57,15 +60,15 @@ architecture archi_firUnit of firUnit is ...@@ -57,15 +60,15 @@ architecture archi_firUnit of firUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_reset : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0); I_inputSample : in std_logic_vector(15 downto 0);
I_loadShift : in std_logic; I_loadShift : in std_logic;
I_initAddress : in std_logic; I_initAddress : in std_logic;
I_incrAddress : in std_logic; I_incrAddress : in std_logic;
I_initSum : in std_logic; I_initSum : in std_logic;
I_loadSum : in std_logic; I_loadSum : in std_logic;
I_loadY : in std_logic; I_loadOutput : in std_logic;
O_processingDone : out std_logic; O_processingDone : out std_logic;
O_Y : out std_logic_vector(7 downto 0)); O_filteredSample : out std_logic_vector(15 downto 0));
end component operativeUnit; end component operativeUnit;
signal SC_processingDone : std_logic; signal SC_processingDone : std_logic;
...@@ -74,7 +77,7 @@ architecture archi_firUnit of firUnit is ...@@ -74,7 +77,7 @@ architecture archi_firUnit of firUnit is
signal SC_incrAddress : std_logic; signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic; signal SC_initSum : std_logic;
signal SC_loadSum : std_logic; signal SC_loadSum : std_logic;
signal SC_loadY : std_logic; signal SC_loadOutput : std_logic;
begin begin
...@@ -89,7 +92,7 @@ begin ...@@ -89,7 +92,7 @@ begin
O_incrAddress => SC_incrAddress, O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum, O_initSum => SC_initSum,
O_loadSum => SC_loadSum, O_loadSum => SC_loadSum,
O_loadY => SC_loadY, O_loadOutput => SC_loadOutput,
O_FilteredSampleValid => O_FilteredSampleValid); O_FilteredSampleValid => O_FilteredSampleValid);
operativeUnit_1 : entity work.operativeUnit operativeUnit_1 : entity work.operativeUnit
...@@ -102,8 +105,8 @@ begin ...@@ -102,8 +105,8 @@ begin
I_incrAddress => SC_incrAddress, I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum, I_initSum => SC_initSum,
I_loadSum => SC_loadSum, I_loadSum => SC_loadSum,
I_loadY => SC_loadY, I_loadOutput => SC_loadOutput,
O_processingDone => SC_processingDone, O_processingDone => SC_processingDone,
O_Y => O_filteredSample); O_filteredSample => O_filteredSample);
end architecture archi_firUnit; end architecture archi_firUnit;
src/hdl/operativeUnit.v 0 → 100644
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src/hdl/operativeUnit.vhd
+ 75
− 36
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...@@ -17,7 +17,12 @@ ...@@ -17,7 +17,12 @@
-- Copyright (c) 2018 -- Copyright (c) 2018
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version A
-- 2025-04-09 1.2 marzel Renamed some signals and port names to match
-- the description of lab activity
-- Modified the sample width to 16 bits
-- Changed the filter coefficients to have abetter
-- low-pass filter
-- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve -- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve
-- the user experience ;) -- the user experience ;)
-- 2018-04-11 1.0 jnbazin Created -- 2018-04-11 1.0 jnbazin Created
...@@ -34,7 +39,7 @@ entity operativeUnit is ...@@ -34,7 +39,7 @@ entity operativeUnit is
port ( port (
I_clock : in std_logic; -- global clock I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample I_inputSample : in std_logic_vector(15 downto 0); -- 16 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_initAddress : in std_logic; -- Control signal to initialize register read address I_initAddress : in std_logic; -- Control signal to initialize register read address
I_incrAddress : in std_logic; -- Control signal to increment register read address I_incrAddress : in std_logic; -- Control signal to increment register read address
...@@ -42,52 +47,73 @@ entity operativeUnit is ...@@ -42,52 +47,73 @@ entity operativeUnit is
I_loadSum : in std_logic; -- Control signal to load the MAC register; I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register I_loadY : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done O_processingDone : out std_logic; -- Indicate that processing is done
O_Y : out std_logic_vector(7 downto 0) -- filtered sample O_filteredSample : out std_logic_vector(15 downto 0) -- filtered sample
); );
end entity operativeUnit; end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is architecture arch_operativeUnit of operativeUnit is
type registerFile is array(0 to 15) of signed(7 downto 0); type registerFile is array(0 to 15) of signed(15 downto 0);
signal SR_coefRegister : registerFile; signal SR_coefRegister : registerFile;
signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples
signal SC_multOperand1 : signed(7 downto 0); signal SC_multOperand1 : signed(15 downto 0);
signal SC_multOperand2 : signed(7 downto 0); signal SC_multOperand2 : signed(15 downto 0);
signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi signal SC_MultResult : signed(31 downto 0); -- Result of the multiplication Xi*Hi
signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition signal SC_addResult : signed(35 downto 0); -- result of the accumulation addition
signal SR_sum : signed(19 downto 0); -- Accumulation register signal SR_sum : signed(35 downto 0); -- Accumulation register
signal SR_Y : signed(7 downto 0); -- filtered sample storage register signal SR_filteredSample: signed(15 downto 0); -- filtered sample storage register
signal SR_readAddress : integer range 0 to 15; -- register files read address signal SR_readAddress : integer range 0 to 15; -- register files read address
begin begin
-- Low-pass filter provided with octave (or Matlab ;)) command -- Low-pass filter provided with octave (or Matlab ;)) script :
-- fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6 -- pkg load signal
-- Or python with (import signal from scipy and math) --
-- [round(elem/math.sqrt(sum(signal.firwin(16, .001)**2)) * 2**6) for elem in signal.firwin(16, .001)] -- fs=44100
-- fn=fs/2
SR_coefRegister <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients -- n=16
to_signed(3, 8), -- fc=300
to_signed(6, 8), -- fLP=fir1(n-1,fc/fn,"low");
to_signed(10, 8), --
to_signed(15, 8), -- function quantized_signal = quantize(signal, q)
to_signed(20, 8), -- % Quantize the signal to q bits
to_signed(24, 8), -- max_val = 2^(q-1) - 1;
to_signed(26, 8), -- min_val = -2^(q-1);
to_signed(26, 8), -- quantized_signal = round(min(max(signal * 2^(q-1), min_val), max_val)) / 2^(q-1);
to_signed(24, 8), -- end
to_signed(20, 8), --
to_signed(15, 8), -- q=16
to_signed(10, 8), --
to_signed(6, 8), -- fLPq= quantize(fLP,q);
to_signed(3, 8), --
to_signed(2, 8) -- for i=1:n
-- printf("to_signed(%d,%d),\n", fLPq(i)*2^(q-1),q);
-- endfor
-- Table to store the filter coefficients obtained with the previous script
SR_coefRegister <= (to_signed(317,16),
to_signed(476,16),
to_signed(925,16),
to_signed(1589,16),
to_signed(2354,16),
to_signed(3087,16),
to_signed(3661,16),
to_signed(3975,16),
to_signed(3975,16),
to_signed(3661,16),
to_signed(3087,16),
to_signed(2354,16),
to_signed(1589,16),
to_signed(925,16),
to_signed(476,16),
to_signed(317,16)
); );
-- Process to describe the shift register storing the input samples
shift : process (_BLANK_) is shift : process (_BLANK_) is
begin -- process shift begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high) if I_reset = '1' then -- asynchronous reset (active high)
...@@ -97,6 +123,8 @@ begin ...@@ -97,6 +123,8 @@ begin
end if; end if;
end process shift; end process shift;
-- Process to describe the counter providing the selection adresses
-- of the multiplexers
incr_address : process (_BLANK_) is incr_address : process (_BLANK_) is
begin begin
if I_reset = '1' then -- asynchronous reset (active high) if I_reset = '1' then -- asynchronous reset (active high)
...@@ -106,13 +134,23 @@ begin ...@@ -106,13 +134,23 @@ begin
end if; end if;
end process incr_address; end process incr_address;
-- Signal detecting that the next cycle will be the one
-- providing the last product used to compute the convolution
O_processingDone <= '1' when _BLANK_; O_processingDone <= '1' when _BLANK_;
SC_multOperand1 <= _BLANK_; -- 8 bits -- Signals connected with multiplexers (SIMPLY inferred with table indices)
SC_multOperand2 <= _BLANK_; -- 8 bits SC_multOperand1 <= _BLANK_; -- 16 bits
SC_MultResult <= _BLANK_; -- 16 bits SC_multOperand2 <= _BLANK_; -- 16 bits
-- Multiplication of the operands
SC_MultResult <= _BLANK_; -- 32 bits
-- Sum of the multiplication result and the accumulated value
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum; SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
-- Register to store the accumulated value if the loadSum is active
-- It also reduces the width of the sum to fit to the input and output
-- signal widths (be careful with truncating/rounding)
sum_acc : process (_BLANK_) is sum_acc : process (_BLANK_) is
begin begin
if I_reset = '1' then -- asynchronous reset (active high) if I_reset = '1' then -- asynchronous reset (active high)
...@@ -121,12 +159,13 @@ begin ...@@ -121,12 +159,13 @@ begin
end if; end if;
end process sum_acc; end process sum_acc;
-- Register to store the final result if the loadOuput is active
store_result : process (_BLANK_) is store_result : process (_BLANK_) is
begin begin
_BLANK_ _BLANK_
end process store_result; end process store_result;
O_Y <= std_logic_vector(SR_Y); O_filteredSample <= std_logic_vector(SR_filteredSample);
end architecture arch_operativeUnit; end architecture arch_operativeUnit;
src/hdl/processingUnitIP.v deleted 100644 → 0
+ 0
− 3270
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src/hdl/tb_firUnit.vhd
+ 25
− 19
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...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: 8 bit FIR -- Description: 16-bit FIR
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2018 -- Copyright (c) 2018
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -19,6 +19,11 @@ ...@@ -19,6 +19,11 @@
-- 2018-04-11 1.0 jnbazin Created -- 2018-04-11 1.0 jnbazin Created
-- 2018-04-18 1.1 marzel Modified to add more test inputs -- 2018-04-18 1.1 marzel Modified to add more test inputs
-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering -- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
-- 2025-04-09 1.2 marzel Renamed some signals and port names to match
-- the description of lab activity
-- Modified the sample width to 16 bits
-- Changed the filter coefficients to have abetter
-- low-pass filter
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
library ieee; library ieee;
...@@ -33,17 +38,17 @@ architecture archi_tb_firUnit of tb_firUnit is ...@@ -33,17 +38,17 @@ architecture archi_tb_firUnit of tb_firUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_reset : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0); I_inputSample : in std_logic_vector(15 downto 0);
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); O_filteredSample : out std_logic_vector(15 downto 0);
O_filteredSampleValid : out std_logic); O_filteredSampleValid : out std_logic);
end component firUnit; end component firUnit;
signal SC_clock : std_logic := '0'; signal SC_clock : std_logic := '0';
signal SC_reset : std_logic; signal SC_reset : std_logic;
signal SC_inputSample : std_logic_vector(7 downto 0); signal SC_inputSample : std_logic_vector(15 downto 0);
signal SC_inputSampleValid : std_logic := '0'; signal SC_inputSampleValid : std_logic := '0';
signal SC_filteredSample : std_logic_vector(7 downto 0); signal SC_filteredSample : std_logic_vector(15 downto 0);
signal SC_filteredSampleValid : std_logic; signal SC_filteredSampleValid : std_logic;
begin begin
...@@ -55,24 +60,25 @@ begin ...@@ -55,24 +60,25 @@ begin
SC_inputSampleValid <= not SC_inputSampleValid after 100 ns; SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
-- Null signal followed by a Dirac and then an arbitrary sequence -- Null signal followed by a Dirac and then an arbitrary sequence
SC_inputSample <= "00000000", SC_inputSample <= "0000000000000000",
"01111111" after 401 ns, "0111111111111111" after 401 ns,
"00000000" after 601 ns, "0000000000000000" after 601 ns,
"00100100" after 4201 ns, "0000000000100100" after 4201 ns,
"01100100" after 4401 ns, "0000000001100100" after 4401 ns,
"10100010" after 4601 ns, "1111111110100010" after 4601 ns,
"11011011" after 4801 ns, "1111111111011011" after 4801 ns,
"00001011" after 5001 ns, "0000000000001011" after 5001 ns,
"10000000" after 5201 ns, "1111111110000000" after 5201 ns,
"01111111" after 5401 ns, "0000000001111111" after 5401 ns,
"10111010" after 5601 ns; "1111111110111010" after 5601 ns;
-- the filter output on 8 bits is a sequence of signed numbers (with the assumption -- the filter output on 16 bits is a sequence of signed numbers (with the assumption
-- of rounding the output, so the accuracy can be slightly different depending -- of rounding the output, so the accuracy can be slightly different depending
-- on your final stage): -- on your final stage):
-- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8 -- 317,476,925,1589,2354,3087,3661,3975,3975,3661,3087,2354,1589,925,476,317,
-- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116 -- 0,0,0,0,1,2,3,4,4,5,2,-1,-5,-10,-16,-23,-30,-37,-43,-49,-56,-61,-64,-68,
-- -68, -70, ...
firUnit_1 : entity work.firUnit firUnit_1 : entity work.firUnit
......
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