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Commit d0bde25d authored by Jean-Noël Bazin's avatar Jean-Noël Bazin
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Fix readme, update vhdl

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README.md
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# TP filtre audio # TP filtre audio
[ ] Comment utiliser Git et Gitlab : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/gitlab/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/gitlab/) - Comment utiliser Git et Gitlab : [https://mee-labs.gitlab-pages.imt-atlantique.fr/gitlab/](https://mee-labs.gitlab-pages.imt-atlantique.fr/gitlab/)
[ ] Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/filtre/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/filtre/) - Énoncé du TP : [https://mee-labs.gitlab-pages.imt-atlantique.fr/vhdl/filter/](https://mee-labs.gitlab-pages.imt-atlantique.fr/vhdl/filter/)
## Questions ## Questions
......
src/hdl/operativeUnit.vhd
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...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> -- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company : -- Company :
-- Created : 2018-04-11 -- Created : 2018-04-11
-- Last update: 2019-02-13 -- Last update: 2025-03-28
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -31,99 +31,102 @@ use ieee.numeric_std.all; ...@@ -31,99 +31,102 @@ use ieee.numeric_std.all;
entity operativeUnit is entity operativeUnit is
port ( port (
I_clock : in std_logic; -- global clock I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_initAddress : in std_logic; -- Control signal to initialize register read address I_initAddress : in std_logic; -- Control signal to initialize register read address
I_incrAddress : in std_logic; -- Control signal to increment register read address I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register; I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register I_loadY : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done O_processingDone : out std_logic; -- Indicate that processing is done
O_Y : out std_logic_vector(7 downto 0) -- filtered sample O_Y : out std_logic_vector(7 downto 0) -- filtered sample
); );
end entity operativeUnit; end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is architecture arch_operativeUnit of operativeUnit is
type registerFile is array(0 to 15) of signed(7 downto 0); type registerFile is array(0 to 15) of signed(7 downto 0);
signal SR_coefRegister : registerFile; signal SR_coefRegister : registerFile;
signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples
signal SC_multOperand1 : signed(7 downto 0); signal SC_multOperand1 : signed(7 downto 0);
signal SC_multOperand2 : signed(7 downto 0); signal SC_multOperand2 : signed(7 downto 0);
signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi
signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition
signal SR_sum : signed(19 downto 0); -- Accumulation register signal SR_sum : signed(19 downto 0); -- Accumulation register
signal SR_Y : signed(7 downto 0); -- filtered sample storage register signal SR_Y : signed(7 downto 0); -- filtered sample storage register
signal SR_readAddress : integer range 0 to 15; -- register files read address signal SR_readAddress : integer range 0 to 15; -- register files read address
begin begin
-- Low-pass filter provided with octave (or Matlab ;)) command -- Low-pass filter provided with octave (or Matlab ;)) command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6 -- fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
SR_coefRegister <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients -- Or python with (import signal from scipy and math)
to_signed(3, 8), -- [round(elem/math.sqrt(sum(signal.firwin(16, .001)**2)) * 2**6) for elem in signal.firwin(16, .001)]
to_signed(6, 8),
to_signed(10, 8), SR_coefRegister <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
to_signed(15, 8), to_signed(3, 8),
to_signed(20, 8), to_signed(6, 8),
to_signed(24, 8), to_signed(10, 8),
to_signed(26, 8), to_signed(15, 8),
to_signed(26, 8), to_signed(20, 8),
to_signed(24, 8), to_signed(24, 8),
to_signed(20, 8), to_signed(26, 8),
to_signed(15, 8), to_signed(26, 8),
to_signed(10, 8), to_signed(24, 8),
to_signed(6, 8), to_signed(20, 8),
to_signed(3, 8), to_signed(15, 8),
to_signed(2, 8) to_signed(10, 8),
); to_signed(6, 8),
to_signed(3, 8),
shift : process (_BLANK_) is to_signed(2, 8)
begin -- process shift );
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0')); shift : process (_BLANK_) is
elsif _BLANK_ begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
end if; SR_shiftRegister <= (others => (others => '0'));
end process shift; elsif _BLANK_
incr_address : process (_BLANK_) is end if;
begin end process shift;
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0; incr_address : process (_BLANK_) is
elsif _BLANK_ begin
if I_reset = '1' then -- asynchronous reset (active high)
end if; SR_readAddress <= 0;
end process incr_address; elsif _BLANK_
O_processingDone <= '1' when _BLANK_ ; end if;
end process incr_address;
SC_multOperand1 <= _BLANK_ ; -- 8 bits
SC_multOperand2 <= _BLANK_ ; -- 8 bits O_processingDone <= '1' when _BLANK_;
SC_MultResult <= _BLANK_ ; -- 16 bits
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum; SC_multOperand1 <= _BLANK_; -- 8 bits
SC_multOperand2 <= _BLANK_; -- 8 bits
sum_acc : process (_BLANK_) is SC_MultResult <= _BLANK_; -- 16 bits
begin SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
if I_reset = '1' then -- asynchronous reset (active high)
SR_sum <= (others => '0'); sum_acc : process (_BLANK_) is
elsif _BLANK_ begin
end if; if I_reset = '1' then -- asynchronous reset (active high)
end process sum_acc; SR_sum <= (others => '0');
elsif _BLANK_
store_result : process (_BLANK_) is end if;
begin end process sum_acc;
_BLANK_
store_result : process (_BLANK_) is
end process store_result; begin
_BLANK_
O_Y <= std_logic_vector(SR_Y);
end process store_result;
O_Y <= std_logic_vector(SR_Y);
end architecture arch_operativeUnit; end architecture arch_operativeUnit;
src/hdl/tb_firUnit.vhd
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------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Title : FirUnit -- Title : FirUnit
-- Project : -- Project :
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : operativeUnit.vhd -- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> -- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company : -- Company :
-- Created : 2018-04-11 -- Created : 2018-04-11
-- Last update: 2019-02-26 -- Last update: 2025-03-28
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: 8 bit FIR -- Description: 8 bit FIR
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2018 -- Copyright (c) 2018
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
-- 2018-04-11 1.0 jnbazin Created -- 2018-04-11 1.0 jnbazin Created
-- 2018-04-18 1.1 marzel Modified to add more test inputs -- 2018-04-18 1.1 marzel Modified to add more test inputs
-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering -- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -29,59 +29,59 @@ entity tb_firUnit is ...@@ -29,59 +29,59 @@ entity tb_firUnit is
end entity tb_firUnit; end entity tb_firUnit;
architecture archi_tb_firUnit of tb_firUnit is architecture archi_tb_firUnit of tb_firUnit is
component firUnit is component firUnit is
port ( port (
I_clock : in std_logic; I_clock : in std_logic;
I_reset : in std_logic; I_reset : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0); I_inputSample : in std_logic_vector(7 downto 0);
I_inputSampleValid : in std_logic; I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); O_filteredSample : out std_logic_vector(7 downto 0);
O_filteredSampleValid : out std_logic); O_filteredSampleValid : out std_logic);
end component firUnit; end component firUnit;
signal SC_clock : std_logic := '0'; signal SC_clock : std_logic := '0';
signal SC_reset : std_logic; signal SC_reset : std_logic;
signal SC_inputSample : std_logic_vector(7 downto 0); signal SC_inputSample : std_logic_vector(7 downto 0);
signal SC_inputSampleValid : std_logic:='0'; signal SC_inputSampleValid : std_logic := '0';
signal SC_filteredSample : std_logic_vector(7 downto 0); signal SC_filteredSample : std_logic_vector(7 downto 0);
signal SC_filteredSampleValid : std_logic; signal SC_filteredSampleValid : std_logic;
begin begin
SC_clock <= not SC_clock after 5 ns; SC_clock <= not SC_clock after 5 ns;
SC_reset <= '0', '1' after 19 ns, '0' after 57 ns; SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
-- Sample period = 20 clk period -- Sample period = 20 clk period
SC_inputSampleValid <= not SC_inputSampleValid after 100 ns; SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
-- Null signal followed by a Dirac and then an arbitrary sequence -- Null signal followed by a Dirac and then an arbitrary sequence
SC_inputSample <= "00000000", SC_inputSample <= "00000000",
"01111111" after 401 ns, "01111111" after 401 ns,
"00000000" after 601 ns, "00000000" after 601 ns,
"00100100" after 4201 ns, "00100100" after 4201 ns,
"01100100" after 4401 ns, "01100100" after 4401 ns,
"10100010" after 4601 ns, "10100010" after 4601 ns,
"11011011" after 4801 ns, "11011011" after 4801 ns,
"00001011" after 5001 ns, "00001011" after 5001 ns,
"10000000" after 5201 ns, "10000000" after 5201 ns,
"01111111" after 5401 ns, "01111111" after 5401 ns,
"10111010" after 5601 ns; "10111010" after 5601 ns;
-- the filter output on 8 bits is a sequence of signed numbers (with the assumption -- the filter output on 8 bits is a sequence of signed numbers (with the assumption
-- of rounding the output, so the accuracy can be slightly different depending -- of rounding the output, so the accuracy can be slightly different depending
-- on your final stage): -- on your final stage):
-- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8 -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
-- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116 -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
firUnit_1 : entity work.firUnit
port map ( firUnit_1 : entity work.firUnit
I_clock => SC_clock, port map (
I_reset => SC_reset, I_clock => SC_clock,
I_inputSample => SC_inputSample, I_reset => SC_reset,
I_inputSampleValid => SC_inputSampleValid, I_inputSample => SC_inputSample,
O_filteredSample => SC_filteredSample, I_inputSampleValid => SC_inputSampleValid,
O_filteredSampleValid => SC_filteredSampleValid); O_filteredSample => SC_filteredSample,
O_filteredSampleValid => SC_filteredSampleValid);
end architecture archi_tb_firUnit; end architecture archi_tb_firUnit;
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