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  • remove-reset
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  • ueee/sar-signal-audio/gr-vhdl-r24lelua/tp-filtre-etudiant-r24lelua
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Commits on Source (3)
......@@ -76,6 +76,9 @@ begin
SR_nextState <= WAIT_SAMPLE;
end if;
when STORE =>
SR_nextState <= PROCESSING_LOOP;
when PROCESSING_LOOP =>
if I_processingDone = '1' then
SR_nextState <= OUTPUT;
......
......@@ -45,7 +45,7 @@ entity operativeUnit is
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register
I_loadOutput : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done
O_filteredSample : out std_logic_vector(15 downto 0) -- filtered sample
);
......@@ -136,14 +136,16 @@ begin
if I_initAddress = '1' then
SR_readAddress <= 0;
elsif I_incrAddress = '1' then
SR_readAddress <= SR_readAddress + 1;
-- if SR_readAddress < 15 then
SR_readAddress <= SR_readAddress + 1;
-- end if;
end if;
end if;
end process incr_address;
-- Signal detecting that the next cycle will be the one
-- providing the last product used to compute the convolution
O_processingDone <= '1' when SR_readAddress = 15 else '0';
-- providing the last product used to compute the convolution.
O_processingDone <= '1' when SR_readAddress = 14 else '0';
-- Signals connected with multiplexers (SIMPLY inferred with table indices)
SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 16 bits
......@@ -170,6 +172,8 @@ begin
end if;
end if;
end process sum_acc;
-- Register to store the final result if the loadOuput is active
store_result : process (I_clock, I_reset) is
......@@ -177,8 +181,12 @@ begin
if I_reset = '1' then
SR_filteredSample <= (others => '0');
elsif rising_edge(I_clock) then
if I_loadY = '1' then
SR_filteredSample <= resize(SR_sum, SR_filteredSample'length);
if I_loadOutput = '1' then
if SC_addResult(14) = '1' then
SR_filteredSample <= SC_addResult(30 downto 15) + 1;
else
SR_filteredSample <= SC_addResult(30 downto 15);
end if;
end if;
end if;
end process store_result;
......@@ -186,3 +194,7 @@ begin
O_filteredSample <= std_logic_vector(SR_filteredSample);
end architecture arch_operativeUnit;