Bonus réussi

src/hdl/operativeUnit.vhd

@@ -53,7 +53,7 @@ entity operativeUnit is
 end entity operativeUnit;
 
 architecture arch_operativeUnit of operativeUnit is
-    type registerFile is array(0 to 15) of signed(15 downto 0);
+    type registerFile is array(0 to 32) of signed(15 downto 0);
     signal SR_coefRegister : registerFile;
 
 
@@ -64,7 +64,7 @@ architecture arch_operativeUnit of operativeUnit is
     signal SC_addResult     : signed(35 downto 0);    -- result of the accumulation addition
     signal SR_sum           : signed(35 downto 0);    -- Accumulation register
     signal SR_filteredSample: signed(15 downto 0);     -- filtered sample storage register
-    signal SR_readAddress   : integer range 0 to 15;  -- register files read address
+    signal SR_readAddress   : integer range 0 to 32;  -- register files read address
 
 
 
@@ -73,10 +73,10 @@ begin
     -- Low-pass filter provided with octave (or Matlab ;)) script :
     -- pkg load signal
     -- 
-    -- fs=44100
+    -- fs=48000
     -- fn=fs/2
-    -- n=16
-    -- fc=300
+    -- n=33
+    -- fc=1000
     -- fLP=fir1(n-1,fc/fn,"low");
     -- 
     -- function quantized_signal = quantize(signal, q)
@@ -95,23 +95,39 @@ begin
     --  endfor
     
     -- Table to store the filter coefficients obtained with the previous script
-    SR_coefRegister <= (to_signed(317,16),
-                        to_signed(476,16),
-                        to_signed(925,16),
-                        to_signed(1589,16),
-                        to_signed(2354,16),
-                        to_signed(3087,16),
-                        to_signed(3661,16),
-                        to_signed(3975,16),
-                        to_signed(3975,16),
-                        to_signed(3661,16),
-                        to_signed(3087,16),
-                        to_signed(2354,16),
-                        to_signed(1589,16),
-                        to_signed(925,16),
-                        to_signed(476,16),
-                        to_signed(317,16)
-                        );
+    SR_coefRegister <= (to_signed(-46,16),
+                        to_signed(-58,16),
+                        to_signed(-84,16),
+                        to_signed(-126,16),
+                        to_signed(-187,16),
+                        to_signed(-266,16),
+                        to_signed(-364,16),
+                        to_signed(-477,16),
+                        to_signed(-602,16),
+                        to_signed(-733,16),
+                        to_signed(-865,16),
+                        to_signed(-991,16),
+                        to_signed(-1105,16),
+                        to_signed(-1202,16),
+                        to_signed(-1274,16),
+                        to_signed(-1320,16),
+                        to_signed(31477,16),
+                        to_signed(-1320,16),
+                        to_signed(-1274,16),
+                        to_signed(-1202,16),
+                        to_signed(-1105,16),
+                        to_signed(-991,16),
+                        to_signed(-865,16),
+                        to_signed(-733,16),
+                        to_signed(-602,16),
+                        to_signed(-477,16),
+                        to_signed(-364,16),
+                        to_signed(-266,16),
+                        to_signed(-187,16),
+                        to_signed(-126,16),
+                        to_signed(-84,16),
+                        to_signed(-58,16),
+                        to_signed(-46,16));
     
     -- Process to describe the shift register storing the input samples
     shift : process (I_reset, I_clock) is
@@ -120,7 +136,7 @@ begin
             SR_shiftRegister <= (others => (others => '0'));
         elsif rising_edge(I_clock) then
             if(I_loadShift='1') then 
-                SR_shiftRegister(1 to 15) <= SR_shiftRegister(0 to 14);
+                SR_shiftRegister(1 to 32) <= SR_shiftRegister(0 to 31);
                 SR_shiftRegister(0) <= signed(I_inputSample);
                 
             end if;
@@ -138,7 +154,7 @@ begin
             if I_initAddress = '1' then 
                SR_readAddress <= 0;
             elsif I_incrAddress = '1' then
-              if SR_readAddress < 15 then 
+              if SR_readAddress < 32 then 
                 SR_readAddress <= SR_readAddress + 1;
               end if; 
             end if;            
@@ -149,7 +165,7 @@ begin
 
     -- Signal detecting that the next cycle will be the one
     -- providing the last product used to compute the convolution
-    O_processingDone <= '1' when SR_readAddress = 14 else '0';
+    O_processingDone <= '1' when SR_readAddress = 31 else '0';
 
     -- Signals connected with multiplexers (SIMPLY inferred with table indices)
     SC_multOperand1 <= SR_shiftRegister(SR_readAddress);             -- 16 bits
@@ -184,7 +200,11 @@ begin
             SR_filteredSample <= (others => '0');
         elsif rising_edge(I_clock) then
             if I_loadOutput = '1' then 
-                SR_filteredSample <= signed(SC_addResult(30 downto 15));
+                if SC_addResult(14)='1' then
+                    SR_filteredSample <= (SC_addResult(30 downto 15))+1;
+                elsif SC_addResult(14)='0' then
+                    SR_filteredSample <= (SC_addResult(30 downto 15));
+            end if;
             end if;
          end if;
                 

src/hdl/tb_firUnit.vhd

@@ -63,14 +63,14 @@ begin
     SC_inputSample <= "0000000000000000",
                         "0111111111111111" after 401 ns,
                         "0000000000000000" after 601 ns,
-                        "0000000000100100" after 4201 ns,
-                        "0000000001100100" after 4401 ns,
-                        "1111111110100010" after 4601 ns,
-                        "1111111111011011" after 4801 ns,
-                        "0000000000001011" after 5001 ns,
-                        "1111111110000000" after 5201 ns,
-                        "0000000001111111" after 5401 ns,
-                        "1111111110111010" after 5601 ns;
+                        "0000000000100100" after 18201 ns,
+                        "0000000001100100" after 18401 ns,
+                        "1111111110100010" after 18601 ns,
+                        "1111111111011011" after 18801 ns,
+                        "0000000000001011" after 19001 ns,
+                        "1111111110000000" after 19201 ns,
+                        "0000000001111111" after 19401 ns,
+                        "1111111110111010" after 19601 ns;
 
 
     -- the filter output on 16 bits is a sequence of signed numbers (with the  assumption