controle valide par simu et carte

docs/compte-rendu.md

@@ -8,6 +8,7 @@
 ## Questions
 
 ### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
+Il y a 
 
 
 ### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.

src/hdl/controlUnit.vhd

@@ -54,23 +54,46 @@ begin
   -- Process to describe the state register
   -- Current state is provide at the output of the register
   -- and is updated with the next state at each rising edge of clock
-  process (_BLANK_) is
+  process (I_reset,I_clock) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
-      SR_currentState <= _BLANK_
+      SR_currentState <= WAIT_SAMPLE;
     elsif rising_edge(I_clock) then     -- rising clock edge
-      _BLANK_
+      SR_currentState <= SR_nextState;
     end if;
   end process;
 
   -- Combinatorial process computing the next state which depends on
   -- the current state and on the inputs
-  process (_BLANK_) is
+  process (SR_currentState,I_inputSampleValid,I_processingDone) is
   begin
     case SR_currentState is
 
       when WAIT_SAMPLE =>
-        _BLANK_
+        if I_inputSampleValid = '1' then
+            SR_nextState <= STORE;
+        else SR_nextState <= WAIT_SAMPLE;
+        end if;
+        
+      when STORE =>      
+        SR_nextState <= PROCESSING_LOOP;
+        
+      when PROCESSING_LOOP =>
+        if I_processingDone = '1' then
+          SR_nextState <= OUTPUT;
+        else
+          SR_nextState <= PROCESSING_LOOP;
+        end if;
+            
+      when OUTPUT =>
+        SR_nextState <= WAIT_END_SAMPLE;
+        
+      when WAIT_END_SAMPLE =>
+        if I_inputSampleValid = '0' then
+          SR_nextState <= WAIT_SAMPLE;
+        else 
+          SR_nextState <= WAIT_END_SAMPLE;
+        end if;      
 
       when others => null;
     end case;
@@ -78,13 +101,13 @@ begin
 
   -- Rules to compute the outputs depending on the current state
   -- (and on the inputs, if you want a Mealy machine).
-  O_loadShift           <= '1' when _BLANK_ else '0';
-  O_initAddress         <= '1' when _BLANK_ else '0';
-  O_incrAddress         <= '1' when _BLANK_ else '0';
-  O_initSum             <= '1' when _BLANK_ else '0';
-  O_loadSum             <= '1' when _BLANK_ else '0';
-  O_loadOutput          <= '1' when _BLANK_ else '0';
-  O_FilteredSampleValid <= '1' when _BLANK_ else '0';
+  O_loadShift           <= '1' when SR_currentState = STORE else '0';
+  O_initAddress         <= '1' when SR_currentState = STORE else '0';
+  O_incrAddress         <= '1' when SR_currentState = PROCESSING_LOOP else '0';
+  O_initSum             <= '1' when SR_currentState = STORE else '0';
+  O_loadSum             <= '1' when SR_currentState = PROCESSING_LOOP else '0';
+  O_loadOutput          <= '1' when SR_currentState = OUTPUT else '0';
+  O_FilteredSampleValid <= '1' when SR_currentState = WAIT_END_SAMPLE else '0';
 
 
 

src/hdl/operativeUnit.vhd

@@ -114,36 +114,45 @@ begin
                         );
     
     -- Process to describe the shift register storing the input samples
-    shift : process (_BLANK_) is
+    shift : process (I_reset,I_clock) is
     begin  -- process shift
         if I_reset = '1' then           -- asynchronous reset (active high)
             SR_shiftRegister <= (others => (others => '0'));
-        elsif _BLANK_
-
+        elsif rising_edge(I_clock) then
+          if I_loadShift = '1' then
+            for i in 15 downto 1 loop
+              SR_shiftRegister(i) <= SR_shiftRegister(i-1);
+            end loop;
+            SR_shiftRegister(0) <= I_inputSample;
         end if;
+       end if;
     end process shift;
 
     -- Process to describe the counter providing the selection adresses
     -- of the multiplexers
-    incr_address : process (_BLANK_) is
+    incr_address : process (I_reset,I_clck) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_readAddress <= 0;
-        elsif _BLANK_
-
+        elsif rising_edge(I_clock) then
+            if I_initAddress = '1' then
+              SR_readAddress <= 0;
+            elsif I_incrAddress = '1' then
+              SR_readAddress <= SR_readAddress + 1;
+            end if; 
         end if;
     end process incr_address;
 
     -- Signal detecting that the next cycle will be the one
     -- providing the last product used to compute the convolution
-    O_processingDone <= '1' when _BLANK_;
+    O_processingDone <= '1' when SR_readAddress = '15' else '0';
 
     -- Signals connected with multiplexers (SIMPLY inferred with table indices)
-    SC_multOperand1 <= _BLANK_;             -- 16 bits
-    SC_multOperand2 <= _BLANK_;             -- 16 bits
+    SC_multOperand1 <= SR_shiftedRegister(SR_readAddress);             -- 16 bits
+    SC_multOperand2 <= SR_coefRegister(SR_readAddress);             -- 16 bits
 
     -- Multiplication of the operands
-    SC_MultResult   <= _BLANK_;             -- 32 bits
+    SC_MultResult   <= SC_multOperand1 * SC_multOperand2;             -- 32 bits
 
     -- Sum of the multiplication result and the accumulated value
     SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
@@ -151,18 +160,30 @@ begin
     -- Register to store the accumulated value if the loadSum is active
     -- It also reduces the width of the sum to fit to the input and output
     -- signal widths (be careful with truncating/rounding)
-    sum_acc : process (_BLANK_) is
+    sum_acc : process (I_clock,I_reset) is
     begin
         if I_reset = '1' then               -- asynchronous reset (active high)
             SR_sum <= (others => '0');
-        elsif _BLANK_
-        end if;
+        elsif rising_edge(I_clock) then
+          if I_initSum = '1' then
+            SR_sum <= (others => '0');
+          elsif I_loadSum = '1' then
+            SR_sum <= SC_addResult;
+          end if;
+        end if;cription⚓
     end process sum_acc;
 
     -- Register to store the final result if the loadOuput is active
     store_result : process (_BLANK_) is
     begin
-        _BLANK_
+        if I_reset = '1' then
+          SR_filteredSample <= (others => '0');
+        elsif rising_edge (I_clock) then
+          if I_loadY ='1' then
+            SR_filteredSample <= 
+          end if;
+        end if;
+          
 
     end process store_result;