mise à jour des noms de port et des signaux+coeff sur 16 bits+nouveau fichier...

mise à jour des noms de port et des signaux+coeff sur 16 bits+nouveau fichier verilog pour l'unité operative

src/constraints/NexysVideo_Master.xdc

@@ -11,7 +11,7 @@ set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
 ##LEDs
 #set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {LED[0]}]
 #set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {LED[1]}]
-#set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {LED[2]}]
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports { led2 }];
 set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports { led3 }];#[get_ports {LED[3]}]
 set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports { led4 }];#[get_ports {LED[4]}]
 set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports { led5 }];#[get_ports {LED[5]}]
@@ -31,7 +31,7 @@ set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports rstn]
 ##Switches
 set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports sw]
 #set_property -dict { PACKAGE_PIN F21  } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
-#set_property -dict { PACKAGE_PIN G21  } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
+set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS33} [get_ports { sw2 }]; #IO_L24P_T3_16 Sch=sw[2]
 set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS33} [get_ports { sw3 }]; #IO_L24N_T3_16 Sch=sw[3]
 set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS33} [get_ports { sw4 }]; #IO_L6P_T0_15 Sch=sw[4]
 set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS33} [get_ports { sw5 }]; #IO_0_15 Sch=sw[5]

src/hdl/audioProc.v

@@ -27,11 +27,13 @@ module audioProc(
 		 input 	rstn,
 		 input 	sw,
 		 //input [3:0]sw,
+		 input 	sw2,
 		 input 	sw3,
 		 input 	sw4,
 		 input 	sw5,
 		 input 	sw6,
 		 input 	sw7,
+		 output led2,
 		 output led3,
 		 output led4,
 		 output led5,
@@ -177,15 +179,17 @@ module audioProc(
    // Marz
    /////////////////////////////
    wire [23:0] inputLeftSample, inputRightSample,outputLeftSample,outputRightSample;
-   wire [4:0] configSw;
+   wire [5:0] configSw;
 
    assign inputLeftSample = in_audioL;
    assign inputRightSample = in_audioR;
-   assign configSw[0]=sw3;
-   assign configSw[1]=sw4;
-   assign configSw[2]=sw5;
-   assign configSw[3]=sw6;
-   assign configSw[4]=sw7;
+   assign configSw[0]=sw2;
+   assign configSw[1]=sw3;
+   assign configSw[2]=sw4;
+   assign configSw[3]=sw5;
+   assign configSw[4]=sw6;
+   assign configSw[5]=sw7;
+   assign led2=sw2;
    assign led3=sw3;
    assign led4=sw4;
    assign led5=sw5;

src/hdl/fir.vhd

@@ -5,13 +5,13 @@ use ieee.numeric_std.all;
 entity fir is
 
   generic (
-    dwidth : natural := 18;
+    dwidth : natural := 24;
     ntaps  : natural := 15);
 
   port (
     din          : in  std_logic_vector(dwidth-1 downto 0);
     dout         : out std_logic_vector(dwidth-1 downto 0);
-    config_sw    : in  std_logic_vector(4 downto 0);  --inutilise dans le TP majeure
+    config_sw    : in  std_logic_vector(5 downto 0);  --inutilise dans le TP majeure
     clk          : in  std_logic;
     rst          : in  std_logic;
     ce           : in  std_logic;  -- signal de validation de din a la frequence des echantillons audio
@@ -31,9 +31,9 @@ architecture myarch of fir is
     port (
       I_clock               : in  std_logic;
       I_reset               : in  std_logic;
-      I_inputSample         : in  std_logic_vector(7 downto 0);
+      I_inputSample         : in  std_logic_vector(15 downto 0);
       I_inputSampleValid    : in  std_logic;
-      O_filteredSample      : out std_logic_vector(7 downto 0);
+      O_filteredSample      : out std_logic_vector(15 downto 0);
       O_filteredSampleValid : out std_logic);
   end component firUnit;
 
@@ -42,33 +42,26 @@ architecture myarch of fir is
 
 begin  -- myarch
 
--- Quantization on 8 bits or less
+-- Quantization on 16 bits or less
 
--- When config_sw(3)='1', rounding is made by finding the nearest value else rounding is made by truncating.
-  prc : process (config_sw(3 downto 0), din) is
+-- When config_sw(0)='1', rounding is made by finding the nearest value else rounding is made by truncating.
+prc : process (config_sw(4 downto 0), din) is
+  variable w : integer;
   begin  -- process prc
-    case to_integer(unsigned(config_sw(3 downto 0))) is
-      when 0      => D_in <= din(dwidth-1 downto dwidth -8);
-      when 1      => D_in <= din(dwidth-1 downto dwidth -7)&'0';
-      when 2      => D_in <= din(dwidth-1 downto dwidth -6)&"00";
-      when 3      => D_in <= din(dwidth-1 downto dwidth -5)&"000";
-      when 4      => D_in <= din(dwidth-1 downto dwidth -4)&"0000";
-      when 5      => D_in <= din(dwidth-1 downto dwidth -3)&"00000";
-      when 6      => D_in <= din(dwidth-1 downto dwidth -2)&"000000"; 
-      when 7      => D_in <= din(dwidth-1)&"0000000";
-      when 8      => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -8);else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -8))+1); end if;
-      when 9      => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -7)&'0'; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -7))+1)&'0'; end if;
-      when 10      => if din(dwidth-7) = '0' then D_in <= din(dwidth-1 downto dwidth -6)&"00"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -6))+1)&"00"; end if;
-      when 11      => if din(dwidth-6) = '0' then D_in <= din(dwidth-1 downto dwidth -5)&"000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -5))+1)&"000"; end if;
-      when 12      => if din(dwidth-5) = '0' then D_in <= din(dwidth-1 downto dwidth -4)&"0000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -4))+1)&"0000"; end if;
-      when 13      => if din(dwidth-4) = '0' then D_in <= din(dwidth-1 downto dwidth -3)&"00000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -3))+1)&"00000"; end if;
-      when 14      => if din(dwidth-3) = '0' then D_in <= din(dwidth-1 downto dwidth -2)&"000000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -2))+1)&"000000"; end if;
-      when 15      => D_in <= din(dwidth-1)&"0000000";
-      when others => D_in <= (others => '0');
-    end case;
+    w:=to_integer(unsigned(config_sw(4 downto 1))); -- number of removed bits
+    D_in <= (others=> '0');
+    if(config_sw(0)='1') then
+        D_in(15 downto w) <= din(dwidth-1 downto dwidth-16+w); -- truncate
+    else
+        if(din(dwidth-16+w-1)='1') then
+            D_in(15 downto w) <= std_logic_vector(signed(din(dwidth-1 downto dwidth-16+w))+1); --round to the upper
+        else
+            D_in(15 downto w) <= din(dwidth-1 downto dwidth-16+w);--round to the lower
+        end if;
+    end if;
   end process prc;
   
---FIR over 8 bits
+--FIR over 16 bits
 
   firUnit_1 : entity work.firUnit
     port map (
@@ -83,8 +76,8 @@ begin  -- myarch
 -- End of FIR
 
 
-  dout(dwidth-1 downto dwidth -8) <= D_out when config_sw(4) = '1' else D_in;
-  dout(dwidth-9 downto 0)         <= (others => '0');
+  dout(dwidth-1 downto dwidth -16) <= D_out when config_sw(5) = '1' else D_in;
+  dout(dwidth-17 downto 0)         <= (others => '0');