feat

proj/AudioProc.cache/wt/project.wpc

 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:10
+6d6f64655f636f756e7465727c4755494d6f6465:11
 eof:

proj/AudioProc.cache/wt/xsim.wdf

 version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:241934075
+eof:2427094519

proj/AudioProc.sim/sim_1/behav/xsim/compile.bat

@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : AMD Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Tue Mar 18 22:56:13 +0100 2025
+REM Generated by Vivado on Wed Mar 26 08:48:39 +0100 2025
 REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
 REM
 REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/AudioProc.sim/sim_1/behav/xsim/compile.log

-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'firUnit'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'

proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat

@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : AMD Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Tue Mar 18 22:56:15 +0100 2025
+REM Generated by Vivado on Wed Mar 26 08:48:40 +0100 2025
 REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
 REM
 REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat

@@ -6,7 +6,7 @@ REM Filename    : simulate.bat
 REM Simulator   : AMD Vivado Simulator
 REM Description : Script for simulating the design by launching the simulator
 REM
-REM Generated by Vivado on Tue Mar 18 22:56:16 +0100 2025
+REM Generated by Vivado on Wed Mar 26 08:21:34 +0100 2025
 REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
 REM
 REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx

 
 { 
-    crc :  7733031991265798486  , 
+    crc :  724585655620237082  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" , 
     buildDate : "Nov  8 2024" , 

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini

@@ -26,8 +26,8 @@ INTERNAL_PROTOINST_FILTER=true
 CONSTANT_PROTOINST_FILTER=true
 VARIABLE_PROTOINST_FILTER=true
 SCOPE_NAME_COLUMN_WIDTH=220
-SCOPE_DESIGN_UNIT_COLUMN_WIDTH=160
-SCOPE_BLOCK_TYPE_COLUMN_WIDTH=304
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=304
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=160
 OBJECT_NAME_COLUMN_WIDTH=350
 OBJECT_VALUE_COLUMN_WIDTH=92
 OBJECT_DATA_TYPE_COLUMN_WIDTH=140

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log

-Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51894
+Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 58402
 Design successfully loaded
-Design Loading Memory Usage: 28580 KB (Peak: 28580 KB)
-Design Loading CPU Usage: 468 ms
+Design Loading Memory Usage: 28572 KB (Peak: 28572 KB)
+Design Loading CPU Usage: 452 ms