feat: implementing state machine and operative unit

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log

+Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 63467
+Design successfully loaded
+Design Loading Memory Usage: 28532 KB (Peak: 28532 KB)
+Design Loading CPU Usage: 452 ms

proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

+0.7
+2020.2
+Nov  8 2024
+22:36:57
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1741458025,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1741454254,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1741455408,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1741459119,vhdl,,,,tb_firunit,,,,,,,,