feat

proj/project_1/project_1.cache/sim/ssm.db

+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 19 10:36:40 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,

proj/project_1/project_1.cache/wt/project.wpc

 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:6
+6d6f64655f636f756e7465727c4755494d6f6465:7
 eof:

proj/project_1/project_1.cache/wt/xsim.wdf

 version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:2427094519
+eof:241934075

proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Wed Feb 26 12:08:10 CET 2025
+# Generated by Vivado on Wed Mar 19 12:10:31 CET 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log

-Vivado Simulator v2024.2.0
+Vivado Simulator v2024.1
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2024.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log 
-Using 2 slave threads.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log 
+Using 8 slave threads.
 Starting static elaboration
 Completed static elaboration
 INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Wed Feb 26 12:08:12 CET 2025
+# Generated by Vivado on Wed Mar 19 12:10:33 CET 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for simulating the design by launching the simulator
 #
-# Generated by Vivado on Wed Feb 26 12:07:21 CET 2025
+# Generated by Vivado on Wed Mar 19 12:10:35 CET 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -17,6 +17,6 @@
 # ****************************************************************************
 set -Eeuo pipefail
 # simulate design
-echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
-xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -view /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/proj/project_1/tb_firUnit_behav.wcfg -log simulate.log"
+xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -view /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/proj/project_1/tb_firUnit_behav.wcfg -log simulate.log
 

proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj

 # compile vhdl design source files
 vhdl xil_defaultlib  \
-"../../../../../src/hdl/controlUnit.vhd" \
-"../../../../../src/hdl/operativeUnit.vhd" \
-"../../../../../src/hdl/firUnit.vhd" \
-"../../../../../src/hdl/tb_firUnit.vhd" \
+"../../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../../src/hdl/firUnit.vhd" \
+"../../../../../../src/hdl/tb_firUnit.vhd" \
 
 # Do not sort compile order
 nosort

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt

+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log" 

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt

+Breakpoint File Version 1.0

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c

+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_35(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[27] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 27;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc",  (void **)funcTab, 27);
+	iki_vhdl_file_variable_register(dp + 14376);
+	iki_vhdl_file_variable_register(dp + 14432);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_xsimdir_location_if_remapped(argc, argv)  ;
+    iki_set_sv_type_file_path_name("xsim.dir/tb_firUnit_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/tb_firUnit_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/tb_firUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx

+
+{ 
+    crc :  1677624650740528615  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" , 
+    buildDate : "May 22 2024" , 
+    buildTime : "18:54:44" , 
+    linkCmd : "/usr/bin/gcc -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/tb_firUnit_behav/xsimk\"   \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel    -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file