feat

proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log

+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'

proj/project_1/project_1.xpr

@@ -60,7 +60,7 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="132"/>
+    <Option Name="WTXSimLaunchSim" Val="136"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>

src/hdl/controlUnit.vhd

@@ -84,11 +84,13 @@ BEGIN
           O_initAddress <= '1';
         ELSE
           SR_futurState <= PROCESS_B;
+          O_initAddress <= '0';
         END IF;
 
       WHEN PROCESS_A =>
-        O_sel <= "10";
         O_initAddress <= '0';
+        O_sel <= "10";
+        
         IF I_processingDoneA = '1' THEN
           SR_futurState <= CLELLAN;
           O_initAddress <= '1';

src/hdl/operativeUnit.vhd

@@ -283,7 +283,7 @@ BEGIN
       SC_multOperand1 <= SR_2A(SR_readAddress);
       SC_multOperand2 <= SR_coefRegisterA(SR_readAddress);
 
-      IF SR_readAddress = 0 THEN
+      IF SR_readAddress = 1 THEN
         O_processingDoneA <= '1';
         O_processingDoneB <= '0';
         O_processingDoneBL <= '0';