update control and operative unit; add new simulation images

src/hdl/controlUnit.vhd

@@ -137,6 +137,10 @@ begin
 --  O_FilteredSampleValid <= '1' when _BLANK_ ;
 
 
+  O_FilteredSampleValid <= '1' when SR_presentState=WAIT_END_SAMPLE else '0';
+
+
+
 
 
 

src/hdl/operativeUnit.vhd

@@ -41,14 +41,14 @@ entity operativeUnit is
     I_initSum        : in  std_logic;  -- Control signal to initialize the MAC register
     I_loadSum        : in  std_logic;  -- Control signal to load the MAC register;
     I_loadY          : in  std_logic;   -- Control signal to load Y register
-    O_processingDone : out std_logic;   -- Indicate that processing is done
+    O_processingDone : out std_logic;   -- Indicate that processing is done -- loadOutput
     O_Y              : out std_logic_vector(7 downto 0)   -- filtered sample
     );
 
 end entity operativeUnit;
 
 architecture arch_operativeUnit of operativeUnit is
-  type registerFile is array(0 to 15) of signed(7 downto 0);
+  type registerFile is array(0 to 15) of signed(7 downto 0); -- chiffres entiers
   signal SR_coefRegister : registerFile;
 
 
@@ -67,7 +67,7 @@ begin
 
 -- Low-pass filter provided with octave (or Matlab ;)) command
 --fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
-  SR_coefRegister <= (to_signed(2, 8),  -- ROM register used file to store FIR coefficients
+  SR_coefRegister <= (to_signed(2, 8),  -- ROM register used file to store FIR coefficients -- chiffres fractionnaires entre -1 et +1; premier chiffre est signée
                       to_signed(3, 8),
                       to_signed(6, 8),
                       to_signed(10, 8),
@@ -90,42 +90,60 @@ begin
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_shiftRegister <= (others => (others => '0'));
     elsif rising_edge(I_clock) then
-        if(I_loadShift = '1')then
-            SR_shiftRegister <= I_inputSample;
-        else
-            SR_shiftRegister(6 downto 0) <= SR_shiftRegister(7 downto 1);
-            SR_shiftRegister(7) <= I_inputSample;
-        end if;
+      if (I_loadShift = '1') then
+          SR_shiftRegister(1 to 15)  <= SR_shiftRegister(0 to 14);
+          SR_shiftRegister(0)  <= SIGNED(I_inputSample);
+      end if;
     end if;
   end process shift;
 
-  incr_address : process (_BLANK_) is
+  incr_address : process (I_reset, I_clock) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_readAddress <= 0;
-    elsif _BLANK_
+    elsif rising_edge(I_clock) then
+       if (I_initAddress = '1') then
+          SR_readAddress <= 0;
+       elsif (I_incrAddress = '1') then
+            if (SR_readAddress = 15) then
+                SR_readAddress <= 0;
+            else
+                SR_readAddress <= SR_readAddress + 1;
+            end if;
+       end if;
 
     end if;
   end process incr_address;
 
-  O_processingDone <= '1' when _BLANK_ ;
+  O_processingDone <= '1' when SR_readAddress = 15 else '0' ;
 
-  SC_multOperand1 <= _BLANK_ ;   -- 8 bits
-  SC_multOperand2 <= _BLANK_ ;    -- 8 bits
-  SC_MultResult   <= _BLANK_ ;  -- 16 bits
+  SC_multOperand1 <= SR_shiftRegister(SR_readAddress);   -- 8 bits
+  SC_multOperand2 <= SR_coefRegister(SR_readAddress);    -- 8 bits
+  SC_MultResult   <= SC_multOperand1*SC_multOperand2;  -- 16 bits
   SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
 
-  sum_acc : process (_BLANK_) is
+  sum_acc : process (I_reset, I_clock) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_sum <= (others => '0');
-    elsif _BLANK_
+    elsif rising_edge(I_clock) then
+        if (I_initSum= '1') then
+          SR_sum <= (others => '0');
+       elsif (I_loadSum = '1') then
+          SR_sum <= SC_addResult;
+       end if;
     end if;
   end process sum_acc;
 
-  store_result : process (_BLANK_) is
+  store_result : process (I_reset, I_clock) is
   begin
-      _BLANK_
+    if I_reset = '1' then               -- asynchronous reset (active high)
+      SR_Y <= (others => '0');
+    elsif rising_edge(I_clock) then
+       if (I_loadY= '1') then
+          SR_Y <= SC_addResult(14 downto 7);
+       end if;
+    end if;
 
   end process store_result;
 

vivado.jou

+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar  4 11:35:53 2025
+# Process ID: 51844
+# Current directory: /homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant-g24obuzo
+# Command line: vivado
+# Log file: /homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant-g24obuzo/vivado.log
+# Journal file: /homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant-g24obuzo/vivado.jou
+# Running On        :fl-tp-br-634
+# Platform          :Ubuntu
+# Operating System  :Ubuntu 24.04.2 LTS
+# Processor Detail  :Intel(R) Core(TM) i5-6600 CPU @ 3.30GHz
+# CPU Frequency     :1100.200 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory       :33538 MB
+# Swap memory       :4294 MB
+# Total Virtual     :37833 MB
+# Available Virtual :35155 MB
+#-----------------------------------------------------------
+start_gui
+open_project /homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant/tp-filtre-etudiant.xpr
+update_compile_order -fileset sources_1
+launch_simulation
+open_wave_config /homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant/tb_firUnit_behav.wcfg
+source tb_firUnit.tcl
+run 10 us
+save_wave_config {/homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant/tb_firUnit_behav.wcfg}
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {/homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant/tp-filtre-etudiant.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+current_hw_device [get_hw_devices xc7a200t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant/tp-filtre-etudiant.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/g24obuzo/Documents/UEG_MEDCONS/tp-filtre-etudiant-g24obuzo/tp-filtre-etudiant/tp-filtre-etudiant.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+close_hw_manager
+open_project /homes/g24obuzo/Documents/UEF_Integrated_Electronics/TP2_Sobel/sobel/sobel.xpr
+current_project tp-filtre-etudiant
+current_project sobel
+close_project
+close_sim