Skip to content
Snippets Groups Projects
Commit c6aebd56 authored by Florian HUYNH's avatar Florian HUYNH
Browse files

retrait des fichiers hld inutiles

parent 7dced045
No related branches found
No related tags found
No related merge requests found
Expand all Hide whitespace changes
Inline Side-by-side
src/hdl/TWICtl.vhd deleted 100644 → 0
+ 0
− 571
View file @ 7dced045
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWIUtils - Package
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-- Description: This package provides enumeration types for TWI (Two-Wire
-- Interface) bus status and error conditions.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
package TWIUtils is
type busState_type is (busUnknown, busBusy, busFree);
type error_type is (errArb, errNAck);
end TWIUtils;
package body TWIUtils is
end TWIUtils;
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWICtl - Behavioral
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-- Description: TWICtl is a reusabled Master Controller implementation of the
-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
-- FAST mode should also be theoretically possible, although it has not been
-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
-- buses. Slave-wait is also supported.
--
--
-- Dependencies: digilent.TWIUtils package - TWICtl.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
library digilent;
--use digilent.TWIUtils.ALL;
entity TWICtl is
----------------------------------------------------------------------------------
-- Title : Mode of operation
-- Description: The controller can be instructed to initiate/continue/stop a
-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
-- signals are synchronous to CLK and input signals must also be synchronous to
-- CLK. Signals are active-high.
-- Fast-track instructions (single byte transfer):
-- -put the TWI address on A_I
-- -if data is written put it on D_I
-- -assert STB_I
-- -when DONE_O pulse arrives, read data is present on D_O, if any
-- -repeat, or deassert STB_I
-- Detailed data transfer flow:
-- -when DONE_O is low, the controller is ready to accept commands
-- -data transfer can be initiated by putting a TWI slave address on the A_I
-- bus and providing a strobe (STB_I)
-- -the direction of data transfer (read/write) is determined by the LSB of the
-- address (0-write, 1-read)
-- -in case of a 'write' the data byte should also be present on the D_I bus
-- prior to the arrival of the strobe (STB_I)
-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
-- together with DONE_I high indicates success
-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
-- strobe can be sent; this is useful, when multiple bytes are sent/received
-- in a single transfer packet; for ex. for write transfers, a new byte can
-- be put on the D_I and STB_I provided;
-- -if no new strobe is provided, the transfer will end
-- -if a new strobe is provided, but the address changed, the current transfer
-- will end and a new will begin
-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
-- a strobe, the data byte will be written/read in a new packet; the advantage
-- of this is relevant only in multi-master buses: rather than waiting for the
-- current transfer to end and the bus to be released, a new transfer can be
-- initiated without giving up the control over the bus
----------------------------------------------------------------------------------
generic (CLOCKFREQ : natural := 50); -- input CLK frequency in MHz
port (
MSG_I : in STD_LOGIC; --new message
STB_I : in STD_LOGIC; --strobe
A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
DONE_O : out STD_LOGIC; --done status signal
ERR_O : out STD_LOGIC; --error status
CLK : in std_logic;
SRST : in std_logic;
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
SDA : inout std_logic; --TWI SDA
SCL : inout std_logic --TWI SCL
);
end TWICtl;
architecture Behavioral of TWICtl is
attribute fsm_encoding: string;
constant FSCL : natural := 400_000; --in Hz SCL clock frequency
constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
constant TSCL_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
constant TIMEOUT_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
type busState_type is (busUnknown, busFree, busBusy);
type error_type is (errNAck, errArb);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop : std_logic;
signal busState : busState_type := busUnknown;
signal errTypeR, errType : error_type;
signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
signal slaveWait, arbLost : std_logic;
signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
signal rSda, rScl : std_logic := '1';
signal subState : std_logic_vector(1 downto 0) := "00";
signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal int_Rst : std_logic := '0';
begin
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
SYNC_FFS: process(CLK)
begin
if Rising_Edge(CLK) then
dSda <= SDA;
ddSda <= dSda;
dScl <= SCL;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
TWISTATE: process(CLK)
begin
if Rising_Edge(CLK) then
if (int_Rst = '1') then
busState <= busUnknown;
elsif (fStart = '1') then --If START condition detected, bus is busy
busState <= busBusy;
elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
busState <= busFree;
end if;
end if;
end process;
TBUF_CNT: process(CLK)
begin
if Rising_Edge(CLK) then
if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
busFreeCnt <= TSCL_CYCLES;
elsif (dSCL = '1' and dSDA = '1') then
busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
end if;
end if;
end process;
----------------------------------------------------------------------------------
--Slave devices can insert wait states by keeping SCL low
----------------------------------------------------------------------------------
slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
'0';
----------------------------------------------------------------------------------
--If the SDA line does not correspond to the transmitted data while the SCL line
--is at the HIGH level the master lost an arbitration to another master.
----------------------------------------------------------------------------------
arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
'0';
----------------------------------------------------------------------------------
-- Internal reset signal
----------------------------------------------------------------------------------
RST_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle and SRST = '0') then
int_Rst <= '0';
elsif (SRST = '1') then
int_Rst <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
SCL_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (sclCnt = 0 or state = stIdle) then
sclCnt <= TSCL_CYCLES/4;
elsif (slaveWait = '0') then -- clock synchronization with other masters
sclCnt <= sclCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
TIMEOUT_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (timeOutCnt = 0 or slaveWait = '0') then
timeOutCnt <= TIMEOUT_CYCLES;
elsif (slaveWait = '1') then -- count timeout on wait period inserted by slave
timeOutCnt <= timeOutCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (CLK)
begin
if Rising_Edge(CLK) then
if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
dataByte <= loadByte; --latch address/data
bitCount <= 7;
--set flag so that we now what is the byte we are sending
if (latchData = '1') then
addrNData <= '0';
else
addrNData <= '1';
end if;
elsif (shiftBit = '1' and sclCnt = 0) then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
loadByte <= A_I when latchAddr = '1' else
D_I;
dataBitOut <= dataByte(dataByte'high);
D_O <= dataByte;
----------------------------------------------------------------------------------
-- Title: Current address register
-- Description: Stores the TWI slave address
----------------------------------------------------------------------------------
CURRADDR_REG: process (CLK)
begin
if Rising_Edge(CLK) then
if (latchAddr = '1') then
currAddr <= A_I; --latch address/data
end if;
end if;
end process;
rwBit <= currAddr(0);
----------------------------------------------------------------------------------
-- Title: Substate counter
-- Description: Divides each state into 4, to respect the setup and hold times of
-- the TWI bus.
----------------------------------------------------------------------------------
SUBSTATE_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle) then
subState <= "00";
elsif (sclCnt = 0) then
subState <= subState + 1;
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
state <= nstate;
rSda <= iSda;
rScl <= iScl;
DONE_O <= iDone;
ERR_O <= iErr;
errTypeR <= errType;
end if;
end process;
OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
begin
iSda <= rSda; --no change by default
iScl <= rScl;
iDone <= '0';
iErr <= '0';
errType <= errTypeR; --keep error type
shiftBit <= '0';
latchAddr <= '0';
latchData <= '0';
if (state = stStart) then
case (subState) is
when "00" =>
iSda <= '1';
--keep SCL
when "01" =>
iSda <= '1';
iScl <= '1';
when "10" =>
iSda <= '0';
iScl <= '1';
when "11" =>
iSda <= '0';
iScl <= '0';
when others =>
end case;
end if;
if (state = stStop or state = stStopError) then
case (subState) is
when "00" =>
iSda <= '0';
--keep SCL
when "01" =>
iSda <= '0';
iScl <= '1';
when "10" =>
iSda <= '1';
iScl <= '1';
when others =>
end case;
end if;
if (state = stRead or state = stSAck) then
case (subState) is
when "00" =>
iSda <= '1'; --this will be 'Z' on SDA
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stWrite) then
case (subState) is
when "00" =>
iSda <= dataBitOut;
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMAck) then
case (subState) is
when "00" =>
iSda <= '0'; -- acknowledge by writing 0
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMNAckStop or state = stMNAckStart) then
case (subState) is
when "00" =>
iSda <= '1'; -- not acknowledge by writing 1
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stSAck and sclCnt = 0 and subState = "01") then
if (dSda = '1') then
iDone <= '1';
iErr <= '1'; --not acknowledged
errType <= errNAck;
elsif (addrNData = '0') then
--we are done only when the data is sent too after the address
iDone <= '1';
end if;
end if;
if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
iDone <= '1'; --read done
end if;
if (state = stWrite and arbLost = '1') then
iDone <= '1'; --write done
iErr <= '1'; --we lost the arbitration
errType <= errArb;
end if;
if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
shiftBit <= '1';
end if;
if (state = stStart) then
latchAddr <= '1';
end if;
if (state = stSAck and subState = "11") then --get the data byte for the next write
latchData <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I,
SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (STB_I = '1' and busState = busFree and SRST = '0') then
nstate <= stStart;
end if;
when stStart =>
if (subState = "11" and sclCnt = 0) then
nstate <= stWrite;
end if;
when stWrite =>
if (arbLost = '1') then
nstate <= stIdle;
elsif (subState = "11" and sclCnt = 0 and bitCount = 0) then
nstate <= stSAck;
end if;
when stSAck =>
if (subState = "11" and sclCnt = 0) then
if (int_Rst = '1' or dataByte(0) = '1') then
nstate <= stStop;
else
if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
elsif (STB_I = '1') then
if (MSG_I = '1' or currAddr /= A_I) then
nstate <= stStart;
else
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
else
nstate <= stStop;
end if;
end if;
end if;
when stStop =>
if (subState = "10" and sclCnt = 0) then
nstate <= stIdle;
end if;
when stRead =>
if (subState = "11" and sclCnt = 0 and bitCount = 7) then --bitCount will underflow
if (int_Rst = '0' and STB_I = '1') then
if (MSG_I = '1' or currAddr /= A_I) then
nstate <= stMNAckStart;
else
nstate <= stMAck;
end if;
else
nstate <= stMNAckStop;
end if;
end if;
when stMAck =>
if (subState = "11" and sclCnt = 0) then
nstate <= stRead;
end if;
when stMNAckStart =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (subState = "11" and sclCnt = 0) then
nstate <= stStart;
end if;
when stMNAckStop =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (subState = "11" and sclCnt = 0) then
nstate <= stStop;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA <= 'Z' when rSDA = '1' else
'0';
SCL <= 'Z' when rSCL = '1' else
'0';
end Behavioral;
\ No newline at end of file
src/hdl/audioProc.v deleted 100644 → 0
+ 0
− 231
View file @ 7dced045
// -*- Mode: Verilog -*-
// Filename : audioProc.v
// Description : Audio processing project for IMTA A1S2 Labs in digital electronics, based on looper project by Digilent Inc.
// Author : Matthieu Arzel
// Created On : Fri Feb 8 11:16:35 2019
// Last Modified By: Matthieu Arzel
// Last Modified On: Fri Feb 8 11:16:35 2019
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns / 1ps
module audioProc(
input BTNL,
input BTNR,
input BTND,
input BTNC,
input BTNU,
// input JA1,
// input JA2,
// input JA3,
// input JA4,
input CLK100MHZ,
input rstn,
input sw,
//input [3:0]sw,
input sw3,
input sw4,
input sw5,
input sw6,
input sw7,
output led3,
output led4,
output led5,
output led6,
output led7,
inout scl,
inout sda,
output ac_mclk,
input ac_adc_sdata,
output ac_dac_sdata,
output ac_bclk,
output ac_lrclk
);
wire rst;
assign rst = ~rstn;
wire clk50;
parameter tenhz = 10000000;
wire [4:0] buttons_i;
assign buttons_i = {BTNU, BTNR, BTNC, BTND, BTNL};
reg [21:0] max_block=0;
wire set_max;
wire reset_max;
wire [4:0] buttons_db;//Debounced buttons
wire data_flag;
reg [23:0] sound_dataL;
reg [23:0] sound_dataR;
wire data_ready;
wire mix_data;
wire [21:0] block48KHz;
wire clk_out_100MHZ;
wire clk_out_200MHZ;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//// clk_wiz instantiation and wiring
//////////////////////////////////////////////////////////////////////////////////////////////////////////
clk_wiz_0 clk_1
(
// Clock in ports
.clk_in1(CLK100MHZ),
// Clock out ports
.clk_out1(clk_out_100MHZ),
.clk_out2(clk_out_200MHZ),
.clk_out3(ac_mclk),
.clk_out4(clk50),
// Status and control signals
.locked()
);
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//// Audio Initialization via TWI
//////////////////////////////////////////////////////////////////////////////////////////////////////////
audio_init initialize_audio
(
.clk(clk50),
.rst(rst),
.sda(sda),
.scl(scl)
);
wire [23:0] mixL;
wire [23:0] mixR;
debounce dbuttons(
.clock(clk_out_100MHZ),
.reset(rst),
.button(buttons_i),
.out(buttons_db)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////
// Audio input and output
////////////////////////////////////////////////////////////////////////////////////////////////////////
wire [23:0] in_audioL;
wire [23:0] in_audioR;
wire [23:0] out_audioL;
wire [23:0] out_audioR;
i2s_ctl audio_inout(
.CLK_I(clk_out_100MHZ), //Sys clk
.RST_I(rst), //Sys rst
.EN_TX_I(1), // Transmit Enable (push sound data into chip)
.EN_RX_I(1), //Receive enable (pull sound data out of chip)
.FS_I(4'b0101), //Sampling rate selector
.MM_I(0), //Audio controller Master mode select
.D_L_I(mixL), //Left channel data input from mix (mixed audio output)
.D_R_I(mixR), //Right channel data input from mix
.D_L_O(in_audioL), // Left channel data (input from mic input)
.D_R_O(in_audioR), // Right channel data (input from mic input)
.BCLK_O(ac_bclk), // serial CLK
.LRCLK_O(ac_lrclk), // channel CLK
.SDATA_O(ac_dac_sdata), // Output serial data
.SDATA_I(ac_adc_sdata) // Input serial data
);
reg lrclkD1=0;
reg lrclkD2=0;
always@(posedge(clk_out_100MHZ))begin
lrclkD1<=ac_lrclk;
lrclkD2<=lrclkD1;
end
reg pulse48kHz;
wire lrclkrise;
assign lrclkrise = lrclkD1 & ~lrclkD2;
reg[3:0] lrclkcnt=0;
always@(posedge(clk_out_100MHZ))begin
if (lrclkcnt==15)begin
pulse48kHz<=1;
lrclkcnt<=0;
end
else
pulse48kHz<=0;
if (lrclkrise)lrclkcnt<=lrclkcnt+1;
end
//////////////////////////////
//FIR filter
// Marz
/////////////////////////////
wire [23:0] inputLeftSample, inputRightSample,outputLeftSample,outputRightSample;
wire [4:0] configSw;
assign inputLeftSample = in_audioL;
assign inputRightSample = in_audioR;
assign configSw[0]=sw3;
assign configSw[1]=sw4;
assign configSw[2]=sw5;
assign configSw[3]=sw6;
assign configSw[4]=sw7;
assign led3=sw3;
assign led4=sw4;
assign led5=sw5;
assign led6=sw6;
assign led7=sw7;
fir #(24,16) leftFir
(
inputLeftSample,
outputLeftSample,
configSw,//config_sw, // : in std_logic_vector(3 downto 0); --inutilise dans le TP majeure
clk_out_100MHZ, // : in std_logic;
rst,// : in std_logic;
pulse48kHz// : in std_logic; -- signal de validation de din a la frequence des echantillons audio
);
fir #(24,16) rightFir
(
inputRightSample,
outputRightSample,
configSw,//config_sw, // : in std_logic_vector(3 downto 0); --inutilise dans le TP majeure
clk_out_100MHZ, // : in std_logic;
rst,// : in std_logic;
pulse48kHz// : in std_logic; -- signal de validation de din a la frequence des echantillons audio
);
assign mixL = buttons_db[2] ? in_audioL : outputLeftSample;
assign mixR = buttons_db[2] ? in_audioR : outputRightSample;
////////////////////////////////////////////////////////////////////////////////////////////////////////
//// Data in latch
////////////////////////////////////////////////////////////////////////////////////////////////////////
//Latch audio data input when data_flag goes high
always@(posedge(clk_out_100MHZ))begin
if (data_flag==1)begin
sound_dataL<=in_audioL;
sound_dataR<=in_audioR;
end
end
endmodule
src/hdl/audio_init.v deleted 100644 → 0
+ 0
− 246
View file @ 7dced045
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/08/2015 06:07:53 PM
// Design Name:
// Module Name: audio_init
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module audio_init(
input clk,
input rst,
inout sda,
inout scl
);
parameter stRegAddr1 = 4'b0000;
parameter stRegAddr2 = 4'b0001;
parameter stData1 = 4'b0010;
parameter stData2 = 4'b0011;
parameter stError = 4'b0100;
parameter stDone = 4'b0101;
parameter stIdle = 4'b0110;
parameter stDelay = 4'b0111;
parameter stPLLsecond = 4'b1111;
parameter INIT_VECTORS = 35;
parameter IRD = 1'b1;//init read
parameter IWR = 1'b0;//init write
parameter delay = 1000*24;
reg [3:0] state=stIdle;//State machine
reg [32:0] initWord;
reg initFbWe;
reg initEn;
reg [6:0]initA=0;
always @(posedge(clk))begin
case (initA)
0: initWord <= {IWR,31'h40150100};
1: initWord <= {IWR,31'h40160000};
2: initWord <= {IWR,31'h40170000};
3: initWord <= {IWR,31'h40F80000};
4: initWord <= {IWR,31'h40191300};
5: initWord <= {IWR,31'h402A0300};
6: initWord <= {IWR,31'h40290300};
7: initWord <= {IWR,31'h40F20100};
8: initWord <= {IWR,31'h40F97F00};
9: initWord <= {IWR,31'h40FA0300};
10: initWord <= {IWR,31'h40200300};
11: initWord <= {IWR,31'h40220100};
12: initWord <= {IWR,31'h40210900};
13: initWord <= {IWR,31'h4025E600};
14: initWord <= {IWR,31'h4026E600};
15: initWord <= {IWR,31'h40270300};
16: initWord <= {IWR,31'h40100100};
17: initWord <= {IWR,31'h40280000};
18: initWord <= {IWR,31'h4023E600};
19: initWord <= {IWR,31'h4024E600};
20: initWord <= {IWR,31'h400A0100};
21: initWord <= {IWR,31'h400B0500};
22: initWord <= {IWR,31'h400C0100};
23: initWord <= {IWR,31'h400D0500};
24: initWord <= {IWR,31'h400E0300};
25: initWord <= {IWR,31'h400F0300};
26: initWord <= {IWR,31'h401C2100};
27: initWord <= {IWR,31'h401D0000};
28: initWord <= {IWR,31'h401E4100};
29: initWord <= {IWR,31'h401F0000};
30: initWord <= {IWR,31'h40F30100};
31: initWord <= {IWR,31'h40F40000};
32: initWord <= {IWR,31'h40000F00};
33: initWord <= {IWR,31'h4002007D};//This sends the address of the PLL reg and the first config bits
34: initWord <= {IWR,31'h000C2101}; //These are the config bytes for the PLL reg
endcase
end
reg msg;//New message signal
reg stb;//Strobe signal
reg [7:0] data_i;//Data into TWI controller
wire [7:0] data_o;//Data out of TWI controller
wire done;
wire error;
wire errortype;
wire [7:0] twiAddr;//Address of device on TWI
reg [7:0] regData1;
reg delayEn=0;
integer delaycnt;
assign twiAddr[7:1] = 7'b0111011;
assign twiAddr[0] = 0;
TWICtl twi_controller(
.MSG_I(msg),
.STB_I(stb),
.A_I(twiAddr),
.D_I(data_i),
.D_O(data_o),
.DONE_O(done),
.ERR_O(error),
.CLK(clk),
.SRST(rst),
.SDA(sda),
.SCL(scl)
);
always @(posedge(clk))begin
if (delayEn==1)
delaycnt<=delaycnt-1;
else
delaycnt<=delay;
end
always @(posedge(clk))begin
if (state == stData1 && done == 1 && error != 1)
regData1 <= data_o;
end
always @(posedge(clk))begin
if (rst==1)begin
state<= stIdle;
delayEn <= 0;
initA <=0;
end
else begin
data_i <= "--------";
stb <= 0;
msg <= 0;
initFbWe <= 0;
case (state)
stRegAddr1: begin// Sends x40
if (done == 1)begin
if (error == 1)
state <= stError;
else
state <= stRegAddr2;
end
data_i <= initWord[31:24];
stb <= 1;
msg <= 1;
end
stRegAddr2: begin //Sends register address x40(XX)
if (done == 1)begin
if (error == 1)
state <= stError;
else
state <= stData1;
end
data_i <= initWord[23:16];
stb <= 1;
end
stData1: begin
if (done == 1) begin
if (error == 1)
state <= stError;
else begin
if (initWord[7:0]!=0)//If there is another byte, send it
state <= stData2;
else begin//no more bytes to send
initEn <= 1;
if (initA == INIT_VECTORS-1)//Done with all instructions
state <= stDone;
else //Only 3 bytes to send
state <= stDelay;
end
end
end
if (initWord[32] == 1) msg <= 1;
data_i <= initWord[15:8];
stb <= 1;
end
stData2: begin
if (done == 1)begin
if (error == 1)
state <= stError;
else begin
initEn<=1;
if (initWord[32] == 1) initFbWe <= 1;
if (initWord[23:16]== 8'h02)begin//If its the PLL register
initA<=initA+1;//Move initWord to the remaining PLL config bits
state <= stPLLsecond;//And send them
end
else if (initA == INIT_VECTORS-1)
state <= stDone;
else
state <= stDelay;
end
end
data_i <= initWord[7:0];
stb <= 1;
end
stPLLsecond:begin
if (done == 1)begin
if (error == 1)
state <= stError;
else
state <= stRegAddr2;
end
data_i <= initWord[31:24];
stb <= 1;
end
stError: begin
state <= stRegAddr1;
end
stDone: begin
end
stIdle:begin
state <= stRegAddr1;
end
stDelay:begin
delayEn <= 1;
if (delaycnt==0)begin
delayEn<=0;
if (initEn)begin
initA<=initA+1;
initEn <= 0;
end
state<=stRegAddr1;
end
end
endcase
end
end
endmodule
src/hdl/debounce.v deleted 100644 → 0
+ 0
− 108
View file @ 7dced045
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/13/2015 09:14:14 PM
// Design Name:
// Module Name: debounce
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debounce(
input clock,//100MHz clock
input reset,
input [4:0] button,//Buttons to debounce
output reg [4:0]out
);
reg [12:0] cnt0=0, cnt1=0, cnt2=0, cnt3=0, cnt4;
reg [4:0] IV = 0;
//parameter dbTime = 19;
parameter dbTime = 4000;
always @ (posedge(clock))begin
if(reset==1)begin
cnt0<=0;
cnt1<=0;
cnt2<=0;
cnt3<=0;
cnt4<=0;
out<=0;
end
else begin
if(button[0]==IV[0]) begin
if (cnt0==dbTime) begin
out[0]<=IV[0];
end
else begin
cnt0<=cnt0+1;
end
end
else begin
cnt0<=0;
IV[0]<=button[0];
end
if(button[1]==IV[1]) begin
if (cnt1==dbTime) begin
out[1]<=IV[1];
end
else begin
cnt1<=cnt1+1;
end
end
else begin
cnt1<=0;
IV[1]<=button[1];
end
if(button[2]==IV[2]) begin
if (cnt2==dbTime) begin
out[2]<=IV[2];
end
else begin
cnt2<=cnt2+1;
end
end
else begin
cnt2<=0;
IV[2]<=button[2];
end
if(button[3]==IV[3]) begin
if (cnt3==dbTime) begin
out[3]<=IV[3];
end
else begin
cnt3<=cnt3+1;
end
end
else begin
cnt3<=0;
IV[3]<=button[3];
end
if(button[4]==IV[4]) begin
if (cnt4==dbTime) begin
out[4]<=IV[4];
end
else begin
cnt4<=cnt4+1;
end
end
else begin
cnt4<=0;
IV[4]<=button[4];
end
end
end
endmodule
\ No newline at end of file
src/hdl/fir.vhd deleted 100644 → 0
+ 0
− 93
View file @ 7dced045
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fir is
generic (
dwidth : natural := 18;
ntaps : natural := 15);
port (
din : in std_logic_vector(dwidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0);
config_sw : in std_logic_vector(4 downto 0); --inutilise dans le TP majeure
clk : in std_logic;
rst : in std_logic;
ce : in std_logic; -- signal de validation de din a la frequence des echantillons audio
dbg_output_0 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
dbg_output_1 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
dbg_output_2 : out std_logic; --inutilise dans le TP majeure
dbg_output_3 : out std_logic; --inutilise dans le TP majeure
dbg_output_4 : out std_logic --inutilise dans le TP majeure
-- dout_valid : out std_logic
);
end fir;
architecture myarch of fir is
component firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0);
I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0);
O_filteredSampleValid : out std_logic);
end component firUnit;
signal D_in, D_out : std_logic_vector(7 downto 0);
begin -- myarch
-- Quantization on 8 bits or less
-- When config_sw(3)='1', rounding is made by finding the nearest value else rounding is made by truncating.
prc : process (config_sw(3 downto 0), din) is
begin -- process prc
case to_integer(unsigned(config_sw(3 downto 0))) is
when 0 => D_in <= din(dwidth-1 downto dwidth -8);
when 1 => D_in <= din(dwidth-1 downto dwidth -7)&'0';
when 2 => D_in <= din(dwidth-1 downto dwidth -6)&"00";
when 3 => D_in <= din(dwidth-1 downto dwidth -5)&"000";
when 4 => D_in <= din(dwidth-1 downto dwidth -4)&"0000";
when 5 => D_in <= din(dwidth-1 downto dwidth -3)&"00000";
when 6 => D_in <= din(dwidth-1 downto dwidth -2)&"000000";
when 7 => D_in <= din(dwidth-1)&"0000000";
when 8 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -8);else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -8))+1); end if;
when 9 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -7)&'0'; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -7))+1)&'0'; end if;
when 10 => if din(dwidth-7) = '0' then D_in <= din(dwidth-1 downto dwidth -6)&"00"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -6))+1)&"00"; end if;
when 11 => if din(dwidth-6) = '0' then D_in <= din(dwidth-1 downto dwidth -5)&"000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -5))+1)&"000"; end if;
when 12 => if din(dwidth-5) = '0' then D_in <= din(dwidth-1 downto dwidth -4)&"0000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -4))+1)&"0000"; end if;
when 13 => if din(dwidth-4) = '0' then D_in <= din(dwidth-1 downto dwidth -3)&"00000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -3))+1)&"00000"; end if;
when 14 => if din(dwidth-3) = '0' then D_in <= din(dwidth-1 downto dwidth -2)&"000000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -2))+1)&"000000"; end if;
when 15 => D_in <= din(dwidth-1)&"0000000";
when others => D_in <= (others => '0');
end case;
end process prc;
--FIR over 8 bits
firUnit_1 : entity work.firUnit
port map (
I_clock => clk,
I_reset => rst,
I_inputSample => D_in,
I_inputSampleValid => ce,
O_filteredSample => D_out,
O_filteredSampleValid => open);
-- End of FIR
dout(dwidth-1 downto dwidth -8) <= D_out when config_sw(4) = '1' else D_in;
dout(dwidth-9 downto 0) <= (others => '0');
end myarch;
src/hdl/firUnit.vhd deleted 100644 → 0
+ 0
− 109
View file @ 7dced045
-------------------------------------------------------------------------------
-- Title : firUnit
-- Project :
-------------------------------------------------------------------------------
-- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company :
-- Created : 2018-04-11
-- Last update: 2018-04-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 8 bit FIR
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-11 1.0 jnbazin Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity firUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic
);
end entity firUnit;
architecture archi_firUnit of firUnit is
component controlUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
I_inputSampleValid : in std_logic;
I_processingDone : in std_logic;
O_loadShift : out std_logic;
O_initAddress : out std_logic;
O_incrAddress : out std_logic;
O_initSum : out std_logic;
O_loadSum : out std_logic;
O_loadY : out std_logic;
O_FilteredSampleValid : out std_logic);
end component controlUnit;
component operativeUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
I_inputSample : in std_logic_vector(7 downto 0);
I_loadShift : in std_logic;
I_initAddress : in std_logic;
I_incrAddress : in std_logic;
I_initSum : in std_logic;
I_loadSum : in std_logic;
I_loadY : in std_logic;
O_processingDone : out std_logic;
O_Y : out std_logic_vector(7 downto 0));
end component operativeUnit;
signal SC_processingDone : std_logic;
signal SC_loadShift : std_logic;
signal SC_initAddress : std_logic;
signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic;
signal SC_loadSum : std_logic;
signal SC_loadY : std_logic;
begin
controlUnit_1 : entity work.controlUnit
port map (
I_clock => I_clock,
I_reset => I_reset,
I_inputSampleValid => I_inputSampleValid,
I_processingDone => SC_processingDone,
O_loadShift => SC_loadShift,
O_initAddress => SC_initAddress,
O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum,
O_loadSum => SC_loadSum,
O_loadY => SC_loadY,
O_FilteredSampleValid => O_FilteredSampleValid);
operativeUnit_1 : entity work.operativeUnit
port map (
I_clock => I_clock,
I_reset => I_reset,
I_inputSample => I_inputSample,
I_loadShift => SC_loadShift,
I_initAddress => SC_initAddress,
I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum,
I_loadSum => SC_loadSum,
I_loadY => SC_loadY,
O_processingDone => SC_processingDone,
O_Y => O_filteredSample);
end architecture archi_firUnit;
src/hdl/i2s_ctl.vhd deleted 100644 → 0
+ 0
− 296
View file @ 7dced045
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : i2s_ctl.vhd
-- MODULE NAME : I2S Control
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2012-25-01 Mihaita Nagy Created
-- 2.0 2012-02-04 Mihaita Nagy Remade the i2s_transmitter.vhd and
-- i2s_receiver.vhd into one new module.
-- 3.0 2014-12-02 HegbeliC Implemented edge detection for the
-- master mode and the division rate
-- for the different sampling rates
-------------------------------------------------------------------------------
-- KEYWORDS : I2S
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements the I2S transmitter and receiver
-- interface, with a 32-bit Stereo data transmission. Parameter
-- C_DATA_WIDTH sets the width of the data to be transmitted,
-- with a maximum value of 32 bits. If a smaller width size is
-- used (i.e. 24) than the remaining bits that needs to be
-- transmitted to complete the 32-bit length, are automaticaly
-- set to 0.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_ctl is
generic (
-- Width of one Slot (24/20/18/16-bit wide)
C_DATA_WIDTH: integer := 24
);
port (
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
EN_TX_I : in std_logic; -- Transmit enable
EN_RX_I : in std_logic; -- Receive enable
FS_I : in std_logic_vector(3 downto 0); -- Sampling rate slector
MM_I : in std_logic; -- Audio controler Master Mode delcetor
D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
-- OE_L_O : out std_logic; -- Left channel data output enable pulse
-- OE_R_O : out std_logic; -- Right channel data output enable pulse
-- WE_L_O : out std_logic; -- Left channel data write enable pulse
-- WE_R_O : out std_logic; -- Right channel data write enable pulse
D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
BCLK_O : out std_logic; -- serial CLK
LRCLK_O : out std_logic; -- channel CLK
SDATA_O : out std_logic; -- Output serial data
SDATA_I : in std_logic -- Input serial data
);
end i2s_ctl;
architecture Behavioral of i2s_ctl is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- Counter for the clock divider
signal Cnt_Bclk : integer range 0 to 31;
-- Counter for the L/R clock divider
signal Cnt_Lrclk : integer range 0 to 31;
-- Rising and Falling edge impulses of the serial clock
signal BCLK_Fall, BCLK_Rise : std_logic;
signal BCLK_Fall_int, BCLK_Rise_int : std_logic;
--signal BCLK_Fall_shot, BCLK_Rise_shot : std_logic;
-- Synchronisation signals for Rising and Falling edge
signal Q1R, Q2R, Q3R : std_logic;
signal Q1F, Q2F, Q3F : std_logic;
-- Internal synchronous BCLK signal
signal BCLK_int : std_logic;
-- Internal synchronous LRCLK signal
signal LRCLK_int : std_logic;
signal LRCLK : std_logic;
--
signal Data_Out_int : std_logic_vector(31 downto 0);
--
signal Data_In_int : std_logic_vector(31 downto 0);
--
signal D_L_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
--
signal D_R_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
--Internal synchronous OE signals
signal OE_R_int, OE_L_int : std_logic;
--Internal synchronous WE signals
signal WE_R_int, WE_L_int : std_logic;
-- Division rate for the BCLK and LRCLK
signal DIV_RATE : natural := 4;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Sampling frequency and data width decoder (DIV_RATE, C_DATA_WIDTH)
------------------------------------------------------------------------
BIT_FS: process(CLK_I)
begin
if rising_edge(CLK_I) then
case (FS_I) is
when x"0" => DIV_RATE <= 24;
when x"1" => DIV_RATE <= 16;
when x"2" => DIV_RATE <= 12;
when x"3" => DIV_RATE <= 8;
when x"4" => DIV_RATE <= 6;
when x"5" => DIV_RATE <= 4;
when x"6" => DIV_RATE <= 2;
when others => DIV_RATE <= 4;
end case;
end if;
end process;
------------------------------------------------------------------------
-- Serial clock generator (BCLK_O, BCLK_Fall, BCLK_Rise)
------------------------------------------------------------------------
SER_CLK: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Cnt_Bclk <= 0;
BCLK_int <= '0';
elsif Cnt_Bclk = ((DIV_RATE/2)-1) then
Cnt_Bclk <= 0;
BCLK_int <= not BCLK_int;
else
Cnt_Bclk <= Cnt_Bclk + 1;
end if;
end if;
end process SER_CLK;
-- Rising and Falling edges when in Slave mode
BCLK_Fall_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '1' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
BCLK_Rise_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '0' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
-- Falling edge selection with respect to Master Mode bit
BCLK_Fall <= BCLK_Fall_int;
-- Risesing edge selection with respect to Master Mode bit
BCLK_Rise <= BCLK_Rise_int;
-- Serial clock output
BCLK_O <= BCLK_int when EN_RX_I = '1' or EN_TX_I = '1' else '1';
------------------------------------------------------------------------
-- Left/Right clock generator (LRCLK_O, LRCLK_Pls)
------------------------------------------------------------------------
LRCLK_GEN: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Cnt_Lrclk <= 0;
LRCLK <= '0'; -- Left channel active by default
elsif BCLK_Fall = '1' then
if Cnt_Lrclk = 31 then -- half of frame (64 bits)
Cnt_Lrclk <= 0;
LRCLK <= not LRCLK;
else
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
end if;
end process LRCLK_GEN;
-- L/R clock output
LRCLK_O <= LRCLK when EN_TX_I = '1' or EN_RX_I = '1' else '0';
LRCLK_int <= LRCLK;
------------------------------------------------------------------------
-- Load in paralled data, shift out serial data (SDATA_O)
------------------------------------------------------------------------
SER_DATA_O: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; -- Left channel data by default
Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
elsif Cnt_Lrclk = 0 and BCLK_Rise = '1' then -- load par. data
if LRCLK_int = '1' then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_R_I;
Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
else
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I;
Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
end if;
elsif BCLK_Fall = '1' then -- shift out ser. data
Data_Out_int <= Data_Out_int(30 downto 0) & '0';
end if;
end if;
end process SER_DATA_O;
-- Serial data output
SDATA_O <= Data_Out_int(31) when EN_TX_I = '1' else '0';
------------------------------------------------------------------------
-- Shift in serial data, load out parallel data (SDATA_I)
------------------------------------------------------------------------
SER_DATA_I: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
Data_In_int <= (others => '0');
D_L_O_int <= (others => '0');
D_R_O_int <= (others => '0');
elsif Cnt_Lrclk = 0 and BCLK_Fall = '1' then -- load par. data
if LRCLK_int = '1' then
D_L_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
Data_In_int <= (others => '0');
else
D_R_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
Data_In_int <= (others => '0');
end if;
elsif BCLK_Rise = '1' then -- shift in ser. data
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
end process SER_DATA_I;
D_L_O <= D_L_O_int;
D_R_O <= D_R_O_int;
--------------------------------------------------------------------------
---- Output Enable signals (for FIFO)
--------------------------------------------------------------------------
-- OE_GEN: process(CLK_I)
-- begin
-- if rising_edge(CLK_I) then
-- if Cnt_Lrclk = 31 and BCLK_Fall = '1' then
-- if LRCLK_int = '1' then -- Right channel
-- OE_R_int <= '1';
-- else -- Left channel
-- OE_L_int <= '1';
-- end if;
-- else
-- OE_R_int <= '0';
-- OE_L_int <= '0';
-- end if;
-- end if;
-- end process OE_GEN;
-- OE_R_O <= OE_R_int when EN_TX_I = '1' else '0';
-- OE_L_O <= OE_L_int when EN_TX_I = '1' else '0';
--------------------------------------------------------------------------
---- Write Enable signals (for FIFO)
--------------------------------------------------------------------------
-- WE_GEN: process(CLK_I)
-- begin
-- if rising_edge(CLK_I) then
-- if Cnt_Lrclk = 1 and BCLK_Rise = '1' then
-- if LRCLK_int = '1' then -- Right channel
-- WE_R_int <= '1';
-- else -- Left channel
-- WE_L_int <= '1';
-- end if;
-- else
-- WE_R_int <= '0';
-- WE_L_int <= '0';
-- end if;
-- end if;
-- end process WE_GEN;
-- WE_R_O <= WE_R_int when EN_RX_I = '1' else '0';
-- WE_L_O <= WE_L_int when EN_RX_I = '1' else '0';
end Behavioral;
src/hdl/processingUnitIP.v deleted 100644 → 0
+ 0
− 3270
View file @ 7dced045
This diff is collapsed.
src/hdl/tb_firUnit.vhd deleted 100644 → 0
+ 0
− 87
View file @ 7dced045
This diff is collapsed.
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment