Code VHDL

src/hdl/controlUnit.vhd

@@ -49,33 +49,58 @@ architecture archi_operativeUnit of controlUnit is
 
 begin
 
-  process (_BLANK_) is
+  process (I_clock, I_reset) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
-      SR_presentState <= _BLANK_
+      SR_presentState <= WAIT_SAMPLE;
     elsif rising_edge(I_clock) then     -- rising clock edge
-      _BLANK_
+      SR_presentState <= SR_futurState;
     end if;
   end process;
 
-  process (_BLANK_) is
+  process (SR_presentState, I_inputSampleValid, I_processingDone) is
   begin
     case SR_presentState is
 
       when WAIT_SAMPLE =>
-        _BLANK_
-
+        if I_inputSampleValid = '1' then
+            SR_futurState <= STORE;
+        else
+            SR_futurState <= WAIT_SAMPLE;   
+        end if;     
+      
+      when STORE =>
+        SR_futurState <= PROCESSING_LOOP;
+      
+      when PROCESSING_LOOP =>
+        if I_processingDone = '1' then
+            SR_futurState <= OUTPUT;
+        else
+            SR_futurState <= PROCESSING_LOOP;
+        end if;
+                    
+      when OUTPUT =>
+        SR_futurState <= WAIT_END_SAMPLE;
+        
+      when WAIT_END_SAMPLE =>
+        if I_inputSampleValid = '0' then
+            SR_futurState <= WAIT_SAMPLE;
+        else
+            SR_futurState <= WAIT_END_SAMPLE; 
+        end if;
+        
       when others => null;
     end case;
   end process;
 
-  O_loadShift           <= '1' when _BLANK_ ;
-  O_initAddress         <= '1' when _BLANK_ ;
-  O_incrAddress         <= '1' when _BLANK_ ;
-  O_initSum             <= '1' when _BLANK_ ;
-  O_loadSum             <= '1' when _BLANK_ ;
-  O_loadY               <= '1' when _BLANK_ ;
-  O_FilteredSampleValid <= '1' when _BLANK_ ;
+  O_loadShift           <= '1' when SR_presentState = STORE             else '0';
+  O_initAddress         <= '1' when SR_presentState = STORE             else '0';
+  O_incrAddress         <= '1' when SR_presentState = PROCESSING_LOOP   else '0';
+  O_initSum             <= '1' when SR_presentState = STORE             else '0';
+  O_loadSum             <= '1' when SR_presentState = PROCESSING_LOOP   else '0';
+  O_loadY               <= '1' when SR_presentState = OUTPUT            else '0';
+  O_FilteredSampleValid <= '1' when SR_presentState = WAIT_END_SAMPLE   else '0';
+
 
 
 

src/hdl/operativeUnit.vhd

@@ -85,43 +85,66 @@ begin
                       to_signed(2, 8)
                       );
 
-  shift : process (_BLANK_) is
+  shift : process (I_clock, I_reset) is
   begin  -- process shift
     if I_reset = '1' then               -- asynchronous reset (active high)
-      SR_shiftRegister <= (others => (others => '0'));
-    elsif _BLANK_
-
+        SR_shiftRegister <= (others => (others => '0'));
+    elsif rising_edge(I_clock) then
+        if I_loadShift = '1' then
+            SR_shiftRegister(1 to 15)   <= SR_shiftRegister(0 to 14);
+            SR_shiftRegister(0)             <= signed(I_inputSample);
+        end if;
     end if;
   end process shift;
 
-  incr_address : process (_BLANK_) is
+  incr_address : process (I_clock, I_reset) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_readAddress <= 0;
-    elsif _BLANK_
-
+    elsif rising_edge(I_clock) then
+        if I_initAddress = '1' then
+            SR_readAddress <= 0;
+        elsif I_incrAddress = '1' then
+            if SR_readAddress < 15 then
+                SR_readAddress <= SR_readAddress + 1;
+            end if;
+        end if;
     end if;
   end process incr_address;
 
-  O_processingDone <= '1' when _BLANK_ ;
+  O_processingDone <= '1' when SR_readAddress >= 14 else '0';
 
-  SC_multOperand1 <= _BLANK_ ;   -- 8 bits
-  SC_multOperand2 <= _BLANK_ ;    -- 8 bits
-  SC_MultResult   <= _BLANK_ ;  -- 16 bits
+  SC_multOperand1 <= SR_shiftRegister(SR_readAddress) ;   -- 8 bits
+  SC_multOperand2 <= SR_coefRegister(SR_readAddress) ;    -- 8 bits
+  SC_MultResult   <= SC_multOperand1*SC_multOperand2 ;  -- 16 bits
   SC_addResult    <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
 
-  sum_acc : process (_BLANK_) is
+  sum_acc : process (I_clock, I_reset) is
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_sum <= (others => '0');
-    elsif _BLANK_
-    end if;
+    elsif rising_edge(I_clock) then
+        if I_loadSum = '1' then
+          SR_sum <= SC_addResult;
+        elsif I_initSum = '1' then
+          SR_sum <= (others => '0');
+        end if;
+     end if;
   end process sum_acc;
 
-  store_result : process (_BLANK_) is
+  store_result : process (I_clock, I_reset) is
   begin
-      _BLANK_
-
+    if I_reset = '1' then               -- asynchronous reset (active high)
+        SR_Y <= (others => '0');
+    elsif rising_edge(I_clock) then
+        if I_loadY = '1' then
+            if SC_addResult(6) = '1' then
+                SR_Y <= SC_addResult(14 downto 7) + 1;
+            else
+                SR_Y <= SC_addResult(14 downto 7);
+            end if;
+        end if;
+    end if;
   end process store_result;
 
   O_Y <= std_logic_vector(SR_Y);