Rendu v1

docs/compte-rendu.md

@@ -19,3 +19,51 @@ mainfont: sans-serif
 ## Remarques
 
 (Notez toute information qui vous semble pertinente)
+
+Succession de 3 filtres : FIR -> IIR -> FIR
+
+Pour notre filtre on calcule $x_k \rightarrow y_k \rightarrow z_k \rightarrow r_k$ avec $x_k$ l'entrée
+
+$$y_k = \sum_{i=0}^{94}x_{k-i} \times h_i$$
+
+$$z_k = \sum_{i=0}^2 y_{k-i}\times b_i - \sum_{i=1}^2 z_{k-i}\times a_i$$
+
+$$r_k = \sum_{i=0}^{10} z_{k-i} \times g_i$$
+
+## Code de chaque filtre
+
+### Baseline
+
+```
+Fs=500
+Fn=Fs/2
+fBaseLine=fir1(128, 5/Fn, 'high');
+```
+
+### Coupe-bande basique
+
+```
+Fs=500
+Fn=Fs/2
+f50Hz=fir1(100, [45 55]/Fn, 'stop');
+```
+
+### Pei Tseng Notch
+
+```
+Fs=500
+Fn=Fs/2
+[b, a]=pei_tseng_notch(50/Fn, 10/Fn);
+```
+
+### Parks McClellan
+
+```
+Fs=500
+Fn=Fs/2
+Fpass=50;
+Fstop=60;
+F    =[0 Fpass Fstop Fn]/(Fn)
+A    =[1 1 0 0]
+fLP  =remez(10, F, A)
+```
\ No newline at end of file

tp_vivado/proj/ECG.cache/sim/ssm.db

+################################################################################
+#                            DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 26 11:21:43 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+#                            DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,

tp_vivado/proj/ECG.cache/wt/project.wpc

+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:6
+eof:

tp_vivado/proj/ECG.cache/wt/xsim.wdf

+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:2427094519

tp_vivado/proj/ECG.hw/ECG.lpr

+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.2 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

tp_vivado/proj/ECG.ip_user_files/README.txt

+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

tp_vivado/proj/ECG.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho

+-- 
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+--  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+--   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock   Freq (MHz)    Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+  clk_in1           : in     std_logic;
+  -- Clock out ports
+  clk_out1          : out    std_logic;
+  clk_out2          : out    std_logic;
+  clk_out3          : out    std_logic;
+  clk_out4          : out    std_logic;
+  -- Status and control signals
+  reset             : in     std_logic;
+  locked            : out    std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+   port map ( 
+
+   -- Clock in ports
+   clk_in1 => clk_in1,
+  -- Clock out ports  
+   clk_out1 => clk_out1,
+   clk_out2 => clk_out2,
+   clk_out3 => clk_out3,
+   clk_out4 => clk_out4,
+  -- Status and control signals                
+   reset => reset,
+   locked => locked            
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/compile.bat

+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : AMD Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Wed Mar 26 12:19:40 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+call xvhdl  --incr --relax -prj tb_firUnit_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.bat

+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : AMD Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Wed Mar 26 12:19:42 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+call xelab  --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.log

+Vivado Simulator v2024.2.0
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2024.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.bat

+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : AMD Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Wed Mar 26 11:45:26 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+call xsim  tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.log

+Time resolution is 1 ps

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit.tcl

+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj

+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../src/hdl/firUnit.vhd" \
+"../../../../../src/hdl/tb_firUnit.vhd" \
+
+# Do not sort compile order
+nosort

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt

+--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log" 

tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt

+Breakpoint File Version 1.0