fin de seance 1

src/hdl/wave_generator.vhd

@@ -64,12 +64,12 @@ begin
             G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
             )
         port map (
-            I_clk    => ,
-            I_rst    => ,
-            I_u_d    => ,
-            O_val    => ,
-            O_last   => ,
-            O_middle =>
+            I_clk    => I_clk,
+            I_rst    => I_rst,
+            I_u_d    => S_u_d,
+            O_val    => S_addr,
+            O_last   => S_last,
+            O_middle => S_middle
             );
 
     -- Module C
@@ -94,10 +94,10 @@ begin
             G_fs => G_fs
             )
         port map (
-            I_clk      => ,
-            I_rst      => ,
-            I_addr     => ,
-            O_triangle =>
+            I_clk      => I_clk,
+            I_rst      => I_rst,
+            I_addr     => S_addr(C_addr_half_w-1 downto 0),
+            O_triangle => S_triangle_out_lut
             );
 
     -- Module E
@@ -108,10 +108,10 @@ begin
             G_fs => G_fs
             )
         port map (
-            I_clk       => ,
-            I_rst       => ,
-            I_addr      => ,
-            O_saw_tooth =>
+            I_clk       => I_clk,
+            I_rst       => I_rst,
+            I_addr      => S_addr,
+            O_saw_tooth => S_saw_tooth_out_lut
             );
 
     S_square <= ((G_N-1) => '0', others => '1');
@@ -119,12 +119,12 @@ begin
     -- Module F
     F_inst : entity work.module_F
         port map (
-            I_sel  => ,
-            I_din0 => ,
-            I_din1 => ,
-            I_din2 => ,
-            I_din3 => ,
-            O_dout =>
+            I_sel  => I_wave_sel,
+            I_din0 => S_sine_out_lut,
+            I_din1 => S_square,
+            I_din2 => S_saw_tooth_out_lut,
+            I_din3 => S_triangle_out_lut,
+            O_dout => S_wave_sample
             );
 
     -- Module G
@@ -133,17 +133,17 @@ begin
             G_N => G_N
             )
         port map (
-            I_din  => ,
-            O_dout =>
+            I_din  => S_wave_sample,
+            O_dout => S_opposite_wave_sample
             );
 
     -- Module H
     H_inst : entity work.module_H
         port map (
-            I_sel  => ,
-            I_din0 => ,
-            I_din1 => ,
-            O_dout =>
+            I_sel  => S_sign_sel,
+            I_din0 => S_wave_sample,
+            I_din1 => S_opposite_wave_sample,
+            O_dout => S_wave_value
             );
 
     -- Module I
@@ -152,10 +152,10 @@ begin
             G_N => G_N
             )
         port map (
-            I_clk  => ,
-            I_rst  => ,
-            I_din  => ,
-            O_dout =>
+            I_clk  => I_clk,
+            I_rst  => I_rst,
+            I_din  => S_wave_value,
+            O_dout => O_wav
             );
 
 end arch;

vivado.jou

+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May  5 14:16:34 2025
+# Process ID: 82280
+# Current directory: /homes/a24carne/Documents/SAR Audio/tp-synthe-etudiant-a24carne
+# Command line: vivado
+# Log file: /homes/a24carne/Documents/SAR Audio/tp-synthe-etudiant-a24carne/vivado.log
+# Journal file: /homes/a24carne/Documents/SAR Audio/tp-synthe-etudiant-a24carne/vivado.jou
+# Running On        :fl-tp-br-519
+# Platform          :Ubuntu
+# Operating System  :Ubuntu 24.04.2 LTS
+# Processor Detail  :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency     :900.921 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory       :16533 MB
+# Swap memory       :4294 MB
+# Total Virtual     :20828 MB
+# Available Virtual :18706 MB
+#-----------------------------------------------------------
+start_gui
+cd tp-synthe-etudiant-$USER/proj
+cd tp-synthe-etudiant-a24carne/proj
+ls
+cd proj
+ls
+source ./create_project.tcl
+update_compile_order -fileset sources_1
+launch_simulation
+source tb_module_B.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_C [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_C.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_D [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_D.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_E.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_F [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_F.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_H [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_H.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_G [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_G.tcl
+current_sim simulation_1
+close_sim
+close_sim
+close_sim
+close_sim
+close_sim
+close_sim
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_I [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_I.tcl
+current_sim simulation_7
+close_sim
+close_sim
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_runs impl_1 -jobs 6
+wait_on_run impl_1
+open_run impl_1
+launch_runs impl_1 -to_step write_bitstream -jobs 6
+wait_on_run impl_1
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {/homes/a24carne/Documents/SAR Audio/tp-synthe-etudiant-a24carne/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+current_hw_device [get_hw_devices xc7a200t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
+set_property PROGRAM.FILE {/homes/a24carne/Documents/SAR Audio/tp-synthe-etudiant-a24carne/proj/Synthe.runs/impl_1/audioProc.bit} [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]