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Commit de60aa66 authored by Edgar ROUSSEAU's avatar Edgar ROUSSEAU
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......@@ -8,10 +8,10 @@
## Questions
### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
### Deux processus sont utilisés, un séquentiel et un combinatoire, on les différencie grâce à leurs entrées : celles du processus séquentiel comprend une horloge et un reset.
### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
### La séquence renvoyé par la simulation est bien celle attendue, ce n'est pas une condition suffisante pour être sûr que la description VHDL est adapté mais donne tout de même pseudo validation.
### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
......
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......@@ -54,37 +54,68 @@ begin
-- Process to describe the state register
-- Current state is provide at the output of the register
-- and is updated with the next state at each rising edge of clock
process (_BLANK_) is
process (I_clock,I_reset) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_currentState <= _BLANK_
SR_currentState <= WAIT_SAMPLE;
elsif rising_edge(I_clock) then -- rising clock edge
_BLANK_
SR_currentState <= SR_nextState;
end if;
end process;
-- Combinatorial process computing the next state which depends on
-- the current state and on the inputs
process (_BLANK_) is
process (SR_currentState,I_processingDone, I_inputSampleValid ) is
begin
case SR_currentState is
when WAIT_SAMPLE =>
_BLANK_
when others => null;
if I_inputSampleValid = '1' then
SR_nextState <= STORE;
else
SR_nextState <= WAIT_SAMPLE;
end if;
when STORE =>
SR_nextState <= PROCESSING_LOOP;
when PROCESSING_LOOP =>
if I_processingDone = '1' then
SR_nextState <= OUTPUT;
else
SR_nextState <= PROCESSING_LOOP;
end if;
when OUTPUT =>
SR_nextState <= WAIT_END_SAMPLE;
when WAIT_END_SAMPLE =>
if I_inputSampleValid = '0' then
SR_nextState <= WAIT_SAMPLE;
else
SR_nextState <= WAIT_END_SAMPLE;
end if;
when others =>
SR_nextState <= WAIT_SAMPLE;
end case;
end process;
-- Rules to compute the outputs depending on the current state
-- (and on the inputs, if you want a Mealy machine).
O_loadShift <= '1' when _BLANK_ else '0';
O_initAddress <= '1' when _BLANK_ else '0';
O_incrAddress <= '1' when _BLANK_ else '0';
O_initSum <= '1' when _BLANK_ else '0';
O_loadSum <= '1' when _BLANK_ else '0';
O_loadOutput <= '1' when _BLANK_ else '0';
O_FilteredSampleValid <= '1' when _BLANK_ else '0';
O_loadShift <= '1' when SR_currentState = STORE else '0';
O_initAddress <= '1' when SR_currentState = STORE else '0';
O_incrAddress <= '1' when SR_currentState = PROCESSING_LOOP else '0';
O_initSum <= '1' when SR_currentState = STORE else '0';
O_loadSum <= '1' when SR_currentState = PROCESSING_LOOP else '0';
O_loadOutput <= '1' when SR_currentState = OUTPUT else '0';
O_FilteredSampleValid <= '1' when SR_currentState = WAIT_END_SAMPLE else '0';
......
......@@ -114,7 +114,7 @@ begin
);
-- Process to describe the shift register storing the input samples
shift : process (_BLANK_) is
shift : process (I_reset, I_clock, ) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));
......
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